RU2257003C1 - Controlled pulse shaper - Google Patents

Abstract

FIELD: digital pulse engineering.

SUBSTANCE: proposed device designed for shaping output pulses of desired length for each of three events, that is, signal front across first control input, signal zero level from closing button incorporating provision for chatter suppression, and detection of pulse skipping across signal pulse input has seven resistors 1 - 7, two capacitors 11, 18, button 10, first and second control inputs 12, 13, pulse input 14, AND gate 17, NOT gate 8, two NAND gates 9 - 16, NOT gate with open collector output 15, and pulse signal envelope detector 19. This pulse shaper can be used, for instance, as system reset pulse shaper of numeric control device.

EFFECT: enlarged functional capabilities.

1 cl, 1 dwg

Description

The invention relates to pulsed digital technology, is intended for generating output pulses with the required duration for each of three events (along the signal front at the first control input, at the zero signal level from the closing button with chatter suppression with a single signal at the first control input, when a gap is detected pulse or “freezing” (termination of change) of the signal at the pulse input when resolving by single signals at the first and second control inputs), and can be used, for example p, as a system reset pulse shaper (RESET (RST)) of a program control device (UPU) with non-volatile random access memory (RAM) of a serviced or unattended microcontroller or microprocessor system (M-system) of information processing and control that supports the hardware watchdog timer mode to restart the UPA when the application program M-system “hangs up”, designed taking into account the following basic principles [1]: program control, backbone information exchange, m muzzle of construction and capacity computing power.

The modern typical M-system contains a UPU module based on a microcontroller (MK) or microprocessor (MP), functionally-oriented controllers and modems modules for input / output of information during the interaction of the M-system with external objects (operator panel, event sensors in the control object, actuators, adjacent systems, etc.), a power supply unit and a system bus formed by control buses (ШУ), addresses (ША) and data (ШД), for the exchange of information between modules (functionally complete composition bubbled parts M-system) in the operation of M-system [2, p.14, Fig.1.1].

In the general case, the UPU module contains an autonomous memory, for example, a combined one (RAM + ROM + ROM), a computer, for example, containing an MC, a quartz resonator, and two capacitors to ensure operation of the internal MK clock generator [2, p. 63, Fig. 2.6a ], an internal trunk and ШУ inputs and outputs, ША outputs and a bi-directional ШД of a system trunk, transceivers and a trunk adapter for functionally oriented coupling of MK with internal and system trunks, and a system reset pulse shaper (it is not shown in [2]) A control calculator when a number of events, such as switching on and off the power supply circuit to the housing System Reset button.

When the supply voltage Ep is turned on, the pulse shaper generates a reset pulse RST, at the end of which the components of the M-system are brought into operation (they are reset, initialized and tested under the control of the UPU), and then the M-system generally performs several functions with time division management. These functions are usually implemented cyclically as interacting quasiparallel processes [2, pp. 18-34] on the time grid of the M-system with a certain elementary time interval, which is formed in the MC by the corresponding timer / counter in the internal pulse counting mode.

In the process of functioning, the M-system as a complex digital machine with random access memory and permanent memory is prone to failures, leading, in particular, to “freezing” of the UPA application program. In this regard, the watchdog is becoming increasingly popular with MK manufacturers. For example, in Atmel MK AT89S8252, created on the basis of the popular MCS-51 architecture, the watchdog timer when the equipment is turned on is initialized by writing the PS code [2: 0] of the timer period and the WDTRST enable / reset bit to the WMCON register and is used to generate a reset MK at the hardware and software level (with WDTRST = 1), if the application program performs uncontrolled actions, for example, it “hangs” [2, p. 107, 108].

However, the hardware-software watchdog timer built into the MK is useful, but in the general case it does not completely eliminate the “freezing” of the M-system, since when the WDTRST bit fails to reset, the watchdog timer is disabled and does not prevent the MK from “hanging” due to other failures . Failures arise as a result of internal and / or external interference, leading to functional malfunctions of the MK, which are completely eliminated when the MK is restarted by the reset signal RST. In addition, if the PD (or IDL) bit for controlling the micropower consumption mode (or idle) fails, the MK hangs altogether (or for the period of absence of interruption) [2, p. 94, 95], and exit from the mode microconsumption can be carried out only by applying to the input of an active pulse RST duration t _RST , determined by the restriction

In those applications of the M-system where power consumption is one of the main indicators of product quality, it is advisable to use MK in micro-consumption mode [3, p. 82].

In addition, in case of instantaneous failures of the M-system power supply, the contents of the internal RAM of the MK can be preserved using a low-power source (battery or battery) of the backup supply voltage Ер by interrupting the main power supply source Еп emergency by interrupting the inverse signal NAIP. To do this, the MK on the interrupt signal NAIP = 0 must reload into the internal RAM all the basic parameters of the interrupted operation process and set the PD bit in the PCON register for the transition to micropower consumption mode (Power down) [3, p. 83]. Consequently, with the introduction of the backup power supply Ер into the M-system, it is relatively easy to construct a VGA with non-volatile internal RAM of a modern AT89S8252 type MK. In this case, the MC is powered by a switching voltage source Ek, which operates according to the voltages Ep and Ep and is implemented, for example, according to the technical solution [4, p. 87, Fig. 5.16]. When the power supply is turned off or crashed, this event in the M-system is detected by a change in the NAIP signal from “1” to “0”, which starts the interrupt routine for transferring the microcontroller to micro-consumption mode at the power supply voltage of the microcontroller Ek≥4 V while maintaining the contents of the internal RAM with a subsequent decrease in voltage MK power supply up to Ek≥2 V. Each time the power supply unit of a functioning M-system is turned on, the MK is removed from the micro-power mode with full preservation of the contents of the internal RAM, if the reset pulse RST = 1 is formed not earlier than Ek Ek≥4 reaches level B [5, p.75].

Based on the foregoing, it can be said that when building a typical modern M-system for processing information, serviced with online access to the RESET button, and especially unattended with reset only when the power is turned on and access to the RESET button only during debugging is relevant the task of reliable automatic detection of “freezing” of the UPA application program and its restart, as well as the removal of the UPA from the micropower mode in the M-system with economical energy consumption and / or with the protection of the contents of the RAM UPU from a drop in the main supply voltage with instantaneous power supply failures.

Thus, the creation of a simple controllable system reset pulse generator with reliable hardware detection of both permitting the output of the UPA from the micropower mode and the “hang” of the UPU application program (for example, by detecting a pulse skip or “hang” at the pulse input of the signal generated by the UPA programmatically as a function of the time grid of the M-system operation in time) and generation of a reset pulse with the required duration (i.e., taking into account type (1) constraints) at each detection to technical task.

Formers, as components of modern electronic systems, usually include devices designed to convert input and / or internal signals - events with the appropriate parameters into output pulsed signals of the required duration normalized in amplitude and slope of the edges to control the subsequent components of the system [6, p.263-265].

It should be noted that on a modern element base, shapers, like pulsed digital devices, are preferably developed using logic elements of CMOS technology, which are more suitable for working in pulsed devices compared to TTLs due to their high input resistance, good temperature stability, and also the transfer characteristic, close to ideal [6, p.263]. From the point of view of digital circuitry, the proposed device refers to the “auxiliary” elements of digital nodes and devices [7, p.24-37], of which the following four groups of devices are known for generating pulses.

The first group includes button pulse shapers with the elimination of contact bounce:

- a circuit for eliminating contact bounce based on a trigger with asynchronous (or synchronous) reset and installation inputs and a single-pole switch to two positions [7, p.118, fig. 3.18: b (or c)];

- a pulse shaper [8] containing an RS trigger, two JK triggers, an I element, clock and control inputs, an output, two resistors and a two-pole single-pole switch, the contacts of which are connected to the RS trigger inputs connected via bias resistors to the bias voltage bus. The pulse shaper [8] operates so that with a logical signal “1” or “0” at the control input, for each switching of the switch at the output, it generates one clock pulse or a series of clock pulses, respectively;

- a device for eliminating the influence of contact bounce [9], comprising a switch, logical signal lines “0” and “1”, an RS trigger, a direct output connected to an inverse trigger reset input and its direct output, and an inverse output connected to a switching contact a switch, an inverse input of the trigger setting and its inverse output;

- a chatter suppression device [10], containing a closing button, three resistors, two capacitors, D trigger and an output that is a direct output of the trigger;

- a circuit for suppressing the bounce of a button with one pair of contacts [11, p. 55, Fig. 100], containing a button with one pair of contacts, two combinational elements of CMOS technology, two resistors, a capacitor and direct and inverse outputs;

- a circuit for suppressing contact bounce using a Schmitt trigger [12, p. 85, Fig. 2.41], containing a button with one pair of contacts, two resistors, a capacitor, an output and a Schmitt trigger, the output of which is the output of the device;

- a scheme for using a single vibrator to suppress the chatter of button contacts [12, p.119, Fig.3.36], containing a button with one pair of contacts, a resistor, an output and a single vibrator, the output of which is the output of the device.

The second group includes pulse shapers of the initial installation for power-up:

- MK48 initial installation diagram [3, p.27, Fig.2.7], performing the function of a signal combiner for turning on the power and from the button and containing a button with one pair of contacts, two resistors, a capacitor and an output connected to the first conclusions of the resistors and capacitor, the second terminal of which is connected to the common bus of the driver connected to the first contact of the button, the second contact of which is connected to the second terminal of the first resistor, the second terminal of the second resistor is connected to the bus of the power source of the driver;

- a pulse shaper of the initial installation for turning on the power [12, p.83, Fig.2.38], containing a resistor, a capacitor, a Schmitt trigger and an output connected through a Schmitt trigger with the first terminals of the resistor and capacitor, the second terminal of which is connected to the common bus of the former, the supply voltage bus of which is connected to the second terminal of the resistor.

The third group includes pulse shapers that envelope a series of pulses, each of which is designed to generate a digital signal “1” (or “0”) in the presence (or absence) of a pulse train at the input:

- a device for monitoring a pulse sequence [13], containing control and memory triggers, three AND elements, three inputs of three clock pulses, an input of a controlled pulse sequence and an output that is an inverse output of a memory trigger;

- a pulse shaper enveloping a series of pulses [14], containing a reference frequency generator, two keys, two triggers, a reversible counter, a pulse shaper, an input of a series of pulses and an output that is the output of the first trigger;

- shaper of the envelope signal of the sequence of input pulses [12, p. 116, the first (or second) option to start the AG3 single vibrator in Fig.3.33 with an explanation of Fig.3.35 g on p.118], containing a single vibrator with restart, the pulse sequence input connected to direct (or inverse) input of the start of a single vibrator, and the output, which is a direct output of a single vibrator;

- shaper of the envelope signal of the input signal at the triggers [12, p.139, Fig. 4.14], containing an element NOT, two triggers, an input of a pulse sequence connected through an element NOT with inverse asynchronous inputs of both triggers, the information input of the first of which is connected to the bus logical “1” of the shaper and inverse asynchronous inputs of the installation of both triggers, a clock input connected to the sync inputs of both triggers, and an output that is the inverse output of the second trigger, the information input of which is connected to the output the first trigger.

The fourth group includes a device for detecting pulse loss [15], designed to generate output pulses in case of loss of input pulses.

Based on the above “auxiliary” devices of the first, second and third (or fourth) groups, it is possible to build a device with the functions of the proposed one. However, such a device will repeat the shortcomings of its components, which are the narrow specialization or the limitations of their functional capabilities and hardware complexity when using them to build a controlled pulse shaper of a system reset of a modern M-system.

A device [10] for bounce suppression, comprising a closing button, a CMOS technology trigger, the direct output of which is the device output, three resistors, two capacitors, a supply voltage bus connected through the first resistor to the first output of the first capacitor and the first contact of the button, the second contact of which connected to the first output of the second resistor and the trigger sync input, the inverse output of which is connected through the third resistor to the information input of the trigger and the first output of the second capacitor, the second output to orogo connected to the second terminals of the first capacitor and the second resistor and the common bus device.

In the initial state, the button is open, the trigger is in the state X = 0 (or 1), the first capacitor is charged to the supply voltage EC1 = Ep, the trigger sync input is in the logical “0” state (the sync input through the second resistor is connected to the common bus), and the information the trigger input is in the NX state (where NX is the inversion of X) and the second capacitor is charged to a voltage of EC2≈En (or 0 V) at X = 0 (or 1). By pressing a button on the trigger sync input several pulses of contact bounce are generated during the time of _tinkling t _tear = (1-10) ms [7, p. 117]. On the first front of the first bounce pulse, the trigger switches to the opposite state, at the end of the bounce the first capacitor is discharged to a voltage of EC1≈0 V, and the second capacitor is charged to a voltage of EC2≈0 V (or Ep) at X = 1 (or X = 0). When the button is released, its bounce does not affect the trigger state, since the first capacitor is discharged to “0 V”, and at the end of the bounce the first capacitor is charged through the first resistance to the initial voltage EC1 = Ep. Thus, this device operates in such a way that at each press of a button, the trigger switches to the opposite state.

The main disadvantage of the device [10] is that, with relative hardware complexity, it performs only the function of a one-bit counter of button presses and it does not provide for the function of generating a single pulse when the power is turned on. This limits the use of such technical solutions as even the simplest devices for generating reset pulses when creating modern M-systems.

A device [15] is known that contains two AND elements, a delay element, a NOT element, a pulse sequence regenerator (formed by series-connected OR elements, a delay element and a shaper that performs the function of shortening the input signal in duration), an OR element, counter, decoder, the inputs of which connected to the outputs of the counter, the reset input of which is connected to the output of the first AND element, whose inputs are connected to the outputs of the delay element and the OR element, the pulse sequence input connected the first inputs of the regenerator and the OR element and connected through the element NOT to the first input of the second element And, the second input of which is connected to the input of the delay element and the output of the regenerator, the first pulse output connected to the output of the second element And, the second input of the regenerator and the counter counter input, and a second pulse output, which is the output of the decoder, which is connected to the second input of the OR element.

In the initial state, the counter is reset, each input pulse with a delay and shortening passes to the output of the regenerator and through the element DOES NOT inhibit the second element And, and in case of loss of a pulse in the input sequence, the second element And passes the pulse from the output of the regenerator, i.e. forms at the first output, the output pulse corresponding to the lost. These pulses are counted by the counter and, if the number of missed pulses reaches the threshold, then the decoder at the second output of the device generates a pulse that, through the OR element and the first AND element, resets the counter to the zero state.

The main disadvantage of the device [15] is that it, with considerable hardware complexity, has limited capabilities when performing its functions, since it does not detect pulse loss when a single signal “hangs” at the input of the device, since in this case the OR element of the regenerator is formed constant single signal blocking regeneration.

Of the known technical solutions, the closest to the proposed ones according to the principle of pulse formation and composition is the driver [16], which contains a common bus, a power supply bus, a pulse signal output, two resistors, elements of NOT and NAND technology of CMOS, a closing button, the first contact which is connected to the common bus of the driver, and the second contact of the button is connected to the first input of the NAND element and the first terminals of the first and second resistors, the second terminal of the first of which is connected to the power bus, and a capacitor, the first terminal which is connected to the inverse output of the driver and the output of the element NOT, the input of which is connected to the output of the element AND, the second input of which is connected to the second terminals of the capacitor and the second resistor.

Formally, the functioning of the shaper [16] as a whole can logically be described by the formula

NOX = NIX1 & NIX2,

where NOX is the inverse digital signal generated at the output of the former (i.e., at the output of the element NOT);

NIX1 and NIX2 - inverse digital signals, respectively, at the first and second inputs of the AND element;

& - operator of the logical operation “AND” in the language ABEL;

N is a synonym for the “!” Operator of the logical operation “NOT” in ABEL.

During the operation of the shaper, at the first input of the NAND element, the NIX1 signal repeats the position of the button (i.e., when the NIX1 = 1 button is not pressed, and when NIX1 = 0 is pressed), and at the second input of the N-HE element, the NIX2 signal with NIX1 = 1 is determined depending on the voltage ENIX2 = EC + ENOX (where EC is the voltage across the capacitor measured at the second terminal relative to its first terminal; ENOX is the voltage at the output of the driver), according to the relations

NIX2 = 0 for ENIX2 <E (+) or NIX2 = 1 for ENIX2> E (-),

where E (+) and E (-) are the thresholds of the shaper as a Schmitt trigger and the NOX signal is switched from “0” to “1” and from “1” to “0”, respectively.

In view of the foregoing, the operation of the shaper [16] can be described in detail as follows.

When the button is not pressed, the shaper [16] is in the zero stable state (NOS)

NUS = {ENIX2≈En, EC≈0 V, ENOX≈En, NIX1 = 1, NIX2 = 1, NOX = 1}.

When a button is pressed when it is first touched on the housing of its second contact at the first cut of the NIX1 signal, the output of the element DOES NOT occur as in the Schmitt trigger, the NOX output signal switches from “1” to “0” due to the setting of the ENIX2 voltage at the second input of the AND-NOT element <U (+), and during the bounce of the button, the capacitor and the first and second resistors connected in series form an integrating circuit, the input and output of which are connected to the supply voltage bus Ep and the second input of the AND-NOT element. The time constant R · C (where C is the capacitance of the capacitor, R = R1 + R2, where R1 and R2 are the resistances of the first and second resistors, respectively) of this circuit is chosen such that the formation of the output signal NOX = 0 does not affect the bounce when the button is pressed , since during the bounce ENIX2 <U (+). After the end of the bounce of the pressed button, the shaper [16] is set to the stable state of the pressed button (USN)

USNC = {ENIX2≈0 V, EC≈0 V, ENOX≈0 B, NIX1 = 0, NIX2 = 0, NOX = 0}.

When the button is released, the voltage ENIX2≈EC starts to increase, since the capacitor starts charging from the voltage Ep through the resistance R when the button is opened. Since the time constant C (R1 + R2) of the integrating circuit is chosen sufficiently large, the increasing voltage ENIX2 reaches the threshold E (+) of switching from “0” to “1” the output signal NOX of the driver as a Schmitt trigger only after the end of the rattling of the button. Thus, when the button is opened after the end of its bounce at NIX1 = 1 at some point in time “t”, the voltage ENIX2 (t) becomes equal to Е (+) ≈ Еп / 2, and the driver enters the zone of amplification of the positive increment dENIX2 (t) = ENIX2 (t) -E (+) on the second input of the AND-NOT element. Therefore, the appeared positive increment dENIX2 (t) causes an increased increase in the ENOX voltage, which, through the capacitor along the positive feedback loop, causes, as in the Schmitt trigger, an abrupt change in the ENOX voltage from ENOX≈0 B to ENOX≈Ep with the shaper switching [16], in in accordance with the first switching law (according to this law [17, p.20], for any final current charging or discharging the capacitor, the voltage across it cannot change stepwise), to the zero transition state (NPS) HHC = {ENIX2≈Eп / 2 + Ep, EC≈ + Ep / 2, ENOX≈ Ep, NIX1 = 1, NIX2 = 1, NO X = 1}, and then after about T = 3 · C · [IR (+) + OR] in the NCL of the unpressed button, where IK (+) is the input internal protective resistance of the NAND element on the second input from the input positive voltage ENIX2> Ep, OR - output internal resistance of the element NOT.

Thus, in the process of operation, the shaper [16] repeats the button position with the elimination of bounce so that, when the button is pressed, a digital inverse pulse NOX = 0 is generated, the duration of which corresponds to the button contact closure time, and the front (switching from “0” to “1”) is delayed relative to the opening of the button contacts for a time not less than the duration of the rattling of the button when opened.

The main drawback of the shaper [16] when applying it, for example, to construct the UPA of a modern M-information processing and control system based on MK or MP is the limited functionality of it, for example, it does not generate an output pulse when the power is turned on, but performs the only function of forming output inverse digital pulse NOX, which simulates the position of the button with the elimination of chatter.

The present invention solves the problem of comprehensively expanding the functionality of the driver by generating an output pulse with the required duration both along the signal front at the first control input (generated when the power is turned on or as a command to remove the UPA from the micro-power mode), and when the driver performs a hardware watchdog timer ( allowed by single signals at the first and second control inputs) as an output pulse generator when a pulse is skipped or “freezes” on pulsed input signal which is formed by the VGA hardware as a temporary work function M Grid system over time.

To achieve this technical result, a controllable pulse shaper containing a common bus, a power supply bus, a pulse signal output, two resistors, elements of NOT and NAND CMOS technology, a closing button, the first contact of which is connected to the common bus of the driver, and the second contact of the button connected to the first terminals of the first and second resistors, and a capacitor, additionally introduced third to seventh resistors, first and second control inputs, pulse input, output element NOT with open collector output ohm, which is connected to the first output of the third resistor and is the output of the direct pulse signal of the driver, an additional NAND element, an And element, the first input of which is connected to the output of the NAND element and the first terminal of the capacitor, the second terminal of which is connected to the second terminal of the first resistor and the first output of the fourth resistor, the second output of which through the element is NOT connected to the first input of the NAND element, an additional capacitor, the first output of which is connected to the output of the AND element, the input of the output element NOT and the first m the input of the additional AND-NOT element, the second input of which is connected to the second terminals of the second and third resistors, the second input of the AND-NOT element and the first control input of the driver, the second control input of which is connected through the fifth resistor to the power bus and is the third input of the additional AND element -NE, and a pulse envelope detector equipped with a mounting input connected to the output of an additional AND-NOT element, a pulse input, which is a pulse input of the driver, and an output that connects is connected to the first terminal of the sixth resistor, the second terminal of which is connected to the second terminal of the additional capacitor and the first terminal of the seventh resistor, the second terminal of which is connected to the second input of the AND element, and all logic elements additionally inserted into the former, possibly with the exception of the output element NOT, are elements CMOS technology.

The author is not aware of technical solutions containing features equivalent to distinctive features (the introduction of resistors from third to seventh, first and second control inputs, a pulse input, an output element NOT with an open collector output, an additional NAND element and a CMOS technology element AND, an additional capacitor and envelope detector of the pulse signal), which (compared with the prototype [16]) comprehensively expand the functionality of the driver by generating an output pulse with the required duration both on the signal front at the first control input (it is formed when the power is turned on or as a command to transfer the MK or MP from the micro power consumption mode to active mode), and when the shaper performs the function of a hardware watchdog timer (it is allowed by single signals at the first and second control inputs) in as an output pulse generator when a pulse is skipped or “hangs” at the pulse input of a signal that is formed in time by the MC or MP software as a function of the time grid of the M-systems s.

The drawing shows a functional diagram of the controlled pulse shaping containing a common bus, a power supply bus, a pulse signal output, resistors 1 through 7 7, element 8 NOT, element 9 NAND, closing button 10, the first contact of which is connected to a common bus shaper, and the second contact of the button 10 is connected to the first terminals of the first 1 and second 2 resistors, a capacitor 11, the first 12 and second 13 control inputs, a pulse input 14, the output element 15 is NOT with an open collector output, which is connected to the first output the third resistor 3 and is the output of the direct pulse signal of the driver, an additional element 16 AND-NOT, element 17 AND, the first input of which is connected to the output of element 9 AND-NOT and the first output of the capacitor 11, the second terminal of which is connected to the second terminal of the first resistor 1 and the first output of the fourth resistor 4, the second output of which through the element 8 is NOT connected to the first input of the element 9 AND NOT, an additional capacitor 18, the first output of which is connected to the output of the element 17 AND, the input of the output element 15 is NOT and the first input of the additional element 16 AND-NOT, the second input of which is connected to the second terminals of the second 2 and third 3 resistors, the second input of element 9 AND NOT and the first control input 12 of the driver, the second control input 13 of which is connected through the fifth resistor 5 to the power bus and is the third input of the additional element 16 AND-NOT, and the detector 19 of the envelope of the pulse signal, equipped with a mounting input connected to the output of the additional element 16 AND-NOT, a pulse input, which is a pulse input 14 of the shaper, and an output that is connected to the first terminal of the sixth resistor 6, the second terminal of which is connected to the second terminal of the additional capacitor 18 and the first terminal of the seventh resistor 7, the second terminal of which is connected to the second input of the AND element 17, and all logic elements of the driver, possibly with the exception of the output element 15 NOT, are elements CMOS technology.

The logic elements of the controlled pulse shaper are made on CMOS integrated circuits of the 1554 series (elements 8, 9, 16 and 17 are made on three of the four elements 2I-NOT of the LA3 chip and on two of the four elements 2I of the LA1 chip), operating in the temperature range from -45 ° С to + 85 ° С with a supply voltage Еп from +2 to +6 V at a constant current for each output up to 24 mA and an input current for each input from -1 to -11 μA [18, p.15 and p. 21 tab. 3.1]. In addition [18, p.18], 1554 series microcircuits are capable of operating with an output current of at least 75 mA and an output voltage of at least 3.85 V at Ep = 5.5 V for buses with a wave impedance of Z _o = 50 Ohms.

The pulse envelope detector 19 can be implemented on the basis of any of the above devices of the third group (i.e., a pulse shaper enveloping a series of pulses), and one of the possible options for the detector 19 (see drawing) contains resistors 20, 21, and 22, capacitors 23 and 24, diodes 25, 26 and 27, the installation input connected through a resistor 20 to the anode of the diode 25, a pulse input connected to the first output of the capacitor 23, the second output of which is connected through a resistor 21 to the anode of the diode 26 and the cathode of the diode 27, and an output connected to the cathodes of the diodes 25 and 26 and the first conclusions of the resistor 22 and the capacitor 24, the second conclusions of which are connected to the anode of the diode 27 and a common bus.

As diodes 25 ÷ 27 of the detector 19, for example, diodes of the 2D522B type, or three of the eight diodes of the diode array 2D627A, can be used.

In the general case, the digital signal X12 at the control input 12 is used as an inverse signal for the NAIP failure of the power supply voltage Еп (i.e., the transition of the signal X12 = NAIP from “0” to “1” is formed at the operating supply voltage Еп = (4, 5 ÷ 5.5) In the process of turning on the power supply of the M-system), as well as the command for the control unit (that is, upon the transition of the X12 signal from “1” to “0”, the control unit performs a subroutine for switching to micro power consumption mode to save energy ), and along the edge of the signal X12 (transition from “0” to “1”), the proposed driver generates a reset pulse RS T, at the end of which the UPA performs the subroutine from the micro-consumption mode.

It should also be noted that at present, in the simplest case, as a source of signal X12 = NAIP, one can use a NAIP signal conditioner for an emergency of a voltage source Еп power supply on a DALLAS Semicodactor chip type DS1233D-10, which is a driver of an inverse NAIP signal when the supply voltage deviates from + 5 V. This deviation is in the range from 4.25 V to 4.49 V, and the microcircuit contains a voltage divider with stable parameters in the operating temperature range (Vcc TOLERANCE AND BIAS), a reference voltage source (T.C. REFERENCE), compara torus, delay element (350 ms DELAY), resistor, MOS transistor, supply voltage input connected to the first output of the resistor and connected via a voltage divider to the non-inverting input of the comparator, the inverting input of which is connected to the output of the reference voltage source, common bus input connected with the drain of the transistor, and the output of the inverse pulse connected to the second output of the resistor and the source of the transistor, the gate of which through the delay element is connected to the output of the comparator.

The DS1233D-10 microcircuit operates in the temperature range from -40 ° C to + 85 ° C so that when the voltage Ep <7 V is turned on, it generates an inverse signal NAIP = 0 with a duration of (250 ÷ 450) ms and then switches to “ 1 ”and continuously monitors the voltage level Ep: the comparator compares the output voltage of the divider with the reference voltage of the reference voltage source and through the delay element controls the state of the key - MOS transistor. When the voltage Ep reaches the corresponding point in the range (from 4.25 V to 4.49 V), the NAIP signal at the output of the microcircuit switches from “1” to “0” in a time of no more than 100 ns, for a time of at least (250 ÷ 450) ms.

Further, the operation of the shaper is described using the provisions, notation, and design ratios defined in the following paragraphs.

1. A modified ABEL logical function description language is used, in which the operators “AND”, “OR” and “NOT” are designated “&”, “#” and “!” (Or “N”), respectively, with! NX = X where X is a logical variable equal to “0” or “1”.

2. Digital signals at the inputs 12, 13 and 14 of the shaper are denoted as X12, X13 and X14, respectively, and generated at the outputs of the logic elements 8, 9, 15, 16, 17 and the second contact of the button 10 connected to the first terminals of resistors 1 and 2 , denote by X8, NX9, X15, X16, NX17, and NX10, respectively, whereby the direct signal Xj (or the inverse signal NXj) at Xj = 0 (or NXj = 0) is modeled by the voltage Ej≈0 B, and at Xj = 1 (or NXj = 1) - voltage Ej≈Eп.

3. The analog voltages at resistors 1, 2, 6 and capacitors 11, 18, 23 and 24, respectively, denote how E1 is measured at the second output of resistor 1 relative to its first output, E2 is measured at the first output of resistor 2 relative to its second output, E6 is measured at the second terminal of the resistor 6 relative to its first terminal and E11 is measured at the second terminal of the capacitor 11 with respect to its first terminal, E 18 is measured at the second terminal of capacitor 18 with respect to its first terminal, E23 is measured at the second terminal of capacitor 23 with respect to e of the first output and E24 is measured at the first output of the capacitor 24 relative to its second output connected to a common bus.

The digital and analog signals at the junction of resistors 1 and 4 and capacitor 11 (or resistors 6 and 7 and capacitor 18) are denoted by NX4 and E4 (or NX7 and E7), respectively, taking into account thresholds E (+) and E (-) operation of element 8 (or element 17 on the second input with NX9 = 1) variables (NX4 and E4) and variables (NX7 and E7) are connected by the relations

in which the analog voltages E4 and E7 are determined by the formulas

4. Denote the resistance of the resistors 1-7, 20-22 and capacitance of the capacitors 11, 18, 23 and 24, respectively, through R1-R7, R20-R22, and C11, C18, C23 and C24.

Resistor 4 (or 7) is designed to limit the discharge current of capacitor 11 (or 18) flowing through the protective diode of the input of element 8 NOT (or the protective diode of the second input of element 17 AND) and resistor 4 (or 7) at the beginning or end of the pulse NX9 = 0 (or NX17 = 0). The resistances of these resistors are chosen equal to R4 = R7 = 300 Ohm, taking into account the protection against electric discharge [18, p.20, Fig. 3.12] using the organization of the inputs and outputs of the KR1554 microcircuits with a protective pair of diodes for each input and output [18, p.25, fig.3.24].

The input 13 is technological and is used only when debugging the UPA M-system from the stand, and in the normal mode, the input 13 is open and is in the state X13 = 1 due to the connection of this input to the voltage Ep through a resistor 5, the resistance of which is chosen equal to P5 = 2 kOhm .

Resistors 20 and 21 are designed to limit the pulse currents at the output of the element 16 and at the pulse input 14, respectively. The resistances of these resistors are chosen equal to R20 = R21 = 51 Ohms.

5. The capacitor 23 and the diodes 26 and 27 are used only when the driver is in watchdog mode with monitoring the time behavior of the input pulses X14. With X12 = 1 and NX 10 = 1 (i.e., with E12≈Ep≈ + 5 V and the unpressed button 10), this mode is performed at X13 = 1 and when a sequence of pulses X14 with a period of T14 = T14.0 + is received at input 14 T14.1, so X14 = 0 (or X14 = 1) during T14.0 (or T14.1).

6. Using the accepted notation, the operation of all logical elements of the shaper is described by the following logical functions

the key arguments NX4 and NX7 of which are completely determined by relations (2) and (3), respectively.

7. The digital signal NX9 (or NX 17) is generated using an integrating or shortening RC circuit connected by an output through a terminating resistor 4 (or 7) to the input of element 8 (or to the second input of element 17) and connected by a positive feedback loop through a capacitor 11 (or 18) with the output of element 9 (or 17).

In this case, the problem arises of estimating the response time Tc of the logic element 8 (or 17) when the signal at the input of the corresponding integrating or shortening circuit changes when the signal at the input of the circuit changes from “0 V” to voltage Ep or vice versa from Ep to “0 V”. This time Tc is determined by the time constant T = R · C of the circuit and the response threshold of the logic element, which for the CMOS element is close to half the supply voltage Ep [11, p. 58].

We denote by the input of element 8 (or by the second input of element 17 with NX9 = 1 at the first input) the thresholds for its operation by turning it on and off through E (+) and E (-), respectively, and

where dEy is the interval from E (+) to E (-), in which element 8 (or 17 with NX9 = 1 at the first input) is an inverting (or non-inverting) amplifier for changing the input voltage with a gain much greater than unity.

The response time Te, according to [17, p. 67, 68] and taking into account [11, p. 58] the proximity of the threshold (11) or (12) to the value of Ep / 2, is estimated by the formula

determining the time for the integrating (or shortening) circuit to change the output signal of the circuit from the initial level to a level that is half of the stepwise change in the input signal (or the active duration of the output pulse of the shortening circuit, measured at a level of half the amplitude).

8. The front or slice of any digital signal (direct or inverse) means the change in the logical state of this signal from “0” to “1” or from “1” to “0”, respectively.

Based on the foregoing, we will describe sequentially the operation of the driver when each of the following three events occurs: along the edge of the X12 signal at the first control input 12 when the M-system power supply is turned on, by the NX10 signal when the button 10 is closed and opened with chatter suppression when the signal X12 = 1 at the first control input 12, if a gap or “hang” (termination of change) is detected at the pulse input 14 of the signal X14 with NX10 = 1 and resolution by the signals X12 = 1 and X13 = 1 at the control inputs 12 and 13, respectively.

When you turn on the power supply of the M-system, the voltage Ep starts to increase monotonically and at Ep> 2 V and X12 = 0, the shaper is in the initial steady state (NLS)

and at Ep≈4.5 V, the signal X12 changes from “0” to “1” and, using the unit signals X8 =! NX4 and X12 = 1, element 9 generates a signal NX9 = 0, which passes through the elements 17 and 15 to the output of the former as pulse X15 = 1 reset RST. By the formula (14), taking into account the constraint (1), the durations of T9 and T17, the generated pulses NX9 and NX17, we define by the expressions

The process of generating a digital signal NX9 (or NX17) occurs by changing the voltage E11 (or E18) on the capacitor 11 (or 18), and at the initial moment of time “t = 0” after each switching of the signal NX9 (or NX17) from “1” in “0” or from “0” to “1”, the voltage E11 (t = 0) (or E18 (t = 0)), according to the first switching law [17, p.20], is equal to voltage E11 (or E18) to switching the signal NX9 (or NX17). Given this position, each switching of both the NX9 signal and the NX17 signal will be described below.

During T9, the fast phase (with a duration of approximately (3 · R4 · C11)) of the discharge of the capacitor C11 from the voltage E11 (t = 0) ≈-Ep to approximately “0 V” through the output of element 9, the first protective diode of the input of element 8 and resistor 4, and then during the remaining part of the duration T9, the slow phase of the monotonous charge of the capacitor 11 from the voltage E12≈Ep occurs through the resistance (R2 + R1) and the output of the element 9 at E9≈0 V so that at the end of T9 the voltage E4≈E11 reaches threshold E (+), element 8 enters the zone dEy (13), in which the series connection of elements 8 and 9 is They are amplified by a noninverting amplifier of a positive increment of the input voltage E4 with a gain much larger than unity. This, as in the Schmitt trigger, leads to the closure of the positive feedback of the output signal of element 9 to the input of element 8 through the capacitor 11 and resistor 4 and causes an avalanche-like switching of the signal NX9 = NX4 from “0” to “1” and voltage E4 from E4≈E (+) to Е4≈Е (+) + Еп, and then, during approximately (3 · R4 · C11), the discharge of the capacitor 11 from the voltage E11≈Е (+) to approximately “0 V” occurs through resistor 4 and the second protective diode input element 8, the voltage bus Ep.

During T17> T9, the monotonous charge of the capacitor 18 from the voltage E24≈E16≈En occurs through the resistor 6 and the output of the element 17 at E17≈0 V so that at the end of T17 the voltage E7≈E18 reaches the threshold E (+) at NX9 = 1, the loop of positive feedback of the output of element 17 to its second input through the capacitor 18 and resistor 7 is closed. This causes an avalanche-like switching of the NX17 signal from “0” to “1” and voltage E7 from E7≈E (+) to E7≈E (+) + Ep, and then occurs, approximately during the time (3 R7 · C18), the discharge of the capacitor 18 from the voltage E18≈E (+) ≈ Ep / 2 to approximately “0 V” through p the resistor 7, the second protective diode of the second input of the element 17, the voltage bus Ep.

Thus, after turning on the power and the end of the output pulse X15 =! NX17, the shaper appears (at X12 = 1, X13 = 0 or at X13 = 1 and if signal X14 is detected at pulse input 14, the detection condition of which will be determined below) in the steady state )

If the driver with X12 = 1 is in the control unit (18), then with each closure and opening of button 10 it works as follows.

The position of button 10 with R1 >> R2 is displayed by the digital signal NX10 so that button 10 with NX10 = 1 is not pressed, and with NX10 = 0 it is pressed. When the button 10 is pressed or released, the digital signal NX10 rattles for a time t the _{rattle of the} button 10, the duration of which, according to [7, p. 117], taking into account expressions (16) and (17), is determined by the relation

When the button 10 is pressed, the capacitor 11 and the resistor 1 form a shortening circuit (the input of the circuit is connected to the output of element 9 at E9 ≈ Ep, and the output through the resistor 4 to the input of element 8), and the voltage E4 starts to decrease, since the capacitor 11 starts to charge from voltage E9 ≈ Ep through resistor 1 and a closed button 10. Based on relation (19), the time constant (R1 · C11) is chosen such that the decreasing voltage E4 reaches the repeater switching threshold E (-) (formed at X12 = 1 by a serial connection of the input and output elements 8 and 9 of co respectively) after stopping the bounce of button 10 when pressed. At time t at E4 (t) = E (-) ≈Eп / 2, the follower (from elements 8 and 9) enters the amplification zone of the negative increment dE4 (t) = E4 (t) -E (-). Therefore, the appeared negative increment dE4 (t) causes an enhanced decrease in the voltage E9, which through the capacitor 11 and resistor 4 along the positive feedback circuit causes, as in the Schmitt trigger, a change in the voltage E9 from E9≈Ep to E9≈0 V and the formation of the output pulse X15 = ( ! NX17) = 1 with the former switching (after the discharge of the capacitor 11 from the voltage E11≈-Ep / 2 to about “0 V” and the charge of the capacitor 18 to about E24≈Ep) to the steady state of the pressed button (USHK).

When button 10 is released, the series connection of resistors 1 and 2 (i.e., a resistor with resistance (R1 + R2)) and capacitor 11 form an integrating circuit (the input of this circuit is connected to voltage E12≈Ep, and the output through resistor 4 to the repeater input (from elements 8 and 9), the voltage E4 begins to increase, since the capacitor 11 begins to be charged from the voltage E12≈Ep through the resistance (R1 + R2). The monotonically increasing voltage E4≈E11 reaches the threshold E (+) of switching the repeater from “0” to “1” after stopping the bounce of button 10 when opened. At time t at E4 (t) = E (+) ≈Eп / 2, the follower (from elements 8 and 9) enters the amplification zone of the positive increment dE4 (t) = E4 (t) -E (+) of voltage E4. Therefore the resulting positive increment dE4 (t) causes an increased increase in the voltage E9, which through the capacitor 11 and the resistor 4 along the positive feedback circuit causes, as in the Schmitt trigger, an abrupt switching of the voltage E9 from E9≈0V to E9≈En and the formation of signals NX17 = NX9 = 1 and X15 = (! NX17) = 0 with the former switching (after discharging each of the capacitors 11 and 18 to approximately “0 V”) in the control unit (18).

If the driver is in the control unit (18), then with NX9 = 1, X12 = 1, and X13 = 1, it works as a watchdog timer with the time monitoring of the behavior of voltage pulses E14 of signal X14, determined by the period T14 = T14.0 + T14.1 so that during T14.0 the voltage is E14≈0 V, and during T14.1 the voltage is E14≈Ep. Therefore, with the beginning of each edge of the signal X14 in voltage E14≈Ep over time

the capacitors 23 and 24 are charged through the resistance (R21 + Rd), respectively, to the voltages E23 and E24, defined by the expressions

where Rd≈ (10-1000) Ohm is the differential resistance of the diode 26;

E24 (t = 0) - voltage E24 at the moment of the pulse front X14;

ED26≈0.2 V is the voltage at the open diode 26 at the end of T3 (21).

With the beginning of each decay of the X14 signal at input 14 (i.e., at E14≈0 V and E16≈0 V) during the time T14.0, the capacitor 23 discharges to approximately “0 V”, and during the time (T14-Tz ) there is a discharge of the capacitor 24 from the voltage (23) and a change (dynamic increase and decrease) of the voltage E7 through the resistance R6 depending on the voltage difference [E24 (t) -E17] ≈ [E24 (t) -Ep] with a trend of voltage tracking E7 (t) (5) behind the changing voltage E24 (t), which during each period T14 initially increases during T3 (21) and then decreases during (T14-T3). The voltage E7 (t) when a pulse signal X14 is detected at input 14 is always greater than the threshold E (-), and when E7 (t) = E (-), the driver detects the disappearance of one pulse in the input sequence X14 (or “freezing”), marked by the formation one pulse X15 =! NX17 (or by shifting the shaper into the oscillator mode) with the formation of element 16 by signal NX17 = 0 of a single signal X16 = 1 (i.e. voltage E16≈Ep) of the detector 19 through the limiting resistor 20 and diode 25 to the original state E24≈Ep pulse detection signals X14.

Using the expressions NX7 (3), E7 (5), E (+) (11), E (-) (12) and T3 (21), we determine the condition for the detection of pulses X14 by the relation

and the condition for detecting the disappearance or “freezing” of pulses X14 by the ratio

where Tmax - the length of the detection time is a complex function Tmax = F [R6, R22, C18, C24, E (-)] of many variables and is estimated by the ratio

From the expressions T17 (17), E23 (22), E24 (23) and Tmax (26) it follows that the steady operation of the driver in the watchdog timer mode with tracking the pulse signal X14 can be provided with a margin by the choice of values (T14-Tz) and C23 based on ratios

In view of the above, with NX9 = X12 = X13 = 1, the shaper operates in time as a watchdog timer, starting from a certain point in time “t” of the dynamic state of pulse detection (DSOI)

at E17≈Ep, can be described as follows.

With the beginning of each edge of the signal X14 during the time T3 (21), the voltage of E14≈Ep is the charge of the capacitors 23 and 24 to the voltages E23 (22) and E24 (23), respectively. Then, with the beginning of each decay of the signal X14 during the time T14.0 at E14≈0 V, the discharge of the capacitor 23 occurs approximately to “0 V”, and the discharge of the capacitor 24, from the initial voltage (22), occurs during the time (T14-Tz) , i.e. for most of the period T14 pulse repetition rate X14. The change in voltage E7 (t) occurs continuously with tracking changes in voltage E24> E (-) during both T3 and (T14-T3). In this regard, in this mode, the current value of voltage E7 (t), depending on the duration (T14-Tz), is perceived by element 17 at the second input when condition (24) for detecting pulses X14 is satisfied as a digital signal NX7 = 1 (i.e. E7 (t)> E (-)), and if the condition (25) for detecting a gap (or “freezing”) of pulses X14 is satisfied, then at some point in time, the voltage E7 (t) decreases to the threshold voltage E (-) and through the capacitor 18 and the resistor 7 closes the positive feedback loop, the signal NX17 switches like an avalanche from “1” to “0”, and At the time T17 (17) at Е17≈0В, the switch passes to the single generation state (UGSS)

During the time T17 (17), the driver generates a single reset signal X15 =! NX17 = 1, and the voltage E7 (t) ≈18 (t) continuously increases due to the charge of the capacitor 18 from the voltage (E24-E17) ≈Ep through resistor 6, and at t = T17, the voltage E7 (t) becomes equal to E (+). A further increase in voltage E7 (t) along the positive feedback circuit through capacitor 18 and resistor 7 causes the NX17 signal to switch from “0” to “1” and return the device to DSOI (29). The further functioning of the driver is determined by the behavior of the signal X14 as a function of time, and when the signal “X14” hangs (that is, if the signal X14 = 0 or X14 = 1 remains constant in time), the driver switches to the oscillator mode. The self-oscillator mode is carried out as an alternation in the ring of the described formation processes NX17 = 0 during T17 (17) and NX17 = 1 during Tmax (26), and Tmax> T17.

The M-system interprets the output signal X15 = 1 as a reset pulse RST = 1, at the end of which it is initialized, tested and proceeds to perform its functions. After or during the initialization process, the control unit must begin to programmatically generate a pulse signal X14 according to the restriction (27) to support the functioning of the device in the DSOI (29) with NX9 = X12 = X13 = 1. With the correct functioning of the UPA, the period T14 of the pulse repetition frequency X14 must satisfy the conditions (24) and (27) of reliable detection by the pulse shaper X14.

When X13 = 0, the watchdog timer mode is disabled. This allows you to operate the M-system from the MK or MP emulator in a step-by-step mode during debugging.

Directly from the description of the prototype [16] and this controllable pulse former, it follows that, compared with the prototype, the proposed driver, thanks to its essential features, has significantly expanded functionality by generating an output pulse X15 with the required duration T17 (17) as the signal front X12 at the first control input (it is formed when the M-system power supply is turned on or as a command to remove the UPA from the micro-power mode), and when the shaper performs the appar mode watchdog timer (enabled by single signals X12 and X13 at the first 12 and second 13 control inputs) as an output pulse generator X15 when a pulse is skipped or “hangs” at pulse input 14 of signal X14 generated by the UPA programmatically in time as a function of the time network of operation M -systems.

Literature

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Claims (1)

A controlled pulse shaper containing a common bus, a power supply bus, a pulse signal output, two resistors, elements of NOT and NON-CMOS technology, a closing button, the first contact of which is connected to the common bus of the driver, and the second contact of the button is connected to the first terminals of the first and the second resistors, and a capacitor, characterized in that it further comprises resistors from third to seventh, the first and second control inputs, a pulse input, an output element NOT with an open collector output, which is connected to the first output of the third resistor and is the output of the direct pulse signal of the driver, an additional NAND element, an AND element, the first input of which is connected to the output of the NAND element and the first output of the capacitor, the second terminal of which is connected to the second terminal of the first resistor and the first terminal of the fourth resistor , the second output of which through the element is NOT connected to the first input of the AND element, an additional capacitor, the first output of which is connected to the output of the AND element, the input of the output element NOT and the first input of the additional the second AND-NOT element, the second input of which is connected to the second terminals of the second and third resistors, the second input of the AND-element and the first control input of the driver, the second control input of which is connected through the fifth resistor to the power supply bus and is the third input of the additional And NOT, and a pulse envelope detector equipped with a mounting input connected to the output of an additional AND-NOT element, a pulse input being a pulse input of the driver, and an output that is connected to the first the output of the sixth resistor, the second output of which is connected to the second output of the additional capacitor and the first output of the seventh resistor, the second output of which is connected to the second input of the AND element, and all the logic elements additionally inserted into the driver, possibly with the exception of the output element NOT, are CMOS technology elements.