RU2256288C1 - Pulse shaping device - Google Patents

Abstract

FIELD: digital pulse engineering.

SUBSTANCE: proposed device that can be used for shaping output pulses of desired length for each of three events (power turn-on, detection of input-signal pulse skipping or hanging [stop of changing] when detection is enabled in response to signal from closing button, including chatter suppression) provides for shaping output pulse during power turn-on and can function as hardware watch timer enabling generation of output pulse in case of skipping or hanging of input signal pulse. Device has first and second resistors 1, 2, closing button 4, capacitor 5, logical follower 6, inverted pulse signal output, common bus, and power supply bus. In addition, device has third resistor 3, NAND gate 7, first and second AND gates 8, 9, power turn-on and push-button signal integrator 10, pulse detector 11, pulse signal input 12, and control input 13.

EFFECT: enlarged functional capabilities.

1 cl, 1 dwg

Description

The invention relates to a pulsed digital technique, designed to generate output pulses with the required duration for each of the three events (when the power is turned on, by a signal from a closing button with chatter suppression, when a gap or “hang” (termination of change) of pulses of the input pulse signal is detected, when resolution is enabled) and can be used, for example, as a device for generating system reset pulses (RESET (RST)) of a microcontroller or microprocessor system (M-sys emy) with the function of the information processing and control hardware watchdog to restart application during a "freeze" M-system designed with the following basic principles: [1] the control software, the main information exchange capacity modular construction and processing power.

The modern typical M-system contains a module of a program control device (UPU), modules of functionally oriented controllers and modems for input / output of information during the interaction of the M-system with external objects (operator panel, event sensors in the control object, actuators, adjacent systems and etc.), a power supply unit and a system bus formed by control buses (ШУ), addresses (ША) and data (ШД), for exchanging information between modules (functionally complete components of the M-system em) in the process of its functioning [2, p.14, fig.1.1].

In the general case, the UPU module contains an autonomous memory, for example, a combined memory (RAM + ROM + ROM), a computer containing, for example, a microcontroller, a quartz resonator, and two capacitors to ensure the functioning of the internal clock generator of the microcontroller [2, p. 63, Fig. 2.6a] , an internal trunk and ШУ inputs and outputs, ША outputs and a bi-directional ШД of a system trunk, transceivers and a trunk adapter for functionally oriented interfacing of a microcontroller with an internal and system trunks, and a device GUT for generating a system reset pulses (in [2] is not shown) for controlling the calculator when a series of events such as switching on and off the power supply circuit to the housing System Reset button.

When the supply voltage Ep is turned on, the device for generating pulses generates a reset pulse RST, the duration of which (based on the data given, for example, in [3, p. 27, 28]) can be estimated by the relation

where t _y ≥ 90 ms is the voltage setting time Ep with an accuracy of about 10% after switching on;

t _RST0 ≥ 50 ms is the duration of the RST pulse at the end of t _y , which determines the minimum value of the real pulse duration RST when the supply voltage is turned on.

At the end of each RST pulse, the components of the M-system are brought into working condition (they are reset, initialized and tested under the control of the controller), and then the M-system generally performs several control functions with time separation. These functions are usually implemented cyclically as interacting quasi-parallel processes [2, pp. 18-34] on the time grid of the M-system with a certain elementary time interval, which is formed using the corresponding timer / counter of the microcontroller operating in the internal pulse counting mode. In the process of functioning, the M-system as a complex digital machine with random access memory and permanent memory is prone to failures, leading, in particular, to “freezing” of the UPA application program. In this regard, the watchdog is becoming increasingly popular among microcontroller manufacturers. For example, in the AT89S8252 microcontroller, when the equipment is turned on, the watchdog timer is initialized by writing the PS code [2: 0] to the WMCON register of the timer operation period and the WDTRST enable / reset bit and is intended to form the microcontroller reset at the software and hardware level (with WDTRST = 1) if the application program performs uncontrolled actions, for example, “hung up” [2, p. 107, 108].

However, the hardware-software watchdog timer built into the microcontroller is useful, but in the general case it does not completely eliminate the “freezing” of the M-system, since when resetting the WDTRST bit in the microcontroller due to interference, the microcontroller can continue to change the initialization due to interference and “freeze” " In addition, when the microcontroller (or idle) is controlled due to an interference in the PCON register of the PD (or IDL) bit, the microcontroller freezes altogether (either for the period of no interruption, or until the RST pulse arrives) [2, p. 94, 95], moreover, the exit from the micro-consumption mode can be carried out only by applying to the input of an active pulse RST of duration t _RST1 , determined by the restriction

Thus, when constructing a typical modern M-information processing system — serviced with online access to the RESET button and especially unattended with reset only when the power is turned on and access to the RESET button only during debugging — the problem of reliable automatic detection of “freezes” is relevant ”UPU application program and its restart. In this regard, the creation of a simple device for generating system reset pulses with reliable hardware detection of “freezing” of the UPA application program (for example, by detecting missing or “hanging” pulses in the input pulse signal generated by the UPU microcontroller programmatically as a function of the time grid of the M-system with the pulse repetition rate, which varies within certain limits) and the formation of reset pulses with the required duration (i.e., taking into account type (1) restrictions when the system power is turned on and type (2) constraints when generating reset pulses by a signal from a make-up button with chatter suppression or when an application “hangs” is detected) is an urgent technical task.

Shapers, as components of modern electronic systems, usually include devices designed to convert input and / or internal signals — events with corresponding parameters into output pulsed signals of the required duration normalized in amplitude and slope of the edges to control the subsequent components of the system [4, p. 263-265].

It should be noted that on a modern element base, shapers as pulse digital devices are preferably developed using logic elements of CMOS technology, which are more suitable for working in pulse devices compared to TTLs due to high input resistance, good temperature stability, and a transfer characteristic close to ideal [4, p.263].

From the point of view of digital circuitry, the proposed device relates to the "auxiliary" elements of digital nodes and devices [5 p.24-37], of which the following four groups of devices are known for generating pulses.

The first group includes button pulse shapers with the elimination of contact bounce:

- a circuit to eliminate contact bounce based on a trigger with asynchronous or synchronous reset and installation inputs and a single-pole switch to two positions [5, p.118, fig. 3.18: b or c];

- a pulse shaper [6], containing an RS-flip-flop, two JK-flip-flops, an And element, clock and control inputs, an output, two resistors and a two-pole single-pole switch, the contacts of which are connected to the inputs of the RS-flip-flop connected via resistors to the bus bias voltage, designed to generate at the output of one clock pulse (or series of clock pulses) for each switch switch and logic signal “1” (or “0”) at the control input;

- a device for eliminating the influence of contact bounce [7], comprising a switch, logic signal buses “0” and “1”, an RS trigger, a direct output connected to an inverse trigger reset input and its direct output, and an inverse output connected to a switching the contact of the switch, the inverse input of the installation of the trigger and its inverse output;

- a chatter suppression device [8], containing a closing button, three resistors, two capacitors, a D-trigger and an output, which is a direct output of the trigger;

- a circuit for suppressing the chatter of a button with one pair of contacts [9, p. 55, Fig. 100: a, b, c] contains a button with one pair of contacts, two combinational elements of CMOS technology, two resistors, a capacitor, and direct and inverse outputs;

- a circuit for suppressing contact bounce using a Schmitt trigger [10, p. 85, Fig. 2.41] contains a button with one pair of contacts, two resistors, a capacitor, an output and a Schmitt trigger, the output of which is the output of the device;

- the scheme of using a single vibrator to suppress the chatter of button contacts [10, p.119, Fig.3.36] contains a button with one pair of contacts, a resistor, an output and a single vibrator, the output of which is the output of the device.

The second group includes pulse shapers of the initial installation for power-up:

- MK48 initial installation diagram [3, p.27, Fig.2.7] performs the function of a signal combiner for turning on the power and from the button and contains a button with one pair of contacts, two resistors, a capacitor and an output connected to the first terminals of the resistors and capacitor, the second the output of which is connected to a common bus of the driver connected to the first contact of the button, the second contact of which is connected to the second terminal of the first resistor, the second terminal of the second resistor is connected to the bus of the power source of the driver;

- the pulse shaper of the initial installation for turning on the power [10, p. 83, Fig.2.38] contains a resistor, a capacitor, a Schmitt trigger and an output connected through a Schmitt trigger to the first terminals of the resistor and capacitor, the second terminal of which is connected to the common shaper bus, the bus the supply voltage of which is connected to the second terminal of the resistor.

The third group includes pulse shapers that envelope a series of pulses, each of which is designed to generate a digital signal “1” (or “0”) in the presence (or absence) of a pulse train at the input:

- a device for monitoring a pulse sequence [11], containing control and memory triggers, three AND elements, three inputs of three clock pulses, an input of a controlled pulse sequence and an output that is an inverse output of a memory trigger;

- a pulse shaper enveloping a series of pulses [12], containing a reference frequency generator, two keys, two triggers, a reversible counter, a pulse shaper, an input of a series of pulses and an output that is the output of the first trigger;

- the shaper of the envelope signal of the sequence of input pulses [10: p.116, the first (or second) option to start the AGZ single-vibrator in Fig.3.33 with an explanation of Fig.3.35g on p.118] contains a one-shot with restart, the pulse sequence input connected to direct (or inverse) a single-shot trigger input, and an output that is a direct single-vibrator output;

- the shaper of the envelope signal of the input signal at the triggers [10, p.139, Fig. 4.14] contains an element NOT, two triggers, an input of a pulse sequence connected through an element NOT with inverse asynchronous reset inputs of both triggers, the information input of the first of which is connected to the bus logical “1” of the shaper and inverse asynchronous inputs of the installation of both triggers, a clock input connected to the sync inputs of both triggers, and an output that is the inverse output of the second trigger, the information input of which is connected to Odom first trigger.

The fourth group includes a device for detecting pulse loss [13], designed to generate output pulses in case of loss of input pulses.

Based on the above “auxiliary” devices of the first, second and third (or fourth) groups, it is possible to build a device with the functions of the proposed one. However, such a device will repeat the shortcomings of its components, which are the narrow specialization or the limitations of their functional capabilities and hardware complexity when using them to build a device for generating impulses of a system reset of a modern M-system.

A device [8] for bounce suppression containing a closing button, a CMOS technology trigger, the direct output of which is the device output, three resistors, two capacitors, a supply voltage bus connected through the first resistor to the first output of the first capacitor and the first contact of the button, the second contact of which connected to the first output of the second resistor and the trigger sync input, the inverse output of which is connected through the third resistor to the information input of the trigger and the first output of the second capacitor, the second pin It is connected to the second terminals of the first capacitor and second resistor and to the device common bus.

In the initial state, the button is open, the trigger is in the state X = 0 (or 1), the first capacitor is charged to the supply voltage UC1 = Ep, the trigger sync input is in the logical “0” state (the sync input through the second resistor is connected to the common bus), and the information the trigger input is in the NX state (where NX is the inversion of X) and the second capacitor is charged to a voltage of UC2≈ Ep (or 0 V) at X = 0 (or 1). At the touch of a button, several pulses of contact bounce are generated at the trigger sync input during the time of _tinkling t _tread = 1-10 ms [5, p. 117]).

On the first front of the first bounce pulse, the trigger switches to the opposite state, at the end of the bounce the first capacitor is discharged to a voltage of UC1≈ 0 V, and the second capacitor is charged to a voltage of UC2≈ 0 V (or Ep) at X = 1 (or X = 0). When the button is released, its chatter does not affect the trigger state, since the first capacitor is discharged to 0 V, and at the end of the chatter, the first capacitor is charged through the first resistance to the initial voltage UC1 = Ep. Thus, this device operates in such a way that at each press of the button, the trigger switches to the opposite state.

The main disadvantage of the device [8] is that, with relative hardware complexity, it performs only the function of a one-bit counter of button presses and it does not provide for the function of generating a single pulse at power-ups. This limits the use of such technical solutions as even the simplest devices for generating reset pulses when creating modern M-systems.

A device [13] is known that contains two AND elements, a delay element, a NOT element, a pulse sequence regenerator (formed by series-connected OR elements, a delay element and a shaper that performs the function of shortening the input signal in duration), an OR element, a counter, a decoder, the inputs of which connected to the outputs of the counter, the reset input of which is connected to the output of the first AND element, whose inputs are connected to the outputs of the delay element and the OR element, the pulse sequence input connected the first inputs of the regenerator and the OR element and connected through the element NOT to the first input of the second element And, the second input of which is connected to the input of the delay element and the output of the regenerator, the first pulse output connected to the output of the second element And, the second input of the regenerator and the counter counter input, and the second pulse output, which is the output of the decoder, which is connected to the second input of the OR element.

In the initial state, the counter is reset, each input pulse with a delay and shortening passes to the output of the regenerator and through the element DOES NOT inhibit the second element And, and in case of loss of a pulse in the input sequence, the second element And passes the pulse from the output of the regenerator, i.e. generates an output pulse corresponding to the lost pulse at the first output. These pulses are counted by the counter and, if the number of missed pulses reaches the threshold, then the decoder at the second output of the device generates a pulse that, through the OR element and the first AND element, resets the counter to the zero state.

The main disadvantage of the device [13] is that, with considerable hardware complexity, it has limited capabilities when performing its functions, since it does not detect pulse loss when a single signal “hangs” at the input of the device, since in this case a constant signal is formed at the output of the OR element of the regenerator single signal blocking regeneration.

Of the known technical solutions, the closest to the proposed one according to the principle of generating output pulses and in composition is a device [14] containing two resistors, the first output of the first of which is connected to the device’s supply voltage bus, a capacitor, a logical repeater of CMOS technology (formed by two elements NOT, the input of the first of which is the input of the repeater, the output of which is the output of the second element NOT, the input of which is connected to the output of the first element NOT), a closing button, the first contact of which connected to the device common bus, and the output of the inverse pulse signal connected to the output of the repeater and the first output of the capacitor, the second output of which is connected to the input of the repeater and the first output of the second resistor, the second output of which is connected to the second contact of the button and the second output of the first resistor.

During operation of the device, the voltage IU = UC + OU (where UC is the voltage across the capacitor measured at the second terminal relative to its first output; OU is the voltage at the output of the repeater) is generated at the repeater input), and when the button is not pressed, IU≈ Еп and OU≈ Ep, which determine the inverse digital signals INX = 1 and ONX = 1 at the input and output of the repeater, respectively. Thus, when the button is not pressed, the device is in the zero stable state (NOS) NUS = {IU≈ Ep, UC≈ 0 V, OU≈ Ep, INX = 1, ONX = 1}. When the button is pressed, the capacitor and the second resistor form a shortening circuit (the circuit output is connected to the repeater input, and the input to the repeater output) and the voltage IU starts to decrease, since the capacitor starts charging from the voltage OU≈ Ep through the second resistor and the closed button. If the time constant C · R2, where C and R2 are the capacitance of the capacitor and the resistance of the second resistor, respectively, is selected sufficiently large, then the decreasing voltage IU reaches the threshold U (-) of switching the repeater from “1” to “0” after the button bounce stops when closing . At the moment IU (t) = U (-) ≈ Ep / 2, the repeater enters the amplification zone of the negative increment dIU (t) = IU (t) -U (-). Therefore, the appearing negative increment dIU (t) causes an enhanced decrease in the OU voltage, which, through the capacitor along the positive feedback loop, causes, as in the Schmitt trigger, a jump-like change in the OU voltage from OU≈ Ep to OU≈ 0 V with the device transitioning to a single transition state ( ENP)

ENP = {IU≈ UC≈ -En / 2, OU≈ 0 V, INX = 0, ONX = 0},

since (according to the first law of switching [15, p.20]) for any finite current charging or discharging the capacitor, the voltage across it cannot change stepwise. Next, after about time

T = 3 · [IR (-) + OR]

the capacitor is almost discharged, and the device goes into a single stable state (EUS)

ЕУС = {IU≈ UC≈ OU≈ 0 V, INX = 0, ONX = 0}, where

IR (-) - input internal protective resistance of the repeater input from the negative voltage IU <0 V;

OR is the output internal resistance of the repeater.

When you release the button, the series connection of the first and second resistors (i.e., resistor R with resistance R = R1 + R2) and the capacitor form an integrating circuit (the output of the circuit is connected to the input of the repeater, and the input to the supply voltage Ep) and the voltage IU starts to increase , since the capacitor starts charging from the voltage Ep through R when the button is opened. Since the time constant is (C · R)> (C · R2), the increasing voltage IU reaches the threshold U (+) of switching the repeater from “0” to “1” after the button rattles when it opens. At the moment IU (t) = U (+) ≈ Ep / 2, the repeater enters the amplification zone of the positive increment dIU (t) = IU (t) -U (+). Therefore, the appeared positive increment dIU (t) causes an increased increase in the voltage OU, which through the capacitor through the positive feedback loop causes, as in the Schmitt trigger, an abrupt change in the voltage OU from OU≈ 0 V to OU≈ Ep with the transition of the device, in accordance with the first the law of switching, to the zero transition state (NPS)

NPS = {IU≈ Ep / 2 + Ep, UC≈ + Ep / 2, OU≈ Ep, INX = 1, ONX = 1},

and then after about time T = 3 · [IR (+) + OR] in the NLS of the button not pressed, where IR (+) is the input internal protective resistance of the repeater from the input positive voltage IU> Ep.

Thus, in the process of functioning, the device [14] repeats the button position so that a button produces a digital inverse pulse ONX = 0 at the output of the button, the duration of which corresponds to the contact closure time of the button, and the slice (switching from “1” to “0”) and the front (switching from “0” to “1”) are delayed relative to the closure and opening of the contacts of the button, respectively.

The main disadvantage of the device [14] when applying it, for example, to build a modern M-system for information processing and control is the limited functionality of it, for example, it does not generate an output pulse when the power is turned on, but performs the only function of generating an output inverse digital pulse ONX, which simulates the state of the button with the elimination of chatter.

The present invention solves the problem of comprehensively expanding the functionality of the device by generating the output pulse when the power is turned on, taking into account the limitations of (1) and making it possible for the device to perform the functions of a hardware watchdog timer while allowing the formation of the output pulse taking into account the limitations of (2) when the pulses are missed or “frozen” input pulse signal arriving at the device, for example, from the microcontroller of the M-system for information processing and control.

To achieve this technical result, a device for forming pulses containing the first and second resistors, a closing button, the first contact of which is connected to a common bus of the device, a capacitor, a logic repeater of CMOS technology, a bus voltage supply and the output of the inverse pulse signal connected to the output of the repeater and the first output of the capacitor, the third resistor is introduced, the AND element, the first and second AND elements, the signal combiner to turn on the power and from the button, the first, second and third inputs of which respectively, are connected to a supply voltage bus, a common bus and a second button contact, a pulse detector, the pulse and installation inputs of which are respectively connected to the outputs of the first and second AND elements, and the detector output is connected to the first output of the first resistor, the second output of which is connected to the second output capacitor and the first output of the second resistor, the second output of which is connected to the input of the repeater, the input of the pulse signal, which is the first input of the first element And, and the control input, through the third resistor with a supply voltage bus and being the first input of the AND-NOT element, the second input of which is connected to the output of the driver, and the output of the AND-NOT element is connected to the first input of the second AND element, the second input of which is connected to the second input of the first AND element and combiner output.

The author is not aware of technical solutions containing features equivalent to distinctive features (introduction of a third resistor, an NAND element, two AND elements, a signal combiner for turning on the power and from a button, pulse detector, pulse signal input and control input) of the proposed device, which (according compared with the prototype [14]) comprehensively expand the functionality of the device due to both the formation of the output pulse when the power is turned on and the device can be executed uu hardware watchdog input pulse signal at a resolution of generating an output pulse when skipping or "hangs" pulses in the input pulse signals to the device, e.g., a microcontroller or serviced M unattended system.

The drawing shows a functional diagram of a device for generating pulses, containing three resistors 1-3, a closing button 4, the first contact of which is connected to a common bus of the device, a capacitor 5, a logical repeater 6 CMOS technology (made, for example, as an element And, the inputs of which are combined and are the inputs of the repeater 6), the supply voltage bus, element 7 AND-NOT, the first 8 and second 9 elements AND, the combiner 10 signals to turn on the power and from the button, the first, second and third inputs of which are respectively connected to the bus voltage supply, the common bus and the second contact of the button 4, the detector 11 pulses, the pulse and installation inputs of which are respectively connected to the outputs of the first 8 and second 9 elements And, and the output of the detector 11 is connected to the first output of the first resistor 1, the output of the inverse pulse signal connected with the output of the follower 6 and the first output of the capacitor 5, the second output of which is connected to the second output of the first resistor 1 and the first output of the second resistor 2, the second output of which is connected to the input of the follower 6, input 12 pulse a clear signal, which is the first input of the first element 8 AND, and the control input 13 connected through the third resistor 3 to the supply voltage bus and is the first input of the element 7 AND NOT, the second input of which is connected to the output of the device, and the output of the element 7 AND NOT connected to the first input of the second element 9 And, the second input of which is connected to the second input of the first element 8 And and the output of the combiner 10.

A possible variant of the combiner 10 signals to turn on the power and from the button contains resistors 14-16, a capacitor 17, a CMOS technology element 18, a first input connected to the first terminals of the resistors 14 and 15, a second input connected to the first terminal of the capacitor 17, the second terminal which is connected to the second terminal of the resistor 14 and the first terminal of the resistor 16, the second terminal of which is connected to the first input of the element 18 AND, the third input connected to the second terminal of the resistor 15 and the second input of the element 18 AND, and the output, which is the output of the element 18 I.

It should be noted that if it is possible to use an imported element base as a combiner 10, it is currently advisable to use a DALLAS Semicodactor type DS1233D-10 chip, which is a driver of an inverse reset signal when the supply voltage deviates from the nominal value +5 V. This deviation is in the range from 4 , 25 V to 4.49 V, and the microcircuit contains a voltage divider with stable parameters in the operating temperature range (Vcc TOLERANCE AND BIAS), a reference voltage source (T.S. REFERENCE), a comparator, a delay element (350 ms DELAY), res side, MOS transistor, a voltage input connected to the first output of the resistor and connected through a voltage divider to a non-inverting input of the comparator, the inverting input of which is connected to the output of the reference voltage source, the common bus input connected to the drain of the transistor, and the output of the inverse pulse, connected to the second output of the resistor and the source of the transistor, the gate of which through the delay element is connected to the output of the comparator.

The DS1233D-10 microcircuit operates in the temperature range from -40 ° C to + 85 ° C so that when the supply voltage is turned on, Ep≤7 V produces an inverse reset pulse NRST = 0 with a duration of t _RST0 = 250-450 ms, and then switches in “1” and continuously monitors the voltage level Ep: the comparator compares the output voltage of the divider with the reference voltage of the reference voltage source and through the delay element controls the state of the key - MOS transistor. When the voltage Ep reaches the corresponding point in the range from 4.25 V to 4.49 V, the NRST signal at the output of the microcircuit switches from “1” to “0” for a time of no more than 100 ns, for a time of at least t _RST0 = 250-450 ms.

When using the DS1233D-10 chip as a combiner 10, its inputs are connected to the supply voltage bus and a common bus, and the output of the chip is the output of the combiner 10, which is connected to the second contact of the button 4 and the second inputs of the elements 8 and 9.

The pulse detector 11 can be implemented on the basis of any of the previously mentioned devices of the third group (i.e., a pulse shaper enveloping a series of pulses), and one of the possible options for the detector 11 contains capacitors 19 and 20, diodes 21, 22 and 23, resistors 24 25 and 26, a pulse input connected to the first output of the capacitor 19, the second output of which is connected through a resistor 24 to the cathode of the diode 21 and the anode of the diode 22, the installation input connected through a resistor 25 to the anode of the diode 23, and the output connected to the cathodes of the diodes 22 and 23 and the first conclusions of the conde a sensor 20 and a resistor 26, the second terminals of which are connected to the anode of the diode 21 and a common bus.

The logical elements of the device are made on CMOS integrated circuits of the 1554 series (the repeater 6 and the elements 8, 9 and 18 are implemented on the same LI1 chip containing four 2 I elements, and the I-NOT element 7 occupies 0.25 LAZ chips containing four 2I- elements NOT), operating in the temperature range from -45 ° С to + 85 ° С with a supply voltage Ep from +2 to +6 V at a constant current for each output up to 24 mA and an input current for each input from -1 to +1 μA - see, for example, [16, p.15, p.21 of Table 3.1]. In addition [16, p.16], 1554 series microcircuits are capable of working with an output current of at least 75 mA and an output voltage of at least 3.85 V at Ep = 5.5 V for buses with a wave impedance of Z _o = 50 Ohms.

As the diodes 21-23 of the detector 11, for example, diodes of the 2D522B type or three of the eight diodes of the diode array 2D627A can be used.

Further, a description of the operation of the device is carried out using the provisions, symbols and design ratios defined in the following paragraphs.

1. When constructing devices containing an integrating (or shortening) RC circuit connected by an output to the input of a logic element associated with its output through a positive feedback circuit, the problem arises of estimating the response time Tav. logic element when changing the signal at the input of the circuit from 0 V to the supply voltage Ep or vice versa from Ep to 0 V. Time Tav. is determined by the time constant T = C · R of the circuit and the response threshold of the logic element, which for the CMOS element is close to half the supply voltage Ep [9, p. 58].

Denote by the input of the logical repeater 6 (or by the first input of the element 18) the thresholds of its operation for switching on and off through U (+) and U (-), respectively, and

where dUy is a small voltage interval from U (+) to U (-), in which the repeater 6 (or element 18) is a non-inverting amplifier for changing the input voltage with a gain much greater than unity.

According to [15, p. 67, 68] and taking into account the proximity of the threshold (4) or (5) to the value of Ep / 2, the response time Tav. estimated by the formula

determining the time for the integrating (or shortening) circuit to change the output signal of the circuit from the initial level to a level that is half of the stepwise change in the input signal (or the active duration of the output pulse of the shortening circuit, measured at a level of half the amplitude).

2. A modified language for describing logical functions ABEL is used, in which the operators “AND” and “NOT” are designated “&” and “!” (Or “N”), respectively.

3. The voltage between the second and first terminals of resistor 1 is denoted by UR1, and the voltage across the capacitors 5, 17, 19, and 20 is denoted by UC5, UC17, UC19, and UC20, respectively, with UC5 (or UC19) measured at the second terminal of capacitor 5 (or 19) with respect to its first output, UC17 - at the second output of the capacitor 17 relative to its first output connected to the common bus, UC20 - at the first output of the capacitor 20 relative to its second output connected to the common bus.

The digital signals at inputs 12, 13, at the junction point of resistors 1, 2 and capacitor 5 and the signals at the outputs of elements 6, 7, 8, 9 and 18 are denoted by IX12, IX13, NIR2 and NOX6, NOX7, 0X8, OX9 and NOX18, and the corresponding analog voltages are denoted by U12, U13, UIR2 and U6, U7, U8, U9 and U18, respectively, and the value “0” or “1” of any digital signal is modeled by the analog voltage “≈ 0 V” (for UIR2 <U ( +)) or “≈ Ep” (for UIR2> U (-)), respectively.

4. Denote the resistance of the resistors 1-3, 14-16, 24-26 and the capacitance of the capacitors 5, 17, 19 and 20 through R1-R3, R14-R16, R24-R26 and C5, C17, C19 and C20, respectively.

Resistor 2 (or 16) is designed to limit the discharge current of the capacitor 5 (or 14) flowing through the protective diodes of the inputs of the 6 And element - repeater 6 (or the protective diode of the first input of the 18 And element) and the resistor 2 (or 16) at the beginning or end output pulse NOX6 = 0 (or when the supply voltage is turned off). The resistances of these resistors are chosen equal to R2 = R16 = 300 Ohm, taking into account [16, p.20, Fig. 3.12] protection circuits against electrical discharge using the organization of the inputs and outputs of the KR1554 microcircuit with a protective pair of diodes for each input and output [16, p.25, Fig.3.24].

Resistors 24 and 25 are designed to limit the pulse currents of the elements 8 and 9, respectively. The resistances of these resistors are chosen equal to R24 = R25 = 51 Ohms.

When the button 4 is not pressed, a logical signal “1” is supplied to the second input of element 18 by connecting this input to the supply voltage through a resistor 15, the resistance of which is chosen equal to R15 = 2 kOhm.

Input 13 is technological (it is used only when debugging the M-system from the stand), and in the normal mode of the system, input 13 is open and is in state ИХ13 = 1 due to its connection to the supply voltage through resistor 3, the resistance of which is chosen equal to R3 = 2 kOhm .

5. Element 8, the capacitor 19, and diodes 21 and 22 are used only when the device is operating in the watchdog mode with monitoring the behavior of the input pulses IX12 in time. With the steady-state supply voltage Ep and the button 4 not pressed, this mode is performed according to OX8 = IX12 with IX13 = 1 and when the pulse sequence is received at input 12 and has a period T12 = T12.0 + T12.1, so that IX12 = 0 (or 1) during T12.0 (or T12.1).

6. The combiner 10 operates so that in it the element 18 AND performs the logical function of combining by OR the inverse signals to turn on the power and from the pressed button 4 and generates an inverse output signal NOX18 = 0 when the supply voltage Ep is turned on, and after setting the voltage Ep at the output of element 18, the digital signal of the position of the button 4 is repeated, namely, NOX18 = 1 and NOX18 = 0 when the button 4 is not pressed and pressed, respectively.

7. Using the accepted notation, the logical functioning of the elements 6-9 of the device is described by the following formulas:

where the voltage UIR2 is determined by the formula

moreover, a monotonic change (increasing to U (+) or decreasing to U (-)) of the voltage UIR2 (t) in the positive feedback loop with the output voltage U6 through capacitor C5 and resistor 2, as in Schmitt's trigger, causes an abrupt switching of the digital signal NOX6 of repeater 6 or from “0” to “1” when the threshold of operation U (+) is reached when increasing; or from “1” to “0” when the threshold of operation U (-) is reached when decreasing.

8. The front or slice of any digital signal (direct or inverse) means the change in the logical state of this signal from “0” to “1” or from “1” to “0”, respectively.

Based on the foregoing, we will describe sequentially the operation of the device when each of the following three events occurs: turning on the supply voltage, closing the button 4 with the subsequent opening, detecting a skipping or “freezing” of the input pulse signal IX12 with IX13 = 1, allowing the device to work in the watchdog timer mode input pulse signal IX12.

Before turning on the power, Ep = UC5 = UC17 = UC19 = UC20 = 0 V and button 4 is open. When the supply voltage is turned on after a few tens of milliseconds when Ep> 2 V is reached at UC17 <U (+), the elements 6–9, 18 begin to work stably and the device at NOX18 = 0 is fixed in the unit in accordance with expressions (7) - (12) steady state power on (EUSWP)

at time t _ON , which according to expression (6) is estimated by the expression

During the time (15), the capacitor 17 is charged through the resistor 14 to the voltage UC17 = U (+) and the element 18 enters the zone dUy (5), in which it is a non-inverting amplifier for increasing the input voltage UC17 with a gain much greater than unity. Through time

transition zone dUy (5), the capacitor C17 is charged to a voltage UC17> U (-), through which the element 18 stably generates an output signal NOX18 = 1. Using the digital signals NOX7 = 1 and NOX18 = 1, element 9 forms a digital signal OX9 = 1, by the voltage U9≈ Ep of which the capacitor 20 is quickly charged through the diode 23 to the voltage UC20≈ Ep and the device is in a single transition state (ENP)

for about time

During the time (18), the capacitor 5 from the voltage UC20≈ Ep is charged through the resistor 1 to the voltage UC5≈ U (+) and at UIR2 = U (+), element 6 enters the gain zone dUy (5) of the further positive voltage increment UIR2 with the gain , many large units. This causes a loop of positive feedback (through capacitor 5 and resistor 2) to short circuit the output signal of element 6 to its input and an avalanche-like switching of the NOX6 signal from “0” to “1” with the transition of the device to the zero transition state (NPS)

Thus, each time the power is turned on, an inverse pulse NOX6 = 0 is formed at the output of the device, the duration of which, subject to the constraint (1), is estimated by the relation

At the end of this pulse, after about time

the capacitor C5 is discharged, and when IX13 = 0 or when 12 pulses of the IX12 signal arrive at the input 12 with a period of T12 satisfying the condition for detecting IX13 pulses (to be determined below), the device goes to the zero stable state (NOS) of the unpressed button 4

If the device is in the NUS (22), then each time you press button 4, it works as follows.

When button 4 is pressed at the output of element 18, a NOX18 signal is generated, which repeats the digital signal of button 4 position, the duration of which t _rattles , according to [5, p. 117], taking into account expression (18), is determined by the relation

After pressing button 4, after time (23), the elements 18, 8 and 9 generate digital signals NOX18 = OX8 = OX9 = 0, the outputs U8≈ U9≈ 0 V are generated at the outputs of the elements 8 and 9, the diodes 22 and 23 are closed, and the device goes on to the zero transition state of the pressed button (NPSK)

the duration of T6.0 which is estimated by the expression

The functioning of the device in state (24) during T6.0 consists in the discharge of the capacitor C20 from the voltage UC20 (t = 0) ≈ Ep and the charge of the capacitor UC5 (t = 0) ≈ 0 V to such values that after a time T6.0 is monotonic the decrease in voltage UIR2 reaches the threshold U (-) = UIR2 = (UC20 + UR1) = (UC5 + U6) ≈ (UC5 + Ep). A further continuous decrease in the voltage UIR2 through the resistor R2 at the inputs is perceived by the follower 6 and causes an amplified decrease in the voltage U6 at its output. The started decrease in U6 through the positive feedback loop through the capacitor C5 and resistor R2 is transmitted to the inputs of the repeater 6 and causes a jump-like process of switching the NOX6 signal from “1” to “0”, and the device goes into a single transient state of the pressed button (ЕПСНК)

Since U8 = U9≈ 0 B, the operation of the device in state (26) consists in the discharge of capacitors 5 and 20. This process ends with the transition of the device to a single stable state of the pressed button (EUSC)

When the button is released after time _trebar (23), the element 18 generates a digital signal NOX18 = 1, and the device then operates according to the previously described transient process when the power is turned on after the element 9 generates a digital signal OX9 = 1, namely, according to the voltage U9≈ Ep through the diode 23 quickly charges the capacitor 20 to a voltage of UC20≈ Ep, with which the device sequentially switches to the UES (17) for about the time T6.1 (18), in the NPS (19) for about the time t _razp 5 (21) and in the NOS (22), which is the original.

If the device is in the NUS (22), then with IH13 = NOX18 = 1 it is put into a watchdog mode with monitoring the behavior in time of the input pulse signal IX12, determined by the period T12 = T12.0 + T12.1 of the pulse repetition rate.

Impulses IX12 through element 8 are fed to the pulse input of the detector 11 in the form of voltage pulses U8 such that during T12.0 (or T12.1) the voltage is U8≈ 0 V (or En). Therefore, with the beginning of each edge of the signal IX12 over time

in voltage U8≈ Ep, the capacitors 19 and 20 are charged through the resistance (R24 + Rd), respectively, to the voltages UC19 and UC20 defined by the expressions

Where

Rd≈ (10-1000) Ohm - differential resistance of the diode 22;

UC20 (t = 0) - voltage UC20 at the moment of the pulse front IX12;

UD22≈0.2 V is the voltage at the open diode 22 at the end of T3 (28).

With the beginning of each decay of the signal at input 12 (i.e., at U8≈ 0 V and U9≈ 0 V), during the time T12.0, the capacitor 19 discharges to approximately 0 V, and during the time (T12-Tz) a discharge occurs capacitor 20 from voltage (30) and the change (dynamic increase and decrease) of voltage UC5 through resistance 1 from the voltage difference [UC20 (t) -U6]) ≈ [UC20 (t) -Ep] with a tendency to monitor voltage UIR2 (t) ( 13) for the changing voltage UC20 (t), which during each period T12 first increases during the time Tz (28), and then decreases during (T12-Tz). The voltage UIR2 (t) when a pulse signal IX12 is detected at input 12 is always greater than the threshold U (-), and when UIR2 (t) = U (-), the device detects the disappearance of one pulse in the input sequence IX12 (or “freezing”), marked by the formation one pulse NOX6 = 0 (or by transferring the device to the oscillator mode) with the formation of element 9 using element 7 of a single signal OX9 = 1 (i.e. voltage U9≈ Ep) to install detector 11 through resistor 25 and diode 23 to its initial state UC20≈ Ep detection of pulses of the signal IX12.

Using expressions (7) - (13), the above (see expressions (25), (28) - (30)) formally describes the operation of the detector 11 pulses of the signal IX12 at input 12, and the condition for the detection of pulses OX8 = IX12 is

and the condition for detecting the disappearance or “freezing” of pulses 0X8 = IX12 is the ratio.

From (25), (28) - (32) it follows that the stable operation of the device in the watchdog mode with tracking the pulse signal at input 12 can be provided by the choice of values (T12-Tz) and C19 with a margin based on the expressions

In view of the foregoing, the operation of the device in the watchdog timer mode (monitoring the time behavior of pulses OX8 = IX12 at IX13 = NOX18 = 1), starting at some point in time from the zero dynamic state of pulse detection (VATOI)

can be described as follows.

With the beginning of each edge of the signal OX8 = IX12 for the time T3 (28), the voltage U8≈ En charges the capacitors 19 and 20 through the resistance (R24 + Rd) to the voltages UC19 (29) and UC20 (30), respectively. Then, with the beginning of each decay of the OX8 signal during T12.0 at U8≈ 0 V, the capacitor 19 discharges to approximately 0 V, and the capacitor 20 discharges from the initial voltage (30) over the course of time (T12-Tz), i.e. . during most of the period T12, the pulse repetition rate is OH8 = IX12. The change in the voltage UIR2 occurs continuously with tracking changes in the voltage UC20> U (-) during both T3 and (T12-T3). In this regard, in this mode, the current value of the voltage UIR2 (t) depending on the duration (T12-Tz) is perceived by the inputs of the repeater 6 when the condition (31) for detecting pulses OX8 = IX12 is met as a digital signal NIR2 = 1 (i.e., UIR2 (t)> U (-)), and if condition (32) for detecting the omission (or “freezing”) of pulses OX8 = IX12 is satisfied, then at some point in time the voltage UIR2 (t) decreases to the threshold voltage U (-), and through the capacitor 5 and resistor 2, the positive feedback loop closes, the NOX6 signal switches from “1” to “0”, and the device switches t at time T6.1 (18) in one state of generation (ESG)

During the time T6.1, the voltage UIR2 (t) continuously increases due to the charge of the capacitor C5 from the voltage (UC20-U6) ≈ Ep through resistor 1, and at t = T6.1 the voltage UIR2 (t) becomes equal to U (+). A further increase in the voltage UIR2 (t) through the positive feedback circuit through the capacitor 5 and resistor 2 causes the ONX6 output signal to switch from “0” to “1” and return the device to VATOI (35). The further operation of the device is determined by the behavior of the signal 0X8 = IX12 as a function of time, and when the signal "IX12" hangs (that is, when the signal IX12 = 0 or IX12 = 1 remains constant in time), the device switches to the oscillator mode. The self-oscillator mode is carried out as an alternation along the ring of the described processes of formation of NOX6 = 0 during T6.1 and NOX6 = 1 during T6.0, and

in accordance with expressions (2), (18) and (25).

The M-system interprets the output signal ONX6 = 0 as an inverse reset pulse NRST = 0, at the end of which it is initialized, tested and proceeds to perform its functions. After or during the initialization process, the UPU microcontroller should begin to programmatically generate a pulse signal IX12 in accordance with restriction (33) to support the functioning of the device in the NDIS (35) with IX13 = 1. With the correct functioning of the UPA, the period T12 of the pulse repetition frequency IX12 must satisfy the conditions (31) and (33) for reliable pulse detection OX8 = IX12 by the detector 11.

With IX13 = 0, the watchdog timer mode is disabled. This allows the M-system in the process of debugging to function from the microcontroller emulator in a step-by-step mode.

Directly from the description of the prototype [14] and this device, it follows that, compared to the prototype, the proposed device, due to its essential features, has significantly expanded functionality due to the formation of the output pulse when the power is turned on, taking into account the constraint (1), implemented as a constraint ( 20), as well as providing the possibility (with IX13 = 1) of the device performing the function of a hardware watchdog timer, which ensures the formation of an output pulse with taking into account constraint (2) implemented as constraint (18).

Literature

1. Ushkar M.N. Microprocessor devices in electronic equipment / ed. B.F. Vysotsky - M .: Radio and communications, 1988. - 128. “The principles of building microprocessor means", p.5-12.

2. Brodin VB, Kalinin A.V. Systems based on microcontrollers and LSI programmable logic. - M.: Publishing house ECOM, 2002 - 400 p.

3. Stashin V.V. et al. Design of digital devices on single-chip microcontrollers / V.V. Stashin, A.V. Urusov, O.F.Molgontseva. - M: Energoatomizdat, 1990 .-- 224 p.

4. Zeldin EA Digital integrated circuits in information technology. L .: Energoatomizdat. Leningra. Separation. 1986.- 280 s. “Pulse devices on microcircuits” - p.202-276.

5. Ugryumov EP Digital circuitry. - SPb .: BHV-Petersburg, 2001 .-- 528 p.

6. A.S. No. 725209, H 03 K 3/78, USSR. Shaper of impulses / V.A. Rtishchev. - Publ. 1980. Bull. No. 12.

7. A.S. No. 731562, H 03 K 3/286, USSR. Device for eliminating the influence of contact bounce / V.A. Matyushevsky. - Publ. 1980. Bull. No. 16.

8. A.S. No. 1132353, H 03 K 5/01, USSR. Chatter suppression device / Yu.B. - Publ. 1984. Bull. No. 48.

9. Biryukov S.A. Digital devices on MOS integrated circuits. - M.: Radio and Communications, 1990. - 128 p.

10. Novikov Yu.V. Basics of digital circuitry. Basic elements and schemes. Design Methods. - M .: Mir, 2001 .-- 379 p. (Modern circuitry).

11. A.S. No. 599341, H 03 K 5/18. Device for monitoring the sequence of pulses / V.M. Kiselev and M.A. Andronov. - Publ. 1978. Bull. No. 11.

12. A.S. No. 1020986, H 03 K 5/156, USSR. Shaper of pulses enveloping a series of pulses / A.M. Hamburg and E.K. Iosipov. - Publ. 1983. Bull. No. 20.

13. A.S. No. 1157670, H 03 K 5/13, 5/19, USSR. Device for detecting pulse loss / A.B. Katz and A.C. Kreslavsky. - Publ. 1985. Bull. No. 19.

14. “Suppression of the rattling of a button with one pair of contacts” - p. 55, fig. 100a - with a delay on and off. In the book: Biryukov S.A. Digital devices on MOS - integrated circuits. - M.: Radio and Communications, 1990. - 128 p. Prototype.

15. Erofeev Yu.N. Pulse devices: Textbook. Allowance for universities on special. "Radio engineering". - M: Higher. school 1989 .-- 527 p.

16. I.I. Petrovsky, A.V. Pribylsky, A.A. Troyan, B.C. Chuvelev. Logical ICs KR1533, KR1554. Directory. In two parts. Part 1. BINOM LLP, 1993. - 254 p.

Claims (1)

A device for generating pulses, containing the first and second resistors, a closing button, the first contact of which is connected to the device common bus, a capacitor, a CMOS logic repeater, a supply voltage bus and an inverse pulse signal output connected to the repeater output and the first capacitor output, characterized in that it contains a third resistor, an NAND element, the first and second AND elements, a signal combiner for turning on the power and from the button, the first, second and third inputs of which respectively are connected to the supply voltage bus, the common bus and the second button contact, a pulse detector, the pulse and installation inputs of which are respectively connected to the outputs of the first and second AND elements, and the detector output is connected to the first output of the first resistor, the second output of which is connected to the second output of the capacitor and the first output of the second resistor, the second output of which is connected to the input of the repeater, the input of the pulse signal, which is the first input of the first element And, and the control input connected through the third cut Sided with the bus voltage and is the first input of AND-NO element, a second input coupled to an output device, and the output of AND-NO element is connected to a first input of the second AND gate, a second input coupled to a second input of the first AND gate and the output of the combiner.