CN115037684A - Satellite internet effective load route forwarding equipment - Google Patents
Satellite internet effective load route forwarding equipment Download PDFInfo
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- CN115037684A CN115037684A CN202210624679.6A CN202210624679A CN115037684A CN 115037684 A CN115037684 A CN 115037684A CN 202210624679 A CN202210624679 A CN 202210624679A CN 115037684 A CN115037684 A CN 115037684A
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- 238000012545 processing Methods 0.000 description 18
- 238000004891 communication Methods 0.000 description 9
- 238000007726 management method Methods 0.000 description 5
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/60—Router architectures
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses satellite internet payload routing forwarding equipment, and relates to the field of space circuits. The route repeater includes: the system comprises a network processor, internal exchange, a CPU module and a board management unit. The board card is in standardized design, unified structure, unified size, standardized interface and strong transportability, and the development cost and the development period of a load product can be greatly saved; the invention uses the idea of separating control surface from data surface and separating internal exchange from external exchange as the route forwarding unit of effective load, and uses industrial components to enhance the reliability of load system through main and standby cold backup.
Description
Technical Field
The invention relates to an aerospace product, in particular to a routing forwarding device for a payload of a satellite internet. In particular to data routing forwarding of inter-satellite and satellite-ground links.
Background
The satellite networking communication load system is one of key subsystems of a communication satellite constellation, and the routing switch is a core unit for satellite networking communication load data interaction. With the rapid development of the satellite internet era, a satellite network consists of a plurality of satellites and ground stations, satellite internet networking communication loads mainly transmit satellite-ground information through microwave antennas at present, and transmit inter-satellite information through laser links, the design of the inter-satellite laser communication links is mature, and the satellites are communicated through high-speed laser links; and the information routing is realized through the routing forwarding unit, and the satellite internet requires low-delay information transmission, so that not only low delay of each transmission terminal is required, but also low delay of a routing switching device part is required, and the processing capacity of the routing forwarding unit is further enhanced. The requirement for large capacity of data exchange is more and more remarkable, satellite exchange becomes an important component of satellite processing, and in order to realize seamless fusion of ground terminal and ground network communication, the route exchange equipment is a hub for networking communication load service data transfer, is an indispensable part of satellite networking, and is one of important development directions of satellite components of the satellite internet at present.
Disclosure of Invention
The technical problem solved by the invention is as follows: the satellite internet payload routing and forwarding equipment supports the SPACE VPX architecture, and standardizes the routing and forwarding circuit interface and size design.
The technical scheme of the invention is as follows: a satellite internet payload routing forwarding device, the device comprising: PPC daughter card and VPX architecture backplane, the PPC daughter card includes: the daughter card data storage device, the secondary power supply and the daughter card interface are all connected with the daughter card processor;
the VPX architecture backplane comprises: the network processor, the MSU and the internal exchanger are in data connection with each other, the network processor and the MSU are both connected with the main card data memory, the power supply module supplies power to the network processor, the MSU and the internal exchanger, and the network processor, the MSU and the internal exchanger are all connected with the main card interface;
the daughter card interface is connected with the main card interface, and the main card interface is also interacted with external data.
Further, the daughter card interface includes: PMC interface, XMC interface, daughter card data memory include: FLASH and DDR 3; here, FLASH is used for storing Boot Loader and application programs of the daughter card processor, and DDR3 is used for storing data of the daughter card processor; the daughter card interface includes: PMC interface, XMC interface;
the main card memory includes: network processors DDR3, MSU DDR3, NAND FLASH and NOR FLAS H; the network processor is connected with a network processor DDR3, and the MSU is connected with MSU DDR3, NAND FLASH and NO R FLASH; the main card interface includes: PMC interface, XMC interface and VPX interface;
the PMC interface and the XMC interface of the main card correspond to the PMC interface and the XMC interface of the daughter card interface, and the VPX interface is connected with the outside.
Furthermore, in the PPC sub-card, a sub-card processor is connected with a PMC interface through a local Bus protocol and is connected with an XMC interface through an Ethernet driving protocol, an RS232 protocol and a GPIO protocol;
in the VPX framework bottom plate, an MSU is connected with a PMC interface through a local Bus protocol, connected with a network processor, an IIC interface and an SRIO (serial peripheral interface) through a Select MAP (local Bus) and an LV DS (local Bus) interface and connected with an internal exchanger, connected with an XMC interface through an RS422 protocol and a CAN (controller area network) protocol and connected with a reference clock after passing through a buffer; the network processor is connected with the internal exchanger through an SRIO protocol, connected with the VPX interface and the XMC interface through the SRIO protocol, and connected with the reference clock through the buffer.
Further, the sub-card processor is P2020; the network processor is an FPGA; the FPGA is connected with an internal exchanger through 2 paths of 4 multiplied by SRIO, and is connected with a VPX interface through 6 paths of 4 multiplied by SRIO, and the reference clock is 156.25M; the MSU reference clock is 125M.
The invention includes 3 exchange interfaces and 3 external exchange interfaces, each exchange interface includes 2 groups of 4XSRIO, the external interface includes 1 group of 4XSRIO, support the large capacity data exchange inside the system and outside the system, the exchange interface uses SRIO interface, the exchange rate of each group of 4XSRIO interface reaches 20 Gps; the invention integrates SPACE VPX specification and VITA related specification, has uniform structure, uniform size and standardized interface, reduces the product cost and shortens the production period.
Drawings
Fig. 1 is a schematic diagram of an embodiment of a satellite internet payload routing and forwarding device of the present invention.
In the figure, 1, a network processor V7 series FPGA, 2, MSU, 3, internal exchange, 4, a CPU processor, 5 interface driving circuits, 6, power supply conversion processing, 7, NAND FLASH, 8, DDR3,9, reference clock CLK, 10, a slow new reference clock, 11, an XMC connector, 12, a current and voltage acquisition circuit ADC.
Detailed Description
A CPU processor chip of a control plane selects P2020, a network processor of a data plane selects a V7 series FPGA, the packet forwarding capability of the device is strong, the FPGA supports a high-speed communication interface SRIO, and external exchange interface processing is realized through an internal IP core processing protocol. The internal switching processing chip is implemented by a CPS1848 switching chip. The structural size of the routing switch module bottom plate is 233.35mm multiplied by 160mm multiplied by 25 mm.
The route forwarding equipment is composed of a bottom plate and a PPC sub-card of a standard 6U VPX framework, wherein the bottom plate mainly completes service data processing, data exchange and whole-plate state management, and the PPC sub-card completes data processing of a control plane and updating and maintaining of a route table.
The network processing FPGA completes data packet forwarding and scheduling management, the operation on the data packets needs to be executed when each data packet arrives and is sent, the data packets are subjected to interface processing with a switching chip, and data unpacking, data packing and the like of an SRIO protocol; the PPC sub card is mainly used for storing, updating and maintaining a routing table and a topology table, and configuring and managing the switching unit; managing with a network processing FPGA interface; the MSU completes module bottom layer management, including configuration management of the PPC daughter card, an FPGA configuration management program, CPS1848 configuration management, resetting of routing forwarding equipment and identification of a module MARK address, and completes local telemetry parameter collection of board card temperature, current and voltage.
The PPC daughter card processor is P2020, is a core chip of the PPC daughter card, and consists of an on-board data storage device DDR3 and FLASH, an interface driving circuit (Ethernet, RS232, SRIO and GPIO) and a secondary power supply circuit. The secondary power supply part on the board completes the distribution of the sub-card working voltage, and the PPC sub-card is integrated with 1 local Bus interface, 1 JTAG interface, 1 10M/100M Ethernet Bus interface, 1 RS232 interface and 10 GPIO interfaces. The controllers of the communication interfaces are integrated in the P2020 chip, and only interface driving circuits need to be designed in the periphery, the PPC daughter card is connected with the backplane through four PMC connectors and one XMC connector, and the XMC high-speed connector is mainly an SRIO interface and is connected to an internal exchanger on the backplane.
The backplane comprises a network processing FPGA, peripheral devices, a power supply conversion unit, an MSU, an internal exchanger, an interface driving circuit (including RS422, CAN and a network port) and connectors (a PMC connector, an XMC connector and a VPX interface).
The network processing FPGA is selected from an FPGA of XILINX 7 series with the model of XC7VX690T 1761I. The FPGA has high-performance DSP and RAM units. The system comprises 108300 logic units, 52920Kb Block RAM, 850 HP general I/O ports, 3600 DSP arithmetic processing units and 40 pair high-speed GTH interfaces. The maximum rate of 40 pairs of GTH is 13.1Gb/s, the rate of SRIO is 5Gb/s, 4 paths of 4X interfaces share 16 pairs of GTH interfaces, and design requirements can be met. The FPGA is connected with the internal exchange chip through 2 paths of 4 multiplied by SRIO interfaces to transmit internal routing data, and is connected with the VPX connector through 6 paths of 4 multiplied by SRIO interfaces to transmit external routing data.
The number of interfaces of the internal switch 80HCPS1848CRMI meets the design requirement, and the internal switch has a total of 48-path 1XSRIO interfaces and can be configured as 12-path 4 × SRIO interfaces. 2 paths of 4 × SRIOs to a network processing module, 1 path of 4 × SRIOs to a PPC daughter card, and 6 paths of 4 × SR IOs to a backboard, namely 2 paths of 4 × SRIOs to a user baseband processing module, 2 paths of 4 × SRIO signaling processing module, and 2 paths of 4 × SRIOs to a spectrum sensing processing module, wherein the SRIO interface rate is 5Gbps, and the 80HCPS1848CRMI is a RapidIO switching chip supporting the rapidIO1.3 specification. The clock source is 156.25MHz, the LVDS level AC coupling is CML level input to 80HCPS1848CRMI, the phase jitter of the clock source is less than 1ps, and the clock stability is less than 30 ppm.
The chip of the MSU is Zynq series MSU of XILINX company, the model is XC7Z045-2FFG676I, the external memory interface is designed to be DDR3, NOR FLASH, NAND FLASH, and the peripheral interface supports gigabit Ethernet, CAN BUS, I2C BUS, SRIO and Local BUS interface.
The clock circuit uses three differential clocks, two single-ended clocks, the differential clocks comprise 156.25M clock, 125M clock and 200M reference clock, the 125M clock provides MSU circuit and network processor, the 156.25M clock provides clock for internal exchanger, the 33M single-ended crystal oscillator provides system clock for MSU, and the 25M single-ended clock provides clock for PHY circuit. And simultaneously, an external reference clock is used for providing a synchronous clock of 100MHz for the card MSU and the network processor through a clock buffer.
The power supply conversion is used for completing voltage conversion required by normal work on the board, the voltage input from the outside is 12V, and the voltage is converted into 1V, 1.2V, 1.8V, 2.5V, 3.3V and 5V through the power supply. The LTM4644 and the LTM4620 are selected as devices, the voltage input range is 4-14V, the requirement of +12V direct current power supply can be met, the voltage input range of 4V-14V is covered, 4 paths of output are achieved, the peak current of each path of output circuit is 4A, and the output voltage range is 0.6V-5.5V. And converting into working voltages of 5V, 3.3V, 1.2V and 1.0V as required. The internal switch 80HCPS1848CRMI has 3 power supplies of 3.3V, 1.2V and 1.0V, and the chip requires the sequential power-up of 1.0V, 1.2V and 3.3V. The MSU chip has 4 power supplies of 3.3V and 1.8V, 1.2V, 1.0V, and the design scheme sets the power-on sequence of the power supplies to be 1V, 1.2V, 3.3V first. And managing the POWER-on sequence of the module by adopting the POWER GOOD signal of the chip. The POWER supply of 5V and 3.3V of the PPC daughter card is turned on by the POWER system, and the POWER GOOD output is turned on for 1V, 1.2V, 1.8V and 3.3V.
The interface driver is a 4-channel CAN, 6-channel RS422, 2-channel RS232 and 1-channel PHY interface driving circuit;
the VPX connector of the bottom plate is connected with the back plate of the case by using a standard 6U VPX connector.
Claims (4)
1. A satellite internet payload routing forwarding device, the device comprising: PPC daughter card and VPX framework bottom plate, the PPC daughter card includes: the daughter card data storage device, the secondary power supply and the daughter card interface are all connected with the daughter card processor;
the VPX architecture backplane comprises: the network processor, the MSU and the internal exchanger are in data connection with each other, the network processor and the MSU are both connected with the main card data memory, the power supply module supplies power to the network processor, the MSU and the internal exchanger, and the network processor, the MSU and the internal exchanger are all connected with the main card interface;
the daughter card interface is connected with the main card interface, and the main card interface is also interacted with external data.
2. The satellite internet payload routing repeater device of claim 1, wherein the daughter card interface comprises: PMC interface, XMC interface, the daughter card data memory includes: FLASH and DDR 3; here, FLASH is used for storing Boot Loader and application programs of the daughter card processor, and DDR3 is used for storing data of the daughter card processor; the daughter card interface includes: PMC interface, XMC interface;
the main card memory includes: network processors DDR3, MSU DDR3, NAND FLASH, and NOR FLASH; the network processor is connected with a network processor DDR3, and the MSU is connected with MSU DDR3, NAND FLASH and NOR FLASH; the main card interface includes: PMC interface, XMC interface and VPX interface;
the PMC interface and the XMC interface of the main card correspond to the PMC interface and the XMC interface of the daughter card interface, and the VPX interface is connected with the outside.
3. The satellite internet payload routing and forwarding device of claim 2, wherein in the PPC daughter card, the daughter card processor is connected to the PMC interface via a local Bus protocol, and is connected to the XMC interface via an ethernet driver protocol, an RS232 protocol, a GPIO protocol;
in the VPX framework bottom plate, an MSU is connected with a PMC interface through a local Bus protocol, connected with a network processor, an IIC interface and an SRIO (serial peripheral interface) through a Select MAP (local Bus) and an LVDS (Low Voltage differential Signaling) interface and an internal exchanger, connected with an XMC interface through an RS422 protocol and a CAN (controller area network) protocol and connected with a reference clock through a buffer; the network processor is connected with the internal exchanger through an SRIO protocol, connected with the VPX interface and the XMC interface through the SRIO protocol, and connected with the reference clock after passing through the buffer.
4. The satellite internet payload routing and forwarding device of claim 3, wherein the sub-card processor is P2020; the network processor is an FPGA; the FPGA is connected with an internal exchanger through 2 paths of 4 multiplied by SRIO, and is connected with a VPX interface through 6 paths of 4 multiplied by SRIO, and the reference clock is 156.25M; the MSU reference clock is 125M.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210624679.6A CN115037684A (en) | 2022-06-02 | 2022-06-02 | Satellite internet effective load route forwarding equipment |
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| CN202210624679.6A CN115037684A (en) | 2022-06-02 | 2022-06-02 | Satellite internet effective load route forwarding equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117639908A (en) * | 2024-01-26 | 2024-03-01 | 中国人民解放军国防科技大学 | Space-based intelligent network connection device based on VPX architecture |
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Cited By (2)
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