CN114975102B - 集成异质结双极晶体管及其制作方法 - Google Patents

集成异质结双极晶体管及其制作方法 Download PDF

Info

Publication number
CN114975102B
CN114975102B CN202210908826.2A CN202210908826A CN114975102B CN 114975102 B CN114975102 B CN 114975102B CN 202210908826 A CN202210908826 A CN 202210908826A CN 114975102 B CN114975102 B CN 114975102B
Authority
CN
China
Prior art keywords
layer
collector
bipolar transistor
heterojunction bipolar
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210908826.2A
Other languages
English (en)
Other versions
CN114975102A (zh
Inventor
何湘阳
魏鸿基
何先良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quanzhou San'an Integrated Circuit Co ltd
Original Assignee
Quanzhou San'an Integrated Circuit Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quanzhou San'an Integrated Circuit Co ltd filed Critical Quanzhou San'an Integrated Circuit Co ltd
Priority to CN202210908826.2A priority Critical patent/CN114975102B/zh
Publication of CN114975102A publication Critical patent/CN114975102A/zh
Application granted granted Critical
Publication of CN114975102B publication Critical patent/CN114975102B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0658—Vertical bipolar transistor in combination with resistors or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0664—Vertical bipolar transistor in combination with diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

本发明公开了一种集成异质结双极晶体管及其制作方法，属于半导体的技术领域，是在进行台面蚀刻时，保留无源区的预设电容区域的外延层和介质层，后续在制作集电极接触金属时，同步于预设区域的介质层上形成金属电极板以制作被动器件结构。本发明在不增加额外工艺的前提下，避免了金属电极板与GaAs外延层接触导致的元素扩散问题，维持金属电极板的平整度，提高被动器件结构的性能。

Description

集成异质结双极晶体管及其制作方法
技术领域
本发明属于半导体技术领域，具体涉及一种集成异质结双极晶体管及其制作方法。
背景技术
目前GaAs基异质结双极晶体管（HBT）产品中，在制作stack 堆叠电容时，其下极板使用的是HBT的集电极接触金属，且该金属直接与高掺杂的子集电极层接触，而该集电极接触金属为AuGe/Ni/Au或Au/Ge/Ni/Au结构，在与高掺杂GaAs子集电极层进行合金化形成欧姆接触过程中Ge会扩散进入GaAs中，Ga会扩散到金属中，形成晶粒，导致金属表面粗糙，降低了电容的击穿电压，影响器件可靠性。
发明内容
本发明针对现有技术存在的不足，提供一种集成异质结双极晶体管及其制作方法。
为了实现以上目的，本发明的技术方案为：
一种集成异质结双极晶体管的制作方法，包括以下步骤：
1）定义出GaAs基HBT外延结构的有源区和无源区，于有源区制作HBT器件结构，并沉积同时覆盖有源区和无源区的介质层；所述HBT外延结构由下至上包括衬底、次集电极层、蚀刻停止层、集电极层、基极层和发射极层；
2）对无源区进行离子注入隔离；
3）遮蔽有源区的HBT器件结构区域和无源区的预设区域，蚀刻未遮蔽区域至集电极层的部分深度形成集电极台面，所述有源区内的集电极台面作为电极形成区域；
4）涂覆负性光阻，于所述电极形成区域和预设区域形成显开窗口，蚀刻有源区的所述电极形成区域至露出次集电极层；
5）进行金属沉积，所述金属沉积同时于所述次集电极层上形成集电极接触金属，于预设区域的介质层上形成金属电极板；
6）进行高温退火，使集电极接触金属与次集电极层形成欧姆接触。
可选的，所述介质层的材料是SiN，厚度为50~200 nm。
可选的，所述步骤5）中，沉积金属为AuGe/Ni/Au叠层或Au/Ge/Ni/Au叠层。
可选的，所述步骤6）中，高温退火处理温度为340~390℃，时间60~120s。
可选的，所述步骤4）中，蚀刻采用的蚀刻剂为磷酸：双氧水：水比例在1:1:20~1:1:10；然后进行所述步骤5）之后再剥离所述负性光阻。
可选的，所述次集电极层是n+GaAs层，所述集电极层是n-GaAs层，所述基极层是p+ GaAs层，所述发射极层是n- InGaP层。
可选的，所述步骤3）中，蚀刻深度至所述集电极层厚度的50~70%。
一种上述制作方法制作的集成异质结双极晶体管，包括形成于有源区的HBT器件和位于无源区的被动器件结构；所述被动器件结构由下至上具有与HBT器件相同的衬底、次集电极层、蚀刻停止层、集电极层、基极层、发射极层和介质层，所述介质层上设有金属电极板，所述金属电极板与所述HBT器件的集电极接触金属具有相同的金属叠层结构。
可选的，所述介质层为SiN。
可选的，所述被动器件结构为电容，所述金属电极板作为电容下极板，电容下极板上还按序设有电介质和电容上极板。
本发明的有益效果为：
1）在HBT器件制作过程中，在进行集电极台面蚀刻时不对无源区预设区域进行蚀刻，于预设区域的介质层上形成金属电极板，避免了金属电极板与GaAs外延层接触导致的元素扩散问题，维持金属电极板的平整度，提高基于金属电极板制作的被动器件结构的性能；
2）将金属电极板制作过程合并于HBT器件制作过程中，在不增加额外工艺的前提下得到性能的提升。
附图说明
图1为实施例1的集成异质结双极晶体管的制作方法的步骤1得到的结构示意图；
图2为实施例1的集成异质结双极晶体管的制作方法的步骤2得到的结构示意图；
图3为实施例1的集成异质结双极晶体管的制作方法的步骤3得到的结构示意图；
图4为实施例1的集成异质结双极晶体管的制作方法的步骤4得到的结构示意图；
图5为实施例1的集成异质结双极晶体管的制作方法的步骤5得到的结构示意图；
图6为实施例1的集成异质结双极晶体管的结构示意图；
图7为对比例的集成异质结双极晶体管的制作方法的步骤3得到的结构示意图；
图8为对比例的集成异质结双极晶体管的制作方法的步骤4得到的结构示意图；
图9为对比例的集成异质结双极晶体管的制作方法的步骤5得到的结构示意图。
具体实施方式
以下结合附图和具体实施例对本发明做进一步解释。本发明的各附图仅为示意以更容易了解本发明，其具体比例可依照设计需求进行调整。文中所描述的图形中相对元件的上下关系以及正面/背面的定义，在本领域技术人员应能理解是指构件的相对位置而言，因此皆可以翻转而呈现相同的构件，此皆应同属本说明书所揭露的范围。
实施例1
实施例1的集成异质结双极晶体管，其制作工艺如下：
步骤1
参考图1，完成部分HBT器件制作后得到的结构包括HBT外延结构，HBT外延结构由下至上包括衬底1、次集电极层2、蚀刻停止层3、集电极层4、基极层5和发射极层6，HBT外延结构定义出有源区和无源区，有源区制作有发射极接触层7、发射极接触金属8和基极接触金属9，有源区和无源区表面均沉积有介质层10。
其中，HBT外延结构为GaAs基HBT外延层，具体，衬底1是GaAs层，次集电极层2是n+ GaAs层，集电极层4是n- GaAs层，基极层5是p+ GaAs层，发射极层6是n- InGaP层，蚀刻停止层3是例如InGaP层。发射极接触层7是InGaAs层，蚀刻出发射极平台后进行基极接触金属9的沉积。介质层10是SiN，厚度为例如50~100 nm。上述结构可参考已知技术制作。
步骤2
参考图2，对无源区通过常规离子注入工艺进行隔离，实现器件绝缘隔离。
步骤3
参考图3，遮蔽有源区的HBT器件结构区域和无源区的预设电容区域，蚀刻未遮蔽区域至集电极层4的部分深度形成集电极台面，例如集电极层深度的50~70%，保留部分集电极层以后续制作肖特基二级管。本次蚀刻于有源区露出集电极层的电极形成区域，同时于无源区保留预设电容区域的HBT外延结构和介质层10。
步骤4
参考图4，涂覆负性光阻R，通过曝光、显影工艺得到位于有源区的显开窗口R1和位于预设电容区的介质层10之上的显开窗口R2，采用磷酸：双氧水：水比例在1:1:20~1:1:10范围的药液蚀刻去除显开窗口R1之内的集电极层4和采用磷酸：盐酸=1：1~1:5药液去除蚀刻停止层3，裸露出次集电极层2表面。
步骤5
参考图5，沉积金属，于显开窗口R1内的次集电极层2上形成集电极接触金属11，于显开窗口R2内的介质层10上形成电容下极板12。然后剥离光阻R。沉积金属为厚度为100~400nm的AuGe/Ni/Au叠层或厚度为100~400nm的Au/Ge/Ni/Au叠层。由于负性光阻为正梯形形貌，沉积于显开窗口R1和R2内的金属不会与沉积于光阻R上的金属相连，便于光阻上金属的剥离。
步骤6
进行退火处理形成欧姆接触，退火温度340~390℃，时间60~120s。
后续还包括在电容下极板12上形成电介质层和电容上极板以得到完整电容结构等步骤。
参考图6，得到的集成异质结双极晶体管，包括形成于有源区的HBT器件和位于无源区的电容C，电容由下至上具有与HBT器件相同的衬底1、次集电极层2、集电极层3、基极层4、发射极层5、发射极层6和介质层10，介质层10上依次设有电容下极板12、电介质层13和电容上极板14，电容下极板12与HBT器件结构的集电极接触金属11具有相同的金属叠层结构。
对比例1
对比例的集成异质结双极晶体管，其制作工艺如下：
步骤1~2同实施例1的步骤1~2。
步骤3
参考图7，进行集电极台面蚀刻，蚀刻深度至集电极层4的部分深度。本次蚀刻仅保留有源区内的器件结构，无源区的HBT外延结构均蚀刻去除至仅保留部分深度的集电极层4。
步骤4
参考图8，涂覆正性光阻R’，通过曝光、显影工艺得到位于有源区的显开窗口R’1和位于预设电容区的集电极层4之上的显开窗口R’2，蚀刻同时去除窗口R’1和窗口R’2内的集电极层4和蚀刻停止层3，裸露出次集电极层2表面。正性光阻R’为倒梯形形貌，需进一步蚀刻集电极层4使其内凹至光阻R’下方。
步骤5
参考图9，沉积金属，于显开窗口R’1内的次集电极层2上形成集电极接触金属11，于显开窗口R’2内的次集电极层2上形成电容下极板12。然后剥离光阻R’。沉积金属同样为厚度为100~400 nm的AuGe/Ni/Au叠层或厚度为100~400 nm的Au/Ge/Ni/Au叠层。通过上述内凹蚀刻使得光阻上的金属不会与次集电极层2上的金属相连，便于剥离。
步骤6与实施例1相同。
相对于对比例1，实施例1具有如下优势：
1）对比例1中，在电容区域金属直接沉积于高掺杂GaAs的次集电极层2表面，由于扩散问题导致金属表面粗糙降低电容的击穿电压；实施例1的电容区域的金属沉积于介质层10表面，不与GaAs接触无法合金化，表面能保持原来的平整度，提高电容的击穿电压；
2）实施例1和对比例1相比，不增加额外步骤，不改变制程条件，与实际生产产线兼容性大，且避免了集电极层过蚀刻内凹到光阻下方所导致的可控性下降，蚀刻时间延长等问题，进一步优化了得到的器件的性能。
上述实施例仅用来进一步说明本发明的一种集成异质结双极晶体管及其制作方法，但本发明并不局限于实施例，凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均落入本发明技术方案的保护范围内。

Claims (10)

1.一种集成异质结双极晶体管的制作方法，其特征在于，包括以下步骤：
步骤1） 定义出GaAs基HBT外延结构的有源区和无源区，所述HBT外延结构由下至上包括衬底、次集电极层、蚀刻停止层、集电极层、基极层和发射极层，于有源区制作HBT器件结构，HBT器件结构包括发射极接触层、发射极接触金属和基极接触金属，并沉积同时覆盖有源区和无源区的介质层；
步骤2） 对无源区进行离子注入隔离；
步骤3） 遮蔽有源区的HBT器件结构区域和无源区的预设区域，蚀刻未遮蔽区域至集电极层的部分深度形成集电极台面，所述有源区内的集电极台面作为电极形成区域；
步骤4） 涂覆负性光阻，于所述电极形成区域和预设区域形成显开窗口，蚀刻有源区的所述电极形成区域至露出次集电极层；
步骤5） 进行金属沉积，所述金属沉积同时于所述次集电极层上形成集电极接触金属，于预设区域的介质层上形成金属电极板；
步骤6） 进行高温退火，使集电极接触金属与次集电极层形成欧姆接触。
2.根据权利要求1所述的集成异质结双极晶体管的制作方法，其特征在于：所述介质层的材料是SiN，厚度为50~200 nm。
3.根据权利要求1所述的集成异质结双极晶体管的制作方法，其特征在于：所述步骤5）中，沉积金属为AuGe/Ni/Au叠层或Au/Ge/Ni/Au叠层。
4.根据权利要求1所述的集成异质结双极晶体管的制作方法，其特征在于：所述步骤6）中，高温退火处理温度为340~390℃，时间60~120s。
5.根据权利要求1所述的集成异质结双极晶体管的制作方法，其特征在于：所述步骤4）中，蚀刻采用的蚀刻剂为磷酸：双氧水：水比例在1:1:20~1:1:10；然后进行所述步骤5）之后再剥离所述负性光阻。
6.根据权利要求1所述的集成异质结双极晶体管的制作方法，其特征在于：所述次集电极层是n+GaAs层，所述集电极层是n-GaAs层，所述基极层是p+ GaAs层，所述发射极层是n-InGaP层。
7.根据权利要求1所述的集成异质结双极晶体管的制作方法，其特征在于：所述步骤3）中，蚀刻深度至所述集电极层厚度的50~70%。
8.一种权利要求1~7任一项所述制作方法制作的集成异质结双极晶体管，其特征在于：包括形成于有源区的HBT器件和位于无源区的被动器件结构；所述被动器件结构由下至上具有与HBT器件相同的衬底、次集电极层、蚀刻停止层、集电极层、基极层、发射极层和介质层，所述介质层上设有金属电极板，所述金属电极板与所述HBT器件的集电极接触金属具有相同的金属叠层结构。
9.根据权利要求8所述的集成异质结双极晶体管，其特征在于：所述介质层为SiN。
10.根据权利要求8所述的集成异质结双极晶体管，其特征在于：所述被动器件结构为电容，所述金属电极板作为电容下极板，电容下极板上还按序设有电介质和电容上极板。
CN202210908826.2A 2022-07-29 2022-07-29 集成异质结双极晶体管及其制作方法 Active CN114975102B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210908826.2A CN114975102B (zh) 2022-07-29 2022-07-29 集成异质结双极晶体管及其制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210908826.2A CN114975102B (zh) 2022-07-29 2022-07-29 集成异质结双极晶体管及其制作方法

Publications (2)

Publication Number Publication Date
CN114975102A CN114975102A (zh) 2022-08-30
CN114975102B true CN114975102B (zh) 2022-10-28

Family

ID=82969327

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210908826.2A Active CN114975102B (zh) 2022-07-29 2022-07-29 集成异质结双极晶体管及其制作方法

Country Status (1)

Country Link
CN (1) CN114975102B (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051373A (en) * 1989-02-16 1991-09-24 Sanyo Electric Co., Ltd. Method of fabricating MMIC semiconductor integrated circuits using the RF and DC measurements of an active device on a substrate to design the passive elements, which are then E-beam written to the substrate
JP2001156179A (ja) * 1999-11-26 2001-06-08 Nec Corp 化合物半導体集積回路の製造方法
JP2002064183A (ja) * 2000-08-17 2002-02-28 Sony Corp 半導体装置およびその製造方法
JP2006108655A (ja) * 2004-09-13 2006-04-20 Matsushita Electric Ind Co Ltd 半導体装置、高周波増幅器および携帯情報端末
WO2007128075A2 (en) * 2006-05-08 2007-11-15 Epitactix Pty Ltd Method and apparatus for manufacture of semiconductors and resulting structures, devices, circuits, and components

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100220250B1 (ko) * 1996-10-19 1999-09-15 김영환 광전자 집적 회로의 제조 방법
JP2001326284A (ja) * 2000-05-17 2001-11-22 Nec Corp 化合物半導体集積回路およびその製造方法
GB0126895D0 (en) * 2001-11-08 2002-01-02 Denselight Semiconductors Pte Fabrication of a heterojunction bipolar transistor with intergrated mim capaci or
TWI291232B (en) * 2006-01-03 2007-12-11 Univ Nat Chiao Tung Copper metalized ohmic contact electrode of compound semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051373A (en) * 1989-02-16 1991-09-24 Sanyo Electric Co., Ltd. Method of fabricating MMIC semiconductor integrated circuits using the RF and DC measurements of an active device on a substrate to design the passive elements, which are then E-beam written to the substrate
JP2001156179A (ja) * 1999-11-26 2001-06-08 Nec Corp 化合物半導体集積回路の製造方法
JP2002064183A (ja) * 2000-08-17 2002-02-28 Sony Corp 半導体装置およびその製造方法
JP2006108655A (ja) * 2004-09-13 2006-04-20 Matsushita Electric Ind Co Ltd 半導体装置、高周波増幅器および携帯情報端末
WO2007128075A2 (en) * 2006-05-08 2007-11-15 Epitactix Pty Ltd Method and apparatus for manufacture of semiconductors and resulting structures, devices, circuits, and components

Also Published As

Publication number Publication date
CN114975102A (zh) 2022-08-30

Similar Documents

Publication Publication Date Title
US7449729B2 (en) Heterojunction bipolar transistor and method for fabricating the same
WO2024032437A1 (zh) 半导体结构及其形成方法
CN100487910C (zh) 异质结双极型晶体管及其制造方法
US5344786A (en) Method of fabricating self-aligned heterojunction bipolar transistors
JPH11288949A (ja) 半絶縁ポリシリコン（ｓｉｐｏｓ）を用いた電力半導体装置及びその製造方法
EP0786816A2 (en) Bipolar transistor having an improved epitaxial base region and method of fabricating the same
CN114975102B (zh) 集成异质结双极晶体管及其制作方法
JP2851044B2 (ja) 半導体装置の製造方法
JPH05136159A (ja) ヘテロ接合型バイポーラトランジスタ及びその製造方法
US5162244A (en) Bipolar transistor and manufacturing method thereof
KR100205018B1 (ko) 이종접합 트랜지스터의 베이스층을 이용한 커패시터의제조방법
KR100497840B1 (ko) 이종접합 바이폴라 트랜지스터의 제조방법, 그에 의해제조된 이종접합 바이폴라 트랜지스터
CN113066762B (zh) 一种双极型场效应晶体管及其制备方法
CN218730945U (zh) 一种集成异质结双极晶体管
CN218867113U (zh) 毫米波薄膜肖特基二极管
JPS63124465A (ja) バイポ−ラトランジスタの製造方法
KR100273396B1 (ko) 이종접합 바이폴라 트랜지스터 및 그 제조방법
JP2976664B2 (ja) バイポーラトランジスタの製造方法
CN116825739A (zh) 异质结双极型晶体管及异质结双极型晶体管的形成方法
JP3321229B2 (ja) 半導体装置
JP2724490B2 (ja) ゲートターンオフサイリスタの製造方法
JP2001085723A (ja) 太陽電池、及び太陽電池の製造方法
CN115497825A (zh) 一种集成静电防护的hemt结构及其制作方法
JPS6231165A (ja) ヘテロ接合化合物半導体装置
CN118156131A (zh) 一种具有支撑结构的浮空t型栅hemt器件及其制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant