CN114930524A - 芯片和集成芯片 - Google Patents

芯片和集成芯片 Download PDF

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Publication number
CN114930524A
CN114930524A CN201980101374.3A CN201980101374A CN114930524A CN 114930524 A CN114930524 A CN 114930524A CN 201980101374 A CN201980101374 A CN 201980101374A CN 114930524 A CN114930524 A CN 114930524A
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CN
China
Prior art keywords
die
dies
chip
frame
interconnect layer
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Pending
Application number
CN201980101374.3A
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English (en)
Inventor
黄伟朝
李涛
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN114930524A publication Critical patent/CN114930524A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种芯片(100)，该芯片(100)包括：互连层(110)和设置在该互连层(110)上的多个裸片，该多个裸片包括第一裸片(1)和第二裸片(2)，第一裸片(1)和第二裸片(2)之间通过边缘区域直接进行走线互联，其中，该边缘区域指示该互连层(110)中边框以外的区域，该边框指示该多个裸片在该互连层(110)中的外围边界。由于该互连层中(110)上述边缘区域没有信号走线，不会受到其他数据信号的干扰，因此，第一裸片(1)和第二裸片(2)之间通过边缘区域走线互联，可以降低这两个裸片之间传输数据信号的延时，提高数据传输效率。

Description

PCT国内申请，说明书已公开。

Claims (14)

  1. PCT国内申请，权利要求书已公开。
CN201980101374.3A 2019-10-16 2019-10-16 芯片和集成芯片 Pending CN114930524A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/111430 WO2021072670A1 (zh) 2019-10-16 2019-10-16 芯片和集成芯片

Publications (1)

Publication Number Publication Date
CN114930524A true CN114930524A (zh) 2022-08-19

Family

ID=75537494

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980101374.3A Pending CN114930524A (zh) 2019-10-16 2019-10-16 芯片和集成芯片

Country Status (4)

Country Link
US (1) US20220238486A1 (zh)
EP (1) EP4036969A4 (zh)
CN (1) CN114930524A (zh)
WO (1) WO2021072670A1 (zh)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059899A (en) * 1990-08-16 1991-10-22 Micron Technology, Inc. Semiconductor dies and wafers and methods for making
US20090294977A1 (en) * 2008-06-02 2009-12-03 Che-Yuan Jao Semiconductor die and bond pad arrangement method thereof
US8890332B2 (en) * 2010-07-29 2014-11-18 Mosys, Inc. Semiconductor chip layout with staggered Tx and Tx data lines
CN103295996B (zh) * 2012-06-29 2016-06-15 上海天马微电子有限公司 封装基板及其制作方法
US9065722B2 (en) * 2012-12-23 2015-06-23 Advanced Micro Devices, Inc. Die-stacked device with partitioned multi-hop network
CN103413796B (zh) * 2013-07-16 2016-01-06 中国科学院计算技术研究所 一种基板多芯片集成的大端口互连类芯片及实现方法
US10102327B2 (en) * 2014-12-31 2018-10-16 Stmicroelectronics, Inc. Integrated circuit layout wiring for multi-core chips
US9543249B1 (en) * 2015-09-21 2017-01-10 Dyi-chung Hu Package substrate with lateral communication circuitry
US10289796B2 (en) * 2016-12-06 2019-05-14 Synopsys, Inc. Automated place-and-route method for HBM-based IC devices

Also Published As

Publication number Publication date
EP4036969A1 (en) 2022-08-03
WO2021072670A1 (zh) 2021-04-22
US20220238486A1 (en) 2022-07-28
EP4036969A4 (en) 2022-11-02

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