CN114914243A

CN114914243A - Memory device

Info

Publication number: CN114914243A
Application number: CN202210531250.2A
Authority: CN
Inventors: 冯立伟
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-05-08
Filing date: 2020-05-08
Publication date: 2022-08-16
Also published as: CN111540738B; CN111540738A

Abstract

The invention provides a memory, a substrate comprises a plurality of active regions extending along a first preset direction; the substrate is provided with a plurality of bit line structures which extend along a second preset direction and penetrate through corresponding active regions, the parts of the bit line structures, which are positioned on the substrate, form a first bit line structure, and the parts of the bit line structures, which extend from the substrate to the active regions, form a second bit line structure; a metal silicide layer is formed between the second bit line structure and the active region, and the active region is electrically connected with the second bit line structure through the metal silicide layer.

Description

Memory device

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a memory.

Background

A Memory, such as a Dynamic Random Access Memory (DRAM), generally has a Memory cell array including a plurality of Memory cells arranged in an array. The memory also has a plurality of bit line structures, each bit line structure being electrically connected to a corresponding memory cell. At present, an excessive contact resistance between a bit line structure and a corresponding memory cell is one of the reasons for limiting the performance of a memory, and how to reduce the contact resistance between the bit line structure and the corresponding memory cell is a technical problem to be solved.

Disclosure of Invention

The invention aims to provide a memory to reduce the contact resistance between a bit line structure and a corresponding memory cell.

In order to achieve the above object, the present invention provides a memory, comprising:

the device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a plurality of active regions extending along a first preset direction;

a plurality of bit line structures located on the substrate and extending along a second predetermined direction to pass through the corresponding active regions, portions of the bit line structures located on the substrate constituting a first bit line structure, portions of the bit line structures extending from the substrate into the active regions constituting a second bit line structure; and the number of the first and second groups,

and the metal silicide layer is positioned between the second bit line structure and the active region and is used for electrically connecting the active region and the second bit line structure.

Optionally, the bit line structure includes a bit line conductive layer, a bit line shielding layer and an isolation sidewall, the bit line shielding layer covers a top wall of the bit line conductive layer, and the isolation sidewall covers the bit line conductive layer and a sidewall of the bit line shielding layer.

Optionally, the isolation sidewall further covers the sidewall of the metal silicide layer.

Optionally, in a direction perpendicular to the height direction, a width dimension of the metal silicide layer is greater than or equal to a width dimension of the bit line conductive layer.

Optionally, the bottom of the isolation sidewall is located at a first depth position in the substrate, the bottom of the metal silicide layer is located at a second depth position of the substrate, and the first depth position is lower than the second depth position.

Optionally, the material of the metal silicide layer includes one or more of cobalt silicide, titanium silicide, tungsten silicide, molybdenum silicide, tantalum silicide, or platinum silicide.

The invention provides a method for forming a memory, which comprises the following steps:

providing a substrate comprising a plurality of active regions extending along a first predetermined direction;

forming a plurality of bit line structures on the substrate, wherein the bit line structures extend along a second predetermined direction to pass through the corresponding active regions, the parts of the bit line structures on the substrate form a first bit line structure, and the parts of the bit line structures extending from the substrate into the active regions form a second bit line structure; and the number of the first and second groups,

and forming a metal silicide layer between the second bit line structure and the active region to electrically connect the active region and the second bit line structure.

Optionally, the metal silicide layer is formed before forming the plurality of bit line structures, and the step of forming the metal silicide layer includes:

forming a mask layer on the substrate;

forming a plurality of bit line grooves in the mask layer, wherein the bit line grooves extend along a second preset direction, the parts of the bit line grooves, which are positioned on the substrate, form first bit line grooves, and the parts of the bit line structures, which extend from the substrate to the active region, form second bit line grooves; and

and forming the metal silicide layer at the bottom of the second bit line groove.

Optionally, the metal silicide layer is formed at the bottom of the second bit line trench by using a salicide process.

Optionally, the step of forming a plurality of bit line structures on the substrate includes:

forming a bit line conductive layer and a bit line shielding layer in the bit line trench in sequence; and the number of the first and second groups,

and forming an isolation side wall in the bit line groove, wherein the isolation side wall covers the bit line conductive layer and the side wall of the bit line shielding layer.

In the memory provided by the invention, the substrate comprises a plurality of active regions extending along a first preset direction; the substrate is provided with a plurality of bit line structures which extend along a second preset direction and penetrate through corresponding active regions, the parts of the bit line structures, which are positioned on the substrate, form a first bit line structure, and the parts of the bit line structures, which extend from the substrate to the active regions, form a second bit line structure; a metal silicide layer is formed between the second bit line structure and the active region, and the active region is electrically connected with the second bit line structure through the metal silicide layer.

Drawings

FIG. 1 is a flow chart of a method for forming a memory according to an embodiment of the invention;

FIGS. 2a to 2d are schematic structural diagrams formed by a method for forming a memory according to an embodiment of the invention;

fig. 2e is a simplified layout of a memory according to a first embodiment of the present invention, where fig. 2a to fig. 2d are schematic cross-sectional views of the structure in fig. 2e along directions a-a 'and b-b';

FIG. 3 is a schematic structural diagram of a memory according to a second embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a memory according to a third embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a memory according to a fourth embodiment of the present invention;

wherein the reference numerals are:

100-a substrate; AA-active region; SIT-trench isolation structure; 300 a-a first barrier layer; 300 b-a second barrier layer; 310-a mask layer; 500-a metal silicide layer;

a WL-word line structure; 200 a-gate oxide layer; 200 b-a gate conductive layer; 200 c-a gate insulating layer;

a BL-bit line structure; 400 a-a first bit line conductive layer; 400 b-a second bit line conductive layer; 400 c-a third bitline conductive layer; 400 d-bit line masking layer; 400 e-isolation side wall; 400 f-bit line conductive layer;

BL1 — first bit line structure; BL1 — second bit line structure; tr-bit line trenches; tr 1-first bit line trench; tr 2-second bit line trench;

x1 — width dimension of metal silicide layer;

x2-width dimension of bit line conductive layer;

h1 — first depth position;

h2-second depth position.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

Fig. 2d is a schematic diagram of a partial structure of the memory in this embodiment, and fig. 2e is a simplified layout of the memory in fig. 2d, wherein fig. 2d is a schematic cross-sectional diagram of the memory in fig. 2e in a direction a-a 'and a direction b-b'.

As shown in fig. 2d and 2e, the memory includes: a substrate 100 and a word line structure WL formed within the substrate 100. The substrate 100 has a plurality of active areas AA extending along a first predetermined direction (Z direction) and trench isolation structures STI formed therein, the trench isolation structures STI separating adjacent active areas AA. The active areas AA are arranged in an array mode, and the active areas AA are mutually independent through the groove isolation structure STI, so that mutual interference among the active areas AA is avoided.

Further, a word line trench is formed in the substrate 100, and the word line trench is used for accommodating the word line structure WL. Specifically, the word line trench extends along a third predetermined direction (X direction) to pass through the corresponding active area AA and the trench isolation structure STI, and the word line trench has a portion located in the trench isolation structure STI and a portion located in the active area AA.

In this embodiment, the size of the opening of the word line trench in the trench isolation structure STI is larger than the size of the opening of the word line trench in the active area AA. Further, the bottom position of the word line trench in the trench isolation structure STI is also lower than the bottom position of the word line trench in the active area AA.

As described above, the word line trench passes through the corresponding active area AA and the trench isolation structure STI, and thus the word line structure WL also passes through the active area AA and the trench isolation structure STI accordingly. In this embodiment, the bottom position of the word line structure WL in the trench isolation structure STI is lower than the bottom position of the word line structure WL in the active area AA, and the top position of the word line structure WL is located at the same height position. The word line structure WL is formed in the word line trench, so a channel region buried in the active region AA to have a bent structure may be formed. Thus, the curved channel region can have a relatively large length as compared with the linear channel region, and short channel effects of the transistor can be improved.

With continued reference to fig. 2d and 2e, the word line structure WL includes a gate dielectric layer 200a, a gate conductive layer 200b and a gate insulating layer 200c, wherein the gate dielectric layer 200a covers an inner wall of the word line trench, the gate conductive layer 200b is located on the gate dielectric layer 200a and fills the word line trench with a partial depth, and the gate insulating layer 200c is located on the gate conductive layer 200b and fills the remaining depth of the word line trench.

Further, the active area AA is used to form a memory transistor, for example, a source/drain region may be further formed in the active area AA, where the source/drain region includes a first source/drain region and a second source/drain region, and the first source/drain region and the second source/drain region are respectively located at two sides of the word line structure WL to jointly form the memory transistor. It is understood that the bottom portions of the first and second source/drain regions are lower than the top portion of the gate conductive layer 200b, so that there is an overlapping region between the first and second source/drain regions and the gate conductive layer 200 b.

With continued reference to fig. 2d and fig. 2e, in the present embodiment, a barrier layer is further formed on the substrate 100, and the barrier layer includes, from bottom to top, a first barrier layer 300a and a second barrier layer 300 b. The material of the first barrier layer 300a may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and a combination thereof. The material of the second barrier layer 300b may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and a combination thereof.

With continued reference to fig. 2d and 2e, a plurality of bit line structures BL are formed on the substrate 100 and extend along a second predetermined direction (Y direction) to pass through the corresponding active areas AA. Referring to fig. 2d, the bit line structure BL includes a bit line conductive layer, and the bit line conductive layer includes a first bit line conductive layer 400a, a second bit line conductive layer 400b, and a third bit line conductive layer 400c stacked in sequence from bottom to top. The material of the first bit line conductive layer 400a includes, for example, doped polysilicon, the material of the second bit line conductive layer 400b includes, for example, titanium nitride, and the material of the third bit line conductive layer 200c includes, for example, tungsten.

Further, the bit line structure BL may further include a bit line shielding layer 400d and an isolation sidewall spacer 400 e. The bit line shielding layer 400d is formed above the bit line conductive layers stacked in sequence, and the isolation sidewall 400e at least covers the sidewalls of the bit line conductive layers stacked in sequence and the sidewalls of the bit line shielding layer 400 d.

In this embodiment, in the vertical height direction, the width dimensions of the first bit line conductive layer 400a, the second bit line conductive layer 400b, the third bit line conductive layer 400c, and the bit line shielding layer 400d are equal, and the isolation sidewall 400e covers the sidewalls of the bit line conductive layer and the bit line shielding layer 400 d. Referring to fig. 2d, the bit line conductive layer and the bit line shielding layer 400d have a width dimension X2 in the vertical height direction.

With continuing reference to fig. 2d and 2e, each of the bit line structures BL has a portion located on the substrate 100 and a portion extending from the substrate 100 into the active area AA. For convenience of description, a portion of the bit line structure BL on the substrate 100 is referred to as a first bit line structure BL1, and a portion of the bit line structure BL extending from the substrate 100 into the active region AA is referred to as a second bit line structure BL 2. The first bit line structure BL1 is located on the substrate 100 and directly above the trench isolation structure STI; the second bit line structure BL2 extends from the substrate 100 through the first barrier layer 300a and the second barrier layer 300b and into the active area AA. Alternatively, it can be understood that the first bit line structure BL1 and the second bit line structure BL2 are two parts of one bit line structure BL.

With reference to fig. 2d, a metal silicide layer 500 is formed between the second bit line structure BL2 and the active area AA, and the upper and lower surfaces of the metal silicide layer 500 are electrically connected to the first bit line conductive layer 400a of the second bit line structure BL2 and the active area AA, respectively, so as to electrically connect the bit line structure BL and the active area AA. It can be understood that the metal silicide layer 500 makes an ohmic contact between the bit line structure BL and the active area AA, thereby reducing a contact resistance between the bit line structure BL and the active area AA and improving the performance of the memory.

Optionally, the material of the metal silicide layer 500 may be one or more of cobalt silicide, titanium silicide, polycide, tungsten silicide, molybdenum silicide, tantalum silicide, or platinum silicide, which is not limited in the present invention.

Further, in the present embodiment, a width dimension X1 of the metal silicide layer 500 is greater than a width dimension X2 of the bit line conductive layer in a direction perpendicular to the height direction. That is, the bit line conductive layer and the bit line shielding layer 400d are both formed above the metal silicide layer 500, and the width of the metal silicide layer 500 is large, so that the bottom of the bit line conductive layer can be ensured to be completely contacted with the active region AA through the metal silicide layer 500, and the contact resistance between the bit line structure BL and the active region AA is further reduced.

The method for forming the memory device according to the present embodiment will be described in detail with reference to fig. 1 and fig. 2a to 2 e. Fig. 1 is a schematic flow chart of a method for forming a memory according to an embodiment of the present invention, and fig. 2a to 2e are schematic diagrams of structures formed in a manufacturing process of the memory according to an embodiment of the present invention.

As shown in fig. 1, the method for forming the memory includes:

step S100: providing a substrate, wherein the substrate comprises a plurality of active regions extending along a first preset direction;

step S200: forming a plurality of bit line structures on the substrate, wherein the bit line structures extend along a second predetermined direction to penetrate through the corresponding active regions, the parts of the bit line structures on the substrate form a first bit line structure, and the parts of the bit line structures extending from the substrate to the active regions form a second bit line structure; and the number of the first and second groups,

step S300: and forming a metal silicide layer between the second bit line structure and the active region to electrically connect the active region and the second bit line structure.

Specifically, referring to fig. 2a, step S100 is performed to provide a substrate 100, wherein a trench isolation structure STI is formed in the substrate 100, and a plurality of active regions AA extending along a first predetermined direction are defined by the trench isolation structure SIT.

Continuing next with fig. 2a, word line structures WL are formed in the substrate 100, the word line structures WL extending in a third predetermined direction and passing through the respective active areas AA and trench isolation structures STI. Further, the lateral width (width dimension in the direction perpendicular to the height) of the word line structure WL located in the active area AA is smaller than the lateral width of the word line structure WL located in the trench isolation structure STI; the bottom of the word line structure WL located in the active area AA is lower than the bottom of the word line structure WL located in the trench isolation structure STI.

The steps of forming the word line structure WL may be as follows:

forming a word line trench (not shown) in the substrate 100 and extending in a third predetermined direction;

forming a gate dielectric layer 200a on the substrate 100, wherein the gate dielectric layer 200a covers the inner wall of the word line trench, and the gate dielectric layer 200a can be used as an insulating layer for isolating the word line from the active area AA;

next, a gate conductive layer 200b is formed in the word line trench, and the gate conductive layer 200b is a conductive film, such as polysilicon or tungsten. The gate conductive layer 200b fills a partial depth of the word line trench; specifically, for example, the height of the gate conductive layer 200b in the word line trench may be reduced through an etch-back process, so that the top surface of the gate conductive layer 200b is lower than the upper surface of the substrate 100. Thus, the lower portion of the word line trench is filled with the gate conductive layer 200b, and the upper portion of the word line trench is still in an empty state;

forming a gate insulating layer 200c on the gate conductive layer 200b, wherein the gate insulating layer 200c covers the gate conductive layer 200b and completely fills the word line trench, and the gate dielectric layer 200a, the gate conductive layer 200b and the gate insulating layer 200c together form the word line structure WL.

It should be noted that although the drawings of the present embodiment do not show a mask layer on the surface of the substrate 100, it should be appreciated that, during the etching process of the substrate 100 to form the word line trench, a mask layer is usually formed on the surface of the substrate 100 to prevent the etching of the region of the substrate 100 that is not corresponding to the trench.

With continued reference to fig. 2a, the method of forming the memory further comprises: forming a source/drain region in the substrate 100, wherein a side edge boundary of the source/drain region extends to a side wall of the word line trench close to the top opening, and a bottom boundary of the source/drain region is lower than a top position of the gate conductive layer 200b, so that the source/drain region and the gate conductive layer 200b have an overlapping region opposite to each other, and in the overlapping region, the gate conductive layer 200b and the source/drain region are separated from each other by the gate dielectric layer 200 a.

Specifically, the source/drain regions include a first source/drain region and a second source/drain region, and the first source/drain region and the second source/drain region are respectively located at two sides of the word line structure WL. In this embodiment, the side edge boundary of the first source/drain region further extends to the sidewall of the trench isolation structure STI.

It should be noted that, in this embodiment, after the word line trench is formed and the word line structure WL is formed, the source and drain regions are prepared. However, in other embodiments, the source and drain regions may be formed first, and then the word line trench and the word line structure WL are sequentially prepared, which is not limited herein.

With continued reference to fig. 2a, a first barrier layer 300a and a second barrier layer 300b are sequentially formed on the substrate 100 from bottom to top, and the first barrier layer 300a and the second barrier layer 300b together form a barrier layer. The barrier layer may protect the substrate 100 during a subsequent etching process.

Referring to fig. 2b, steps S200 and S300 are performed to form a bit line structure on the substrate 100. In forming the bit line structure, the bit line trench Tr needs to be formed first. Specifically, a mask layer 310 is formed on the barrier layer, and then the mask layer 310 is patterned to form a bit line trench Tr, which needs to extend in a second predetermined direction since the bit line trench Tr forms a bit line structure in a subsequent step.

As shown in fig. 2b, a portion of the bit line trench Tr is located in the mask layer 310, and another portion of the bit line trench Tr extends from the mask layer 310 through the barrier layer and down into the active area AA of the substrate 100. For convenience of description, a portion of the bit line trench Tr in the mask layer 310 is referred to as a first bit line trench Tr1, and a portion of the bit line trench Tr extending from the mask layer 310 to the active area AA of the substrate 100 is referred to as a second bit line trench Tr 2.

It is understood that the first bit line trench Tr1 may be formed by etching the mask layer 310; the second bit line trench Tr2 is formed by sequentially etching the mask layer 310, the barrier layer and a portion of the active area AA of the substrate 100 from the top down. Due to the shrinking device size, the lateral dimension between adjacent word line structures WL is further shortened, and in order to increase the bit line structure, the second bit line trench Tr2 is generally extended laterally above the gate conductive layer 200b of the word line structure WL. That is, when the second bit line trench Tr2 is formed, a partial height of the sidewall of the gate insulating layer 200c of the word line structure WL is also etched away, so that the second bit line trench Tr2 is laterally widened.

Further, the bottom of the second bit line trench Tr2 needs to be higher than the top of the gate conductive layer 200b in the word line structure WL so as to prevent damage to the gate conductive layer 200b in the word line structure WL 2.

Referring to fig. 2c, a metal silicide layer 500 is formed in the second bit line trench Tr2, the metal silicide layer 500 covering the bottom of the second bit line trench Tr 2.

In this embodiment, the metal silicide layer 500 is formed by a salicide process. Specifically, taking the material of the metal silicide layer 500 as titanium silicide as an example, the forming step of the metal silicide layer 500 includes:

first, a titanium metal layer is formed on the entire surface of the substrate 100, the titanium metal layer covering the surface of the barrier layer, the surface of the mask layer 310, and the inner walls of the first and second bit line trenches Tr1 and Tr 2;

then, performing a first rapid annealing treatment to enable a part (the titanium metal layer at the bottom of the second bit line trench Tr 2) where the titanium metal layer is in contact with the active area AA to react with silicon in the substrate 100 to generate titanium silicide;

then, removing all the titanium metal layer which does not participate in the reaction by a wet etching process such as ammonium hydroxide and hydrogen peroxide, and leaving the titanium silicide at the bottom of the second bit line groove Tr 2;

finally, a second rapid annealing process is performed to produce a metal silicide phase having a low resistivity.

In the present embodiment, the metal silicide layer 500 is formed by a salicide process, so that alignment errors can be avoided, but it should be understood that the metal silicide layer 500 may be formed by other processes, and the invention is not limited thereto.

Referring to fig. 2d, a bit line structure BL is formed in the bit line trench Tr and the mask layer is removed. The bit line structure BL comprises a bit line conductive layer, and the bit line conductive layer comprises three conductive material layers which are stacked in sequence and are made of different materials. Based on this, the formed bit line structure BL includes the first bit line conductive layer 400a, the second bit line conductive layer 400b, and the third bit line conductive layer 400 c. Further, the bit line structure BL further includes a bit line shielding layer 400d, and the bit line shielding layer 400d may be a patterned film layer and is formed above the bit line conductive layer. Alternatively, for example, the patterned bit line shielding layer 400d is used to sequentially perform a patterning process on the underlying conductive material layer. In this embodiment, the method for forming the bit line structure BL further includes: isolation spacers 400e are formed on the sidewalls of the first bit line conductive layer 400a, the second bit line conductive layer 400b, the third bit line conductive layer 400c, and the bit line shielding layer 400 d.

Referring to fig. 2d, the bit line structure BL includes a first bit line structure BL1 and a second bit line structure BL2, the first bit line structure BL1 is located on the substrate 100, the second bit line structure BL2 extends from the substrate 100 to the active region, and the second bit line structure BL2 is formed on the metal silicide layer 500 and electrically connected to the active region AA through the metal silicide layer 500.

Example two

Fig. 3 is a partial structural diagram of the memory in this embodiment. As shown in fig. 3, the difference from the first embodiment is that, in the present embodiment, the bit line conductive layer 400f in the bit line structure BL is a single film layer, and the material of the bit line conductive layer 400f is the same as that of the gate conductive layer 200 b.

Specifically, the bit line structure BL includes a single-layer bit line conductive layer 400f, a bit line shielding layer 400d, and an isolation sidewall 400e, where the bit line shielding layer 400d covers the bit line conductive layer 400f, and the isolation sidewall 400e covers the bit line conductive layer 400f and a sidewall of the bit line shielding layer 400 d. In this embodiment, the gate conductive layer 200b is made of doped polysilicon, and the bit line conductive layer 400f is also made of doped polysilicon, but the invention is not limited thereto.

With reference to fig. 3, a method for forming the memory of the present embodiment may be the same as the method for forming the memory of the first embodiment. The only difference is that, when the bit line conductive layer of the bit line structure BL is formed, only a film layer of the same material as the gate conductive layer 200b is formed, and then the bit line conductive layer 400f is formed by etching. Compared with the first embodiment, the present embodiment simplifies the structure of the bit line structure BL, and the process for forming the bit line structure BL can be simpler.

EXAMPLE III

Fig. 4 is a schematic diagram of a partial structure of the memory in this embodiment. As shown in fig. 4, the difference from the first embodiment is that, in the present embodiment, the isolation sidewall spacers 400e also cover the sidewalls of the metal silicide layer 500.

Specifically, a gap is formed between the metal silicide layer 500 and the bit line conductive layer and the sidewall of the second bit line trench, and the isolation sidewall spacers 400e are filled in the gap to cover the metal silicide layer 500 and the sidewall of the bit line conductive layer at the same time. At this time, a width dimension X1 of the metal silicide layer 500 is equal to a width dimension X2 of the bit line conductive layer in a direction perpendicular to the height direction.

In this embodiment, the metal silicide layer 500 and the isolation sidewall spacers 400e are both formed in the bit line trenches, and the bottom of the metal silicide layer 500 and the isolation sidewall spacers 400e are located at the same depth position of the substrate 100.

With reference to fig. 4, a method for forming the memory of the present embodiment may be the same as the method for forming the memory of the first embodiment. The only difference is that in the process of forming the bit line conductive layer, the sidewall of the metal silicide layer 500 may also be partially etched, so that the width of the metal silicide layer 500 is equal to the width of the formed bit line conductive layer. Compared to the first embodiment, the isolation sidewall 400e in this embodiment can simultaneously protect the metal silicide layer 500 and the bit line conductive layer, and can prevent the metal silicide layer 500 from interfering with the word line structure WL.

Example four

Fig. 5 is a schematic diagram of a partial structure of the memory in this embodiment. As shown in fig. 5, the difference from the third embodiment is that, in the present embodiment, the depth position of the bottom of the isolation sidewall 400e in the substrate 100 is lower than the depth position of the bottom of the metal silicide layer 500 in the substrate 100.

Specifically, with reference to fig. 5, the bottom of the isolation sidewall 400e is located at a first depth position H1 of the substrate 100, the bottom of the metal silicide layer 500 is located at a second depth position H2 of the substrate 100, and the first depth position H1 is lower than the second depth position H2. Alternatively, it can be understood that the metal silicide layer 500 is located in a bit line trench, and the isolation sidewall spacers 400e are located in the bit line trench and extend downward from the bottom of the bit line trench by a certain depth.

It is understood that, in the present embodiment, the width dimension X1 of the metal silicide layer 500 is equal to the width dimension X2 of the bit line conductive layer in the direction perpendicular to the height direction.

With reference to fig. 5, a method for forming the memory of the present embodiment may be the same as the method for forming the memory of the third embodiment. The only difference is that in the process of forming the bit line conductive layer, the sidewall of the metal silicide layer 500 may also be partially etched, so that the width of the metal silicide layer 500 is equal to the width of the formed bit line conductive layer, and the substrate 100 at the bottom of the bit line trench is also etched to a certain depth, so that the portions of the bit line trench at both ends of the metal silicide layer 500 extend into the substrate 100 to the first depth position H1. Next, the isolation sidewall spacers 400e are formed in the bit line trenches, and the isolation sidewall spacers 400e extend upward from the first depth position H1 and cover the sidewalls of the metal silicide layer 500 and the bit line conductive layer.

Compared with the third embodiment, the isolation sidewall spacers 400e in this embodiment can better protect the metal silicide layer 500 and the bit line conductive layer, and improve the effect of preventing the metal silicide layer 500 from interfering with the word line structure WL.

In summary, in the memory provided in the embodiments of the present invention, the substrate includes a plurality of active regions extending along a first predetermined direction; the substrate is provided with a plurality of bit line structures which extend along a second preset direction and penetrate through corresponding active regions, the parts of the bit line structures, which are positioned on the substrate, form a first bit line structure, and the parts of the bit line structures, which extend from the substrate to the active regions, form a second bit line structure; a metal silicide layer is formed between the second bit line structure and the active region, and the active region is electrically connected with the second bit line structure through the metal silicide layer.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A memory, comprising:

the substrate comprises a plurality of active regions extending along a first preset direction and trench isolation structures used for separating the adjacent active regions;

the metal silicide layer is positioned between the second bit line structure and the active region and is used for electrically connecting the active region and the second bit line structure;

the bit line structure comprises a bit line conducting layer, a bit line shielding layer and an isolation side wall, wherein the bit line shielding layer covers the top wall of the bit line conducting layer, the isolation side wall at least covers the bit line conducting layer and the bit line shielding layer, and the isolation side wall is in direct contact with the metal silicide layer and the groove isolation structure.

2. The memory of claim 1, wherein a bottom of the isolation sidewall is at a first depth in the substrate, a bottom of the metal silicide layer is at a second depth in the substrate, and the first depth is lower than the second depth.

3. The memory of claim 1, wherein a width dimension of the metal silicide layer in a direction perpendicular to a height direction is greater than or equal to a width dimension of the bit line conductive layer.

4. The memory of claim 1, wherein the material of the metal silicide layer comprises one or more of cobalt silicide, titanium silicide, tungsten silicide, molybdenum silicide, tantalum silicide, or platinum silicide.

5. The memory of claim 1, wherein a bottom surface of the metal silicide layer is lower than a bottom surface of the isolation sidewall.

6. The memory of claim 1, wherein a top surface of the metal silicide layer is lower than a top surface of the substrate.

7. The memory of claim 1, further comprising, in a word line trench of the substrate:

the word line structure comprises a gate dielectric layer, a gate conducting layer and a gate insulating layer, wherein the gate dielectric layer covers the inner wall of the word line groove, the gate conducting layer is positioned on the gate dielectric layer and fills the word line groove with partial depth, the gate insulating layer is positioned on the gate conducting layer and fills the residual depth of the word line groove, and the metal silicide layer is in contact with the gate insulating layer.