CN114914158A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN114914158A CN114914158A CN202210507998.9A CN202210507998A CN114914158A CN 114914158 A CN114914158 A CN 114914158A CN 202210507998 A CN202210507998 A CN 202210507998A CN 114914158 A CN114914158 A CN 114914158A
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 110
- 229910052751 metal Inorganic materials 0.000 claims abstract description 96
- 239000002184 metal Substances 0.000 claims abstract description 91
- 238000002955 isolation Methods 0.000 claims abstract description 57
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 46
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000005259 measurement Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 239000007789 gas Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910001260 Pt alloy Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
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- 229910052698 phosphorus Inorganic materials 0.000 description 2
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- 229910000531 Co alloy Inorganic materials 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QXZUUHYBWMWJHK-UHFFFAOYSA-N [Co].[Ni] Chemical compound [Co].[Ni] QXZUUHYBWMWJHK-UHFFFAOYSA-N 0.000 description 1
- LMHKOBXLQXJSOU-UHFFFAOYSA-N [Co].[Ni].[Pt] Chemical compound [Co].[Ni].[Pt] LMHKOBXLQXJSOU-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
The invention provides a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: providing a substrate, forming a grid structure and a side wall on the substrate, and forming a lightly doped region in the substrate at the bottom of the side wall; forming a self-aligned metal silicide barrier layer; etching the self-aligned metal silicide barrier layer in the self-aligned metal silicide forming area, and forming an isolation structure by using the residual part of the self-aligned metal silicide barrier layer at the corner formed by the side wall and the substrate, wherein the isolation structure is positioned at the bottom of the side wall, and the longitudinal section of the isolation structure is triangular; forming a metal layer; and carrying out heat treatment on the substrate to enable the metal layer to react with the substrate to form a self-aligned metal silicide layer, wherein the isolation structure enables a space to exist between the self-aligned metal silicide layer on the substrate and the lightly doped region, so that the on-resistance is reduced, the working efficiency of the device is improved, and the reliability of the device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the continuous reduction of the feature size (CD) of a semiconductor device, the contact resistance between the semiconductor device such as a MOS field effect transistor and an upper interconnection structure has an increasingly large influence on the device performance, and a common method for reducing the contact resistance in the prior art is to form a self-aligned metal Silicide (Silicide) on a contact electrode of the device.
In the manufacturing process of semiconductor devices, some devices need a salicide process, some devices need a non-salicide process, and for devices needing the non-salicide process, the device needing the non-salicide process needs to be covered by a material which does not react with metal by using the characteristics of the salicide. This material used to cover the device that needs to be salicided is called a Self-Aligned metal silicide Block (SAB).
Fig. 1 to 4 are schematic structural diagrams of steps of a conventional method for forming salicide. The existing forming method of the self-aligned metal silicide comprises the following steps:
firstly, as shown in fig. 1, a substrate 10 is provided, a gate structure 11 is formed on the substrate 10, the gate structure 11 includes a gate dielectric layer 11a and a polysilicon gate 11b which are stacked in sequence, a sidewall 12 is formed on a sidewall of the gate structure 11, and the sidewall 12 includes an oxide layer 12a and a nitride layer 12 b. Lightly doped regions 13 and 14 are formed in the substrate 10 at the bottom of the side wall 12, heavily doped regions 15 and 16 are formed in the substrate at the side of the side wall 12 far away from the gate structure 11, the heavily doped region 15 is adjacent to the lightly doped region 13, and the heavily doped region 16 is adjacent to the lightly doped region 14. The lightly doped regions 13, 14 serve as lightly doped regions LDD, and the heavily doped regions 15, 16 serve as source or drain doped regions, respectively.
Next, as shown in fig. 2, a salicide block layer 17 is formed, and the salicide block layer 17 covers the substrate 10, the gate structure 11, and the sidewall 12. The substrate 10 includes a non-salicide forming region and a salicide forming region. The salicide block layer 17 over the non-salicide formation region is retained and the salicide block layer 17 over the salicide formation region is removed (the non-salicide formation region is not shown in fig. 1-4, only the salicide formation region is shown). The salicide block layer 17 is typically completely removed by a combination of dry etching and wet etching.
Next, as shown in fig. 3, a metal layer 18 is formed, and fig. 3 only shows a salicide formation region, so that the salicide block layer 17 has been removed, and the metal layer 18 covers the substrate 10, the gate structure 11, and the sidewall 12.
Next, as shown in fig. 3, the substrate 10 is heat-treated, the metal layer 18 and the contacted silicon react and self-align to form a salicide layer 19, and the metal layer 18 without the salicide layer 19 is self-aligned and removed. The salicide layer 19 is located on the surface of the substrate 10 and the top surface of the gate structure 11.
Referring to fig. 3 and 4, in the forming process of the salicide layer 19, metal elements in the metal layer 18 are not only longitudinally diffused into the substrate 10, but also laterally diffused in the substrate 10, so that the salicide layer 19 formed on the surface of the substrate 10 is diffused into the lightly doped regions 13 and 14 under the sidewall 12 (as shown by the dotted circles in fig. 4) to form non-ohmic contact with the lightly doped regions 13 and 14, and the on resistance (Rdson) is increased, which results in a decrease in the operating efficiency and a decrease in the reliability of the device.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a forming method thereof, so that a distance exists between a self-aligned metal silicide layer formed on a substrate and a lightly doped region, the on-resistance is reduced, the working efficiency of a device is improved, and the reliability of the device is improved.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, comprising the steps of:
providing a substrate, wherein a grid structure and a side wall covering the side wall of the grid structure are formed on the substrate, and a lightly doped region is formed in the substrate at the bottom of the side wall;
forming a self-aligned metal silicide blocking layer, wherein the self-aligned metal silicide blocking layer covers the substrate, the grid structure and the side wall;
etching the self-aligned metal silicide barrier layer in the self-aligned metal silicide forming area, and forming an isolation structure at the rest part of the self-aligned metal silicide barrier layer at the corner formed by the side wall and the substrate, wherein the isolation structure is positioned at the bottom of the side wall, and the longitudinal section of the isolation structure is triangular;
forming a metal layer, wherein the metal layer covers the substrate, the gate structure, the side wall and the isolation structure; and the number of the first and second groups,
and carrying out heat treatment on the substrate to enable the metal layer to react with the substrate to form a self-aligned metal silicide layer, wherein the isolation structure enables a space to exist between the self-aligned metal silicide layer on the substrate and the lightly doped region.
Optionally, the salicide block layer is a stack layer of silicon oxide and silicon nitride or a silicon-rich oxide layer.
Optionally, the salicide block layer in the salicide formation region is dry etched to form the isolation structure.
Optionally, the dry etching comprises three stages, and the etching gas in the first stage comprises CH 3 F、CH 4 Ar, the air pressure is between 50mtorr and 200mtorr, the power is between 700W and 900W, and the etching time is between 1min and 2 min; in the second stage, etching is carried out by adopting an end point measurement mode, and etching gas contains CH 3 F、CH 4 Ar, the air pressure is between 50mtorr and 200mtorr, and the power is between 400W and 600W; the etching gas of the third stage contains CH 2 F 3 Or CH 3 F, the air pressure is between 30mtorr and 100mtorr, the power is between 200W and 400W, and the etching time is between 5s and 15 s.
Optionally, the self-aligned metal silicide formation region is defined by a photoresist pattern formed by a photolithography process, and the photoresist pattern covers the non-self-aligned metal silicide formation region and exposes the self-aligned metal silicide formation region.
Optionally, after forming the isolation structure and before forming the metal layer, the method further includes: and removing the photoresist pattern.
Optionally, a heavily doped region is further formed in the substrate on one side of the sidewall away from the gate structure, and the heavily doped region is adjacent to the lightly doped region.
Optionally, the step of forming the gate structure, the sidewall, the lightly doped region, and the heavily doped region on the substrate includes:
forming a gate structure on the substrate;
performing first ion implantation on the substrate by taking the grid structure as a mask to form a temporary doped region;
forming a side wall on the side surface of the grid structure;
and performing secondary ion implantation on the substrate by taking the gate structure and the side wall as masks, forming a heavily doped region in the temporary doped region, wherein a region in the temporary doped region where the heavily doped region is not formed is used as the lightly doped region.
Optionally, the doping depth of the heavily doped region is greater than the doping depth of the lightly doped region, and the self-aligned metal silicide layer is located in the surface of the heavily doped region and has a distance from the lightly doped region.
Accordingly, the present invention also provides a semiconductor structure comprising:
the semiconductor device comprises a substrate, a grid structure positioned on the substrate and a side wall covering the side wall of the grid structure, wherein a lightly doped region is formed in the substrate at the bottom of the side wall;
the isolation structure is positioned at the corner formed by the side wall and the substrate, the isolation structure is positioned at the bottom of the side wall, and the longitudinal section of the isolation structure is triangular;
a salicide layer located within the substrate surface, there being a gap between the salicide layer and the lightly doped region.
In the semiconductor structure and the forming method thereof provided by the invention, the self-aligned metal silicide barrier layer in the self-aligned metal silicide forming region is etched, the remaining part of the self-aligned metal silicide barrier layer at the corner formed by the side wall and the substrate is used for forming an isolation structure, when a metal layer is formed subsequently and is subjected to heat treatment, metal elements of the metal layer can also be subjected to transverse diffusion when longitudinal diffusion is carried out, however, the existence of the isolation structure prolongs the path of the transverse diffusion, the metal elements can only be diffused to the bottom of the isolation structure and cannot be further diffused to the bottom of the side wall, so that a space exists between the self-aligned metal silicide layer and the light doped region, the conduction impedance is reduced, the working efficiency of a device is improved, and the reliability of the device is improved.
In addition, only dry etching is carried out on the self-aligned metal silicide barrier layer, compared with the prior art, the wet etching step is saved, the process is simplified, and the production cost is reduced.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention.
Fig. 1-4 are schematic structural diagrams of steps of a conventional method for forming salicide.
Fig. 5 is a flow chart of a method of forming a semiconductor structure according to an embodiment of the invention.
Fig. 6-10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
In fig. 1 to 4:
10-a substrate; 11-a gate structure; 11 a-a gate dielectric layer; 11 b-polysilicon gate; 12-side walls; 12 a-an oxide layer; 12 b-a nitride layer; 13-lightly doped region; 14-lightly doped region; 15-heavily doped region; 16-heavily doped region; 17-self-aligned metal silicide barrier layer; 18-a metal layer; 19-salicide layer.
In fig. 6 to 10:
100-a substrate; 110-a gate structure; 110 a-gate dielectric layer; 110 b-polysilicon gate; 120-side walls; 120 a-an oxide layer; 120 b-a nitride layer; 130-lightly doped region; 140-lightly doped region; 150-heavily doped region; 160-heavily doped region; 170-self-aligned metal silicide barrier layer; 180-isolation structures; 190-a metal layer; 200-salicide layer.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
Fig. 5 is a flow chart of a method of forming a semiconductor structure according to an embodiment of the invention. As shown in fig. 5, the method for forming a semiconductor structure provided in this embodiment includes the following steps:
s01: providing a substrate, wherein a grid structure and a side wall covering the side wall of the grid structure are formed on the substrate, and a lightly doped region is formed in the substrate at the bottom of the side wall;
s02: forming a self-aligned metal silicide blocking layer, wherein the self-aligned metal silicide blocking layer covers the substrate, the grid structure and the side wall;
s03: etching the self-aligned metal silicide barrier layer in the self-aligned metal silicide forming area, and forming an isolation structure by using the self-aligned metal silicide barrier layer at the rest part of the corner formed by the side wall and the substrate, wherein the longitudinal section of the isolation structure is triangular;
s04: forming a metal layer, wherein the metal layer covers the substrate, the gate structure, the side wall and the isolation structure;
s05: and carrying out heat treatment on the substrate to enable the metal layer to react with the substrate to form a self-aligned metal silicide layer, wherein the isolation structure enables a space to exist between the self-aligned metal silicide layer on the substrate and the lightly doped region.
Fig. 6 to 10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention, and a method for forming a semiconductor structure according to an embodiment of the present invention will be described in detail with reference to fig. 5 and 6 to 10.
In step S01, referring to fig. 6, a substrate 100 is provided, a gate structure 110 and a sidewall 120 covering a sidewall of the gate structure 110 are formed on the substrate 100, and lightly doped regions 130 and 140 are formed in the substrate at the bottom of the sidewall 120.
The substrate 100 may be any suitable substrate known to those skilled in the art, and may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In this embodiment, the material of the substrate 100 is preferably silicon.
The gate structure 110 includes a gate dielectric layer 110a and a polysilicon gate 110b stacked in sequence, the gate dielectric layer 110a is preferably made of silicon oxide, and the polysilicon gate 110b is made of polysilicon. The sidewall spacer 120 includes an oxide layer 120a and a nitride layer 120b, wherein the material of the oxide layer 120a is preferably silicon oxide, and the material of the nitride layer 120b is preferably silicon nitride. Lightly doped regions 130 and 140 are formed in the substrate 100 at the bottom of the sidewall 120, and dopants are preferably phosphorus (P) or arsenic (As), and heavily doped regions 150 and 160 are formed in the substrate 100 at a side of the sidewall 120 away from the gate structure 110, and dopants are preferably phosphorus (P) or arsenic (As), where the heavily doped region 150 is adjacent to the lightly doped region 130, and the heavily doped region 160 is adjacent to the lightly doped region 140.
Specifically, a gate dielectric layer 110a and a polysilicon gate 110b are sequentially formed on the substrate 100 to form a gate structure 110; performing a first ion implantation on the substrate 100 by using the gate structure 110 as a mask to form a temporary doped region, where the temporary doped region is located in the substrate 100 at two sides of the gate structure 110. Then, an oxide layer 120a and a nitride layer 120b are sequentially formed on the side surface of the gate structure 110 to form a sidewall spacer 120, and the sidewall spacer 120 is located on the two side walls of the gate structure 110. Then, a second ion implantation is performed on the substrate 100 by using the gate structure 110 and the sidewall 120 as masks, wherein the dose of the second ion implantation is greater than the dose of the first ion implantation, heavily doped regions 150 and 160 are formed in the temporary doped region, and regions in the temporary doped region where the heavily doped regions 150 and 160 are not formed are used as the lightly doped regions 130 and 140. The heavily doped regions 150, 160 have a doping depth greater than the lightly doped regions 130, 140. The lightly doped regions 130, 140 serve as lightly doped regions LDD, and the heavily doped regions 150, 160 serve as source or drain doped regions, respectively.
In step S02, please refer to fig. 7, a salicide block layer 170 is formed, and the salicide block layer 170 covers the substrate 100, the gate structure 110, and the sidewall spacers 120.
In this embodiment, the salicide block layer 170 is a silicon oxide and silicon nitride stacked layer or a silicon-rich oxide layer, and the salicide block layer 170 may be formed by a chemical vapor deposition process.
In step S03, please refer to fig. 8, the salicide block layer 170 in the salicide formation region is etched, and the remaining portion of the salicide block layer at the corner formed by the sidewall 120 and the substrate 100 is formed to form an isolation structure 180, where the isolation structure 180 is located at the bottom of the sidewall, and a longitudinal cross section of the isolation structure 180 is triangular.
The substrate 100 includes a non-salicide formation region where salicide is not required to be formed and thus needs to be covered by the salicide block layer 170, and a salicide formation region where salicide needs to be formed and thus needs to be removed, and a portion of the salicide block layer 170 in the salicide formation region. In fig. 6 to 9, only the salicide formation region is shown.
Specifically, a photoresist layer (not shown) is formed on the substrate 100, the photoresist layer covers the salicide block layer 170, a photoresist pattern (not shown) is formed by performing a photolithography process (i.e., an exposure and development process) on the photoresist layer, the photoresist pattern covers the non-salicide forming region and exposes the salicide forming region, and then the salicide block layer 170 may be etched by using the photoresist pattern as a mask.
Preferably, the salicide block layer 170 is dry etched. The salicide block layer 170 remains at the corner formed by the sidewall spacer 120 and the substrate 100 to form an isolation structure 180. The isolation structure 180 is located at the bottom of the sidewall 120, and a longitudinal section of the isolation structure 180 is triangular (the longitudinal section is a plane perpendicular to the substrate 100), one side of the triangle is adjacent to the sidewall of the sidewall 120, and the other adjacent side is adjacent to the substrate 100.
In this embodiment, the dry etching mainly comprises three stages,the first stage (step1) requires etching away most of the salicide block 170, the etching gas mainly containing CH 3 F (fluoromethane), CH 4 (methane) and Ar (argon), but not limited thereto, the gas pressure is between 50mtorr and 200mtorr, the power is between 700W and 900W, and the etching time is between 1min and 2 min; the second stage (Step2) uses an end point measurement to etch, the etching conditions are similar to Step1, and the etching gas mainly contains CH 3 F (fluoromethane), CH 4 (methane) and Ar (argon), the gas pressure is between 50mtorr and 200mtorr, and the power is between 400W and 600W; the power of the third stage (Step3) is between 200W and 400W, the gas pressure is between 30mtorr and 100mtorr, and the etching gas mainly adopts CH 2 F 3 (trifluoromethane) or CH 3 F (fluoromethane) and the like are selected from gases with high selectivity and moderate F/C ratio (fluorine/carbon ratio) so as to prevent excessive loss of the substrate 100, and the etching time is between 5s and 15 s. Of course, the dry etching conditions are not limited thereto, and the present invention is not limited thereto. The size of the isolation structure 180 may be adjusted by adjusting the thickness of the salicide block layer 170 or the etching conditions.
In the embodiment, only dry etching is required to remove a part of the salicide block layer 170, which saves wet etching steps, simplifies the process and reduces the production cost compared with the prior art.
After the isolation structure 180 is formed, the photoresist pattern is removed. Specifically, the photoresist pattern may be removed by an ashing process.
In step S04, as shown in fig. 9, a metal layer 190 is formed, and the metal layer 190 covers the substrate 100, the gate structure 110, the sidewall spacers 120, and the isolation structure 180.
The metal layer 190 may be made of one of titanium, cobalt, nickel-platinum alloy, nickel-cobalt alloy, or nickel-cobalt-platinum alloy, and may be formed by a physical vapor deposition method.
In step S05, as shown in fig. 10, the substrate 100 is heat-treated to react the metal layer 190 with the substrate 100 to form a salicide layer 200, and the isolation structure 180 allows a space between the salicide layer 200 and the lightly doped regions 130 and 140 on the substrate.
The substrate 100 is subjected to a heat treatment to react the metal layer 190 with the exposed substrate 100 to form a salicide layer 200. The reaction is a metal silicidation reaction, that is, the metal elements of the metal layer 190 diffuse, and react with silicon in the substrate 100 to form a salicide layer 200 on the surface of the heavily doped regions 150 and 160, and simultaneously the metal elements in the metal layer 190 react with silicon on the top of the polysilicon gate 110b in the gate structure 110 to form a salicide layer 200 on the top of the gate structure 110, and simultaneously remove the metal layer 190 without the salicide layer 200.
Referring to fig. 10, in the process of performing heat treatment on the metal layer 190, a metal element in the metal layer 190 diffuses and reacts with silicon in the substrate 100, and the metal element not only longitudinally diffuses into the surface of the substrate 100, but also laterally diffuses in the substrate 100 and diffuses toward the lightly doped regions 130 and 140, and due to the arrangement of the isolation structure 180, a lateral diffusion path of the metal element is extended, so that the metal element can only diffuse to the bottom of the isolation structure 180 and cannot further diffuse to the bottom of the sidewall 120, and a gap exists between the self-aligned metal silicide layer 200 and the lightly doped regions 130 and 140, thereby reducing on-resistance, improving device operating efficiency and improving device reliability.
The spacing between the finally formed salicide layer 200 and the lightly doped regions 130, 140 can be changed by changing the dimensions of the isolation structure 180. Increasing the size of the isolation structure 180, mainly the size of the side of the isolation structure 180 adjacent to the substrate 100, may increase the distance between the salicide layer 200 and the lightly doped regions 130, 140. The size of the isolation structure 180 may be determined according to actual circumstances.
In the semiconductor structure and the method for forming the same of the present invention, the salicide block layer 170 in the salicide formation region is etched, the salicide block layer 170 remains at the corners formed by the sidewalls 120 and the substrate 100 to form isolation structures 180, when the metal layer 190 is formed and heat treated subsequently, the metal element of the metal layer 190 may also diffuse laterally when longitudinal diffusion occurs, however, the existence of the isolation structure 180 prolongs the path of lateral diffusion, the metal element can diffuse only to the bottom of the isolation structure 180, and cannot further diffuse to the bottom of the sidewall 120, so that a space exists between the self-aligned metal silicide layer 200 and the lightly doped regions 130 and 140, thereby reducing on-resistance, improving the working efficiency of the device, and improving the reliability of the device.
In addition, only dry etching is performed on the salicide block layer 170, which saves wet etching steps, simplifies the process and reduces the production cost compared with the prior art.
Correspondingly, the invention also provides a semiconductor structure which is formed by adopting the forming method of the semiconductor structure.
Referring to fig. 10, the semiconductor structure includes:
the semiconductor device comprises a substrate 100, a gate structure 110 positioned on the substrate 100 and a side wall 120 covering the side wall of the gate structure 110, wherein lightly doped regions 130 and 140 are formed in the substrate 100 at the bottom of the side wall 120;
the isolation structure 180 is located at a corner formed by the sidewall 120 and the substrate 100, the isolation structure 180 is located at the bottom of the sidewall 120, and a longitudinal section of the isolation structure 180 is triangular;
a salicide layer 200 located within the surface of the substrate 100, wherein a gap exists between the salicide layer 200 and the lightly doped regions 130, 140.
The semiconductor structure further includes heavily doped regions 150, 160, the heavily doped regions 150, 160 are located in the substrate 100 at a side of the sidewall 120 away from the gate structure 110, the heavily doped region 150 is adjacent to the lightly doped region 130, and the heavily doped region 160 is adjacent to the lightly doped region 140. The heavily doped regions 150, 160 have a doping depth greater than the lightly doped regions 130, 140. The lightly doped regions 130, 140 serve as lightly doped regions LDD, and the heavily doped regions 150, 160 serve as source or drain doped regions, respectively.
The gate structure 110 includes a gate dielectric layer 110a and a polysilicon gate 110b stacked in sequence, the gate dielectric layer 110a is preferably made of silicon oxide, and the polysilicon gate 110b is made of polysilicon. The sidewall spacer 120 includes an oxide layer 120a and a nitride layer 120b, wherein the material of the oxide layer 120a is preferably silicon oxide, and the material of the nitride layer 120b is preferably silicon nitride.
A space exists between the salicide layer 200 in the substrate 100 and the lightly doped regions 130 and 140, and the salicide 200 forms ohmic contact with the heavily doped regions 150 and 160, so that on-resistance is reduced, the working efficiency of the device is improved, and the reliability of the device is improved.
In summary, in the semiconductor structure and the forming method thereof provided by the present invention, the salicide block layer in the salicide forming region is etched, the remaining portion of the salicide block layer at the corner formed by the sidewall and the substrate forms an isolation structure, and when a metal layer is formed subsequently and is subjected to a thermal treatment, a metal element of the metal layer is also subjected to a lateral diffusion when subjected to a longitudinal diffusion, but the existence of the isolation structure extends a path of the lateral diffusion, and the metal element can only be diffused to the bottom of the isolation structure and cannot be further diffused to the bottom of the sidewall, so that a gap exists between the salicide layer and the lightly doped region, thereby reducing on-resistance, improving device working efficiency, and improving device reliability.
In addition, the self-aligned metal silicide barrier layer is subjected to dry etching, and compared with the prior art, the dry etching method saves wet etching steps, simplifies the process and reduces the production cost.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for forming a semiconductor structure, comprising:
providing a substrate, wherein a grid structure and a side wall covering the side wall of the grid structure are formed on the substrate, and a lightly doped region is formed in the substrate at the bottom of the side wall;
forming a self-aligned metal silicide blocking layer, wherein the self-aligned metal silicide blocking layer covers the substrate, the grid structure and the side wall;
etching the self-aligned metal silicide barrier layer in the self-aligned metal silicide forming area, and forming an isolation structure at the rest part of the self-aligned metal silicide barrier layer at the corner formed by the side wall and the substrate, wherein the isolation structure is positioned at the bottom of the side wall, and the longitudinal section of the isolation structure is triangular;
forming a metal layer, wherein the metal layer covers the substrate, the gate structure, the side wall and the isolation structure; and the number of the first and second groups,
and carrying out heat treatment on the substrate to enable the metal layer to react with the substrate to form a self-aligned metal silicide layer, wherein the isolation structure enables a space to exist between the self-aligned metal silicide layer on the substrate and the lightly doped region.
2. The method of forming of claim 1, wherein the salicide barrier layer is a stack of silicon oxide and silicon nitride or a silicon-rich oxide layer.
3. The method of forming of claim 1, wherein the salicide block layer within a salicide formation region is dry etched to form the isolation structure.
4. The method of claim 3, wherein the dry etch comprises three stages, and the etch gas in the first stage comprises CH 3 F、CH 4 Ar, the air pressure is between 50mtorr and 200mtorr, the power is between 700W and 900W, and the etching time is between 1min and 2 min; in the second stage, etching is carried out by adopting an end point measurement mode, and etching gas contains CH 3 F、CH 4 Ar, the air pressure is between 50mtorr and 200mtorr, and the power is between 400W and 600W; the etching gas of the third stage contains CH 2 F 3 Or CH 3 F, the air pressure is between 30mtorr and 100mtorr, the power is between 200W and 400W, and the etching time is between 5s and 15 s.
5. The method of claim 1, wherein the salicide formation region is defined by a photoresist pattern formed using a photolithography process, the photoresist pattern covering the non-salicide formation region and exposing the salicide formation region.
6. The method of claim 5, wherein after forming the isolation structure and before forming the metal layer, further comprising: and removing the photoresist pattern.
7. The method according to claim 1, wherein a heavily doped region is further formed in the substrate at a side of the sidewall away from the gate structure, and the heavily doped region is adjacent to the lightly doped region.
8. The method of claim 7, wherein forming the gate structure, the sidewall spacers, the lightly doped region, and the heavily doped region on the substrate comprises:
forming a gate structure on the substrate;
performing first ion implantation on the substrate by taking the grid structure as a mask to form a temporary doped region;
forming a side wall on the side surface of the grid structure;
and performing secondary ion implantation on the substrate by taking the gate structure and the side wall as masks, forming a heavily doped region in the temporary doped region, wherein a region in the temporary doped region where the heavily doped region is not formed is used as the lightly doped region.
9. The method of claim 8, wherein a doping depth of the heavily doped region is greater than a doping depth of the lightly doped region, and the salicide layer is located within a surface of the heavily doped region with a spacing from the lightly doped region.
10. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, a grid structure positioned on the substrate and a side wall covering the side wall of the grid structure, wherein a lightly doped region is formed in the substrate at the bottom of the side wall;
the isolation structure is positioned at the corner formed by the side wall and the substrate, the isolation structure is positioned at the bottom of the side wall, and the longitudinal section of the isolation structure is triangular;
a salicide layer located within the substrate surface, there being a gap between the salicide layer and the lightly doped region.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116072532A (en) * | 2023-03-30 | 2023-05-05 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
| CN116314234A (en) * | 2023-05-19 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and CMOS image sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116072532A (en) * | 2023-03-30 | 2023-05-05 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
| CN116314234A (en) * | 2023-05-19 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and CMOS image sensor |
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