CN114784133B - 一种np层交替外延的碳化硅微沟槽中子探测器结构 - Google Patents
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Abstract
本发明公开了一种NP层交替外延的碳化硅微沟槽中子探测器结构。本发明结构采用多次外延法在N+衬底上依次交替制作N型层和P型层。首先在N+衬底上外延第一层N型层，之后在第一层N型层上外延第一层P型层，之后在第一层P型层外延层上外延第二层N型层，之后在第二层N型层外延层上外延第二层P型层，直到外延最后一层为N型层为止。如果外延的N型层一共有M层，则外延的P型层一共有M‑1层，总的外延层数为2M‑1层。每个N型层与每个P型层的厚度、掺杂浓度完全相同。本发明在外延层内部形成“锯齿形”的纵向电场分布，该电场分布更加均匀，使探测器在更低的衬底偏压下实现外延层的全耗尽，从而有效降低SiC微沟槽中子探测器的工作电压。
Description
技术领域
本发明涉及半导体核辐射探测技术，具体地说是一种NP层交替外延的碳化硅微沟槽中子探测器结构，一种适用于半导体核辐射探测的碳化硅微沟槽中子探测器结构。
背景技术
目前，世界范围应用最广的中子探测是3He气体探测器，但由于3He气体短缺导致的中子探测器供应严重不足，已影响到医学、能源、勘探等多个领域，亟需发展新型中子探测器。半导体型中子探测器具备多项适合高性能中子探测器开发的特性，在同尺寸下，已经可以超越3He探测器效率。但硅(Si)半导体器件的禁带宽度较窄，高温和辐照条件下将出现漏电流的急剧增大，进而导致器件性能退化甚至失效。因此，Si中子探测器的使用寿命远低于3He探测器，难以在反应堆、中子测井、航空航天等领域广泛应用。为了改善半导体中子探测器的抗辐照和耐高温性能，基于宽禁带材料的新型半导体中子探测器成为了科研人员关注的焦点。这其中，碳化硅(SiC)宽禁带半导体材料，由于具备位移阈能大、禁带宽度宽、饱和电子漂移速度高、击穿电场强度大、热导率高、熔点高、抗辐射性能好等优异性能，成为半导体中子探测器领域迅速崛起的新星。
目前，传统SiC平面型中子探测器的探测器效率较低，一般不超过5％。为了解决SiC平面型探测器探测效率不高的问题，SiC微沟槽中子探测器被提出，其最高探测效率可接近20％。通过在SiC外延层上刻蚀微沟槽结构，可以有效提高中子转换材料的填充量并增加与探测器收集区的接触面积，进而使探测效率显著提高。因此，为了获得较高的探测效率，就必须在厚的SiC外延层上刻蚀深的微沟槽，这将使得SiC外延层全耗尽变得非常困难。为了获得理想的电荷收集效率和响应时间，SiC外延层必须工作在全耗尽的状态，因此SiC衬底上需要施加较高的工作偏压，这将导致中子探测器后端电路供电非常困难。为此，本专利提出了一种NP层交替外延的碳化硅微沟槽中子探测器结构，可在更低的工作偏压下实现外延层的全耗尽。
发明内容
本发明基于现有的传统SiC微沟槽中子探测器，提出了一种NP层交替外延的碳化硅微沟槽中子探测器结构。
本发明解决去技术问题所采用的技术方案如下：
本发明结构采用多次外延方法在N+衬底上依次交替制作N型层和P型层。首先在N+衬底上外延第一层N型层，之后在第一层N型层上外延第一层P型层，之后在第一层P型层外延层上外延第二层N型层，之后在第二层N型层外延层上外延第二层P型层，以此类推，直到外延最后一层为N型层为止。可知，如果外延的N型层一共有M(M≥1)层，则外延的P型层一共有M-1层，总的外延层数为2M-1层。此外，为了实现理想的全耗尽状态，令每个N型层与每个P型层的厚度、掺杂浓度完全相同。
本发明的优点在于：
本发明提出NP层交替外延的碳化硅微沟槽中子探测器结构，该结构通过在衬底上依次外延交替的N型层和P型层，可在外延层内部形成“锯齿形”的纵向电场分布，该电场分布比传统单一外延层内形成的“三角形”纵向电场分布更加均匀。更加均匀的电场分布能使探测器在更低的衬底偏压下实现外延层的全耗尽，从而有效降低SiC微沟槽中子探测器的工作电压。
附图说明
图1是传统SiC微沟槽中子探测器结构示意图。
图2是基于本发明中子探测器结构示意图。
图3是图2所示结构的主要制造工艺流程示意图。
图4是图1和图2结构在200V工作偏压下外延层内纵向电场分布曲线图。
图5是图1和图2结构的电荷收集效率随不同工作偏压的变化曲线图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明进行具体阐述。
如图2所示，本发明提出了一种NP层交替外延的碳化硅微沟槽中子探测器结构，通过在N+衬底上依次外延形成N型层和P型层交替结构，使整个外延层的纵向电场均匀分布，在更低的衬底工作偏压下即可实现外延层的全耗尽，进而在满足100％电荷收集效率条件下有效降低探测器的工作电压。
下面采用模拟仿真方式仅对图1和图2所示两种结构进行对比讨论：
①传统SiC微沟槽中子探测器结构：外延层厚度为25μm，外延层掺杂浓度为2.0×1014cm-3；微沟槽宽度为15μm，微沟槽深度20μm；外延层表面P+掺杂区结深为0.5μm，掺杂浓度为1.0×1019cm-3。
②NP层交替外延的SiC微沟槽中子探测器结构：N型层层数M＝3，P型层层数为M-1＝2；每个N型层与每个P型层厚度相同均为5μm，则外延层总厚度为25μm，每个N型层与每个P型层掺杂浓度相同均为2.0×1014cm-3；微沟槽宽度为15μm，微沟槽深度20μm；外延层表面P+掺杂区结深为0.5μm，掺杂浓度为1.0×1019cm-3。
如图1-2所示，图2与图1不同之处在于图2结构采用N型层和P型层交替外延的方式形成探测器结构的外延层，其中图2结构的主要制造工艺流程如图3中(a)-(d)所示。
首先，采用多次外延的方法在N+衬底上制作交替的N型层和P型层作为结构的外延层，其中外延的第一层和最后一层需为N型层，每个N型层之间为P型层，每个N型层和每个P型层的厚度、掺杂浓度均相同(如图3中(a)所示)；其次，通过离子注入掺杂技术在最后一层N型层表面形成均匀的P+重掺杂分布(如图3中(b)所示)；再次，从外延层表面开始进行深沟槽刻蚀，沟槽深度和宽度可依据具体要求设定(如图3中(c)所示)；最后，在制作完成的深沟槽中进行中子转换材料填充(如图3中(d)所示)。
图4给出了衬底偏压为200V时，图1和图2结构沿外延层纵向的电场分布情况比较。图1结构整个外延层的纵向电场呈现典型的“三角形”分布，电场峰值出现在表面的P/N结位置，且随着外延层深度的增加电场急剧下降。根据图4所示仿真结论，衬底偏压200V时，图1结构在25μm厚的外延层范围内并没有完全耗尽。图2结构整个外延层的纵向电场呈现“锯齿形”分布，原因是交替的N型层和P型层可形成空间电荷区，从而使整个外延层的纵向电场均匀分布。根据图4所示仿真结论，衬底偏压200V时，图2结构在25μm厚的外延层范围可实现全耗尽。
图5给出了不同衬底工作偏压下，图1和图2结构的电荷收集效率。根据图5所示仿真结论，图2结构在不同工作偏压下的电荷收集效率均优于图1结构。图1结构在偏压150V时可达到100％的电荷收集效率，而图2结构在偏压75V时即达到了100％的电荷收集效率，从而使探测器的工作电压降低50％。
显然，本领域的技术人员可以对本发明进行各种改动和变形而不脱离本发明的精神和范围。应注意到的是，以上所述仅为本发明的具体实施例，并不限制本发明，凡在本发明的精神和原则之内，所做的调制和优化，皆应属本发明权利要求的涵盖范围。
Claims (3)
1.一种NP层交替外延的碳化硅微沟槽中子探测器结构,其特征在于采用多次外延方法在N+衬底上依次交替制作N型层和P型层，外延的第一层和最后一层需为N型层；
每个N型层与每个P型层的厚度、掺杂浓度完全相同；
通过离子注入掺杂技术在最后一层N型层表面形成均匀的P+重掺杂分布；再次从外延层表面开始进行深沟槽刻蚀，沟槽深度和宽度依据具体要求设定；最后，在制作完成的深沟槽中进行中子转换材料填充。
2.根据权利要求1所述的一种NP层交替外延的碳化硅微沟槽中子探测器结构,其特征在于首先在N+衬底上外延第一层N型层，之后在第一层N型层上外延第一层P型层，之后在第一层P型层外延层上外延第二层N型层，之后在第二层N型层外延层上外延第二层P型层，以此类推，直到外延最后一层为N型层为止。
3.根据权利要求2所述的一种NP层交替外延的碳化硅微沟槽中子探测器结构,其特征在于外延的N型层一共有M层，则外延的P型层一共有M-1层，总的外延层数为2M-1层。
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