CN114743867A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN114743867A
CN114743867A CN202210660372.1A CN202210660372A CN114743867A CN 114743867 A CN114743867 A CN 114743867A CN 202210660372 A CN202210660372 A CN 202210660372A CN 114743867 A CN114743867 A CN 114743867A
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layer
hard mask
patterned
opening
substrate
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刘哲儒
郑志成
林豫立
郭哲劭
陈冠中
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Hefei Xinjing Integrated Circuit Co Ltd
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Hefei Xinjing Integrated Circuit Co Ltd
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Priority to CN202210660372.1A priority Critical patent/CN114743867A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • High Energy & Nuclear Physics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure relates to a semiconductor structure and a method of fabricating the same. The semiconductor structure includes: a substrate; the patterned hard mask layer is positioned on the surface of the substrate and provided with a first opening, and the first opening is exposed out of the surface of the substrate; the patterned ion blocking layer is positioned on the surface, far away from the substrate, of the patterned hard mask layer and provided with a second opening, and the second opening is arranged corresponding to the first opening and exposes the first opening. The semiconductor structure can utilize the patterned hard mask layer to block ions penetrating through the patterned ion blocking layer under the condition of line width reduction by introducing the special patterned hard mask layer. Therefore, the semiconductor structure avoids the failure of the semiconductor device, and the performance of the semiconductor device is optimized.

Description

Semiconductor structure and preparation method thereof
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for fabricating the same.
Background
In the preparation process of the semiconductor, the ion implantation process is a doping technology of a semiconductor material, has the advantages of low-temperature doping, easy masking, accurate dose control and high uniformity, is used for multiple process steps such as source and drain doping, channel doping, lightly doped drain doping and the like, and ensures that the manufactured semiconductor device has the characteristics of high speed, low power consumption, good stability, high yield and the like.
Since the energy dose and other conditions required in different ion implantation processes are different, and the ion implantation is performed by doping in a designated area, other positions need to be masked by a patterned ion barrier layer. Patterned ion blocking layers with different thicknesses have different blocking capabilities for ion implantation, and too thin a thickness allows ions to easily penetrate through the blocking layer, while too thick a photoresist layer has difficulty in controlling critical dimensions during photolithography. With the trend of line width reduction, the thickness of the patterned ion blocking layer needs to be reduced to achieve higher resolution, however, when the thickness of the patterned ion blocking layer is reduced, ions easily penetrate the patterned ion blocking layer, so that the semiconductor device fails.
Therefore, how to ensure that ions can be prevented from penetrating the patterned ion blocking layer under the condition of line width reduction is a problem to be solved urgently.
Disclosure of Invention
Accordingly, there is a need for a semiconductor structure and a method for fabricating the same that can effectively ensure that ions can not penetrate through a patterned ion blocking layer under the condition of line width reduction, so as to optimize the performance of a semiconductor device.
An embodiment of the present application provides a semiconductor structure, including: a substrate; the patterned hard mask layer is positioned on the surface of the substrate and provided with a first opening, and the first opening is exposed out of the surface of the substrate; the patterned ion blocking layer is positioned on the surface, far away from the substrate, of the patterned hard mask layer and provided with a second opening, and the second opening is arranged corresponding to the first opening and exposes the first opening.
Optionally, the substrate comprises a silicon substrate.
Optionally, the substrate has an ion implantation region therein; the first opening and the second opening are exposed out of the ion implantation region.
Optionally, the patterned hard mask layer includes an oxide layer, a silicon nitride layer, or an oxynitride layer; the patterned ion blocking layer comprises a photoresist layer.
Optionally, the thickness of the patterned hard mask layer is 300-2000 angstroms.
The embodiment of the application also provides a preparation method of the semiconductor structure, which comprises the following steps: providing a substrate; forming a hard mask material layer on the surface of a substrate; forming an ion blocking material layer on the surface of the hard mask material layer far away from the substrate; patterning the ion barrier material layer and the hard mask material layer to form a patterned ion barrier layer and a patterned hard mask layer; the patterned hard mask layer is provided with a first opening, and the surface of the substrate is exposed by the first opening; the patterned ion barrier layer is provided with a second opening, and the second opening is arranged corresponding to the first opening and exposes the first opening; and carrying out ion implantation on the substrate based on the patterned ion blocking layer and the patterned hard mask layer so as to form an ion implantation area in the substrate.
Optionally, the ion blocking material layer comprises a photoresist layer, and the hard mask material layer comprises an oxide layer, a silicon nitride layer or an oxynitride layer; the method for forming the graphical ion barrier layer and the graphical hard mask layer comprises the following steps: exposing and developing the ion barrier material layer by adopting an exposure and development process to obtain a patterned ion barrier layer; and etching the hard mask material layer based on the patterned ion barrier layer as a mask to obtain the patterned hard mask layer.
Optionally, the hard mask material layer is etched by a dry etching process based on the patterned ion blocking layer as a mask to obtain the patterned hard mask layer.
Optionally, the patterned hard mask layer includes an oxide layer, a silicon nitride layer, or an oxynitride layer; the patterned ion blocking layer comprises a photoresist layer.
Optionally, the thickness of the patterned hard mask layer is 300-2000 angstroms.
In the semiconductor structure of the application, a special patterned hard mask layer is designed between the substrate and the ion blocking material layer, so that ions penetrating through the patterned ion blocking layer can be blocked by the patterned hard mask layer under the condition of reduced line width. That is, the semiconductor structure prevents ions from penetrating the patterned ion blocking layer under the condition of line width reduction by introducing a special patterned hard mask layer. Therefore, the semiconductor structure avoids the failure of the semiconductor device, and the performance of the semiconductor device is optimized.
In the preparation method of the semiconductor structure, a special patterned hard mask layer is designed between the substrate and the ion blocking material layer, so that ions penetrating through the patterned ion blocking layer can be blocked by the patterned hard mask layer under the condition of line width reduction. That is, the method for manufacturing a semiconductor structure prevents ions from penetrating through the patterned ion blocking layer by designing a special patterned hard mask layer under the condition of line width reduction, thereby preventing the semiconductor device from being invalid and optimizing the performance of the semiconductor device.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in an embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a structure obtained after a substrate is provided in a method for fabricating a semiconductor structure provided in an embodiment of the present application;
fig. 3 is a schematic cross-sectional view illustrating a structure obtained after forming a hard mask material layer on a surface of a substrate in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 4 is a schematic cross-sectional view illustrating a structure obtained after forming an ion blocking material layer on a surface of the hard mask material layer away from the substrate in the method for manufacturing a semiconductor structure provided in an embodiment of the present application;
fig. 5 is a schematic cross-sectional structure diagram of a structure obtained after patterning an ion blocking material layer and a hard mask material layer to form a patterned ion blocking layer and a patterned hard mask layer in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional structure diagram of a structure obtained after performing ion implantation on a substrate based on a patterned ion blocking layer and a patterned hard mask layer to form an ion implantation region in the substrate in a manufacturing method of a semiconductor structure provided in an embodiment of the present application;
fig. 7 is a flowchart illustrating a process of patterning the ion blocking material layer and the hard mask material layer to form a patterned ion blocking layer and a patterned hard mask layer in the method for fabricating a semiconductor structure according to an embodiment of the disclosure.
Description of reference numerals:
10-a substrate; 101-an ion implantation region;
20-a patterned hard mask layer; 200-a layer of hard mask material; 21-a first opening;
30-a patterned ion barrier layer; 300-a layer of ion blocking material; 31-second opening.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Embodiments of the present disclosure are presented in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
In the preparation process of the semiconductor, the ion implantation process is a doping technology of a semiconductor material, has the advantages of low-temperature doping, easy masking, accurate dose control and high uniformity, is used for multiple process steps such as source and drain doping, channel doping, lightly doped drain doping and the like, and ensures that the manufactured semiconductor device has the characteristics of high speed, low power consumption, good stability, high yield and the like.
Because the conditions such as energy dose required in different ion implantation processes are different, and the ion implantation is carried out by doping in a specified area, other positions need to be masked by a patterned ion barrier layer. Patterned ion blocking layers with different thicknesses have different blocking capabilities for ion implantation, and too thin a thickness allows ions to easily penetrate through the blocking layer, while too thick a photoresist layer has difficulty in controlling critical dimensions during photolithography. With the trend of line width reduction, it is required to reduce the thickness of the patterned ion blocking layer to achieve higher resolution, however, as the thickness of the patterned ion blocking layer is reduced, ions easily penetrate the patterned ion blocking layer, so that the semiconductor device fails.
Therefore, how to ensure that ions can be prevented from penetrating the patterned ion blocking layer under the condition of line width reduction is a problem to be solved urgently.
In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a semiconductor structure and a method for fabricating the same, which is capable of effectively preventing ions from penetrating through a patterned ion blocking layer under the condition of line width reduction, so as to optimize the performance of a semiconductor device.
Referring to fig. 1, an embodiment of the present application provides a method for fabricating a semiconductor structure, including the following steps:
s10: providing a substrate;
s20: forming a hard mask material layer on the surface of the substrate;
s30: forming an ion blocking material layer on the surface of the hard mask material layer far away from the substrate;
s40: patterning the ion blocking material layer and the hard mask material layer to form a patterned ion blocking layer and a patterned hard mask layer; the patterned hard mask layer is provided with a first opening, and the surface of the substrate is exposed by the first opening; the patterned ion barrier layer is provided with a second opening, and the second opening is arranged corresponding to the first opening and exposes the first opening;
s50: and carrying out ion implantation on the substrate based on the patterned ion blocking layer and the patterned hard mask layer so as to form an ion implantation area in the substrate.
According to the preparation method of the semiconductor structure, the special patterned hard mask layer is designed between the substrate and the ion blocking material layer, so that ions penetrating through the patterned ion blocking layer can be blocked by the patterned hard mask layer under the condition of width reduction. That is, due to the reduction of the line width, the thickness of the patterned ion blocking layer needs to be reduced to achieve higher resolution, however, the blocking capability of the patterned ion blocking layers with different thicknesses for ion implantation is different, the too thin thickness makes ions easily penetrate through the blocking layer, and the too thick photoresist layer has difficulty in controlling the critical dimension during photolithography. Therefore, the preparation method of the semiconductor structure prevents the semiconductor device from failing by designing a special patterned hard mask layer to prevent ions from penetrating through the patterned ion barrier layer under the condition of line width reduction, so that the performance of the semiconductor device is optimized.
The following describes in detail a method for manufacturing a light emitting unit provided in an embodiment of the present application with reference to fig. 2 to 7.
In step S10, please refer to step S10 in fig. 1 and fig. 2, the substrate 10 is provided.
In some examples, substrate 10 may include, but is not limited to, a silicon substrate. Of course, in other examples, the material of the substrate 10 may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 10 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate on which a dielectric layer or an epitaxial layer is grown, such as a substrate on which an oxide layer is formed, and the oxide layer may include, but is not limited to, a thermal oxidation process. The material of the substrate 10 is not limited in the embodiments of the present application. Substrate 10 is a semiconductor structure that provides mechanical support and electrical performance for the fabrication of semiconductor devices.
In an alternative embodiment, before performing step S20, a step of cleaning the substrate 10 may be further included, and by cleaning, impurities on the surface of the substrate 10 may be removed, so as to avoid affecting subsequent processes, and thus ensure the performance of the device.
Specifically, the substrate 10 may be cleaned with a cleaning solution, and the substrate 10 may be placed in a cleaning tank in which the cleaning solution is stored for cleaning; of course, the substrate 10 may be cleaned by spraying. The particular cleaning solution and cleaning process used to clean the substrate 10 are known to those skilled in the art and will not be described in detail herein.
It should be noted that a step of drying the substrate 10 is further included after the substrate 10 is cleaned, and a method of drying the substrate 10 is well known to those skilled in the art and will not be described herein again.
In step S20, referring to step S20 in fig. 1 and fig. 3, a hard mask material layer 200 is formed on the surface of the substrate 10.
Specifically, the hard mask material layer 200 may be formed on the surface of the substrate 10 by, but not limited to, a deposition process (e.g., a physical vapor deposition process, a chemical vapor deposition process, an atomic deposition process, or the like). The embodiment of the present application does not limit the method for forming the hard mask material layer 200 on the surface of the substrate 10.
In some examples, the hard mask material layer 200 includes, but is not limited to, an oxide layer, a silicon nitride layer, or an oxynitride layer.
In an alternative embodiment, taking the substrate as a silicon substrate as an example, the hard mask material layer 200 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like. Of course, in other examples, the hard mask material layer 200 may be other material layers. In this embodiment, the hard mask material layer 200 may include a silicon oxide layer.
In some examples, the thickness of the hard mask material layer 200 may be set according to actual needs, and in the present embodiment, the thickness of the hard mask material layer 200 may be, but is not limited to, 300 to 2000 angstroms. Specifically, the thickness of the hard mask material layer 300 may be 300 angstroms, 500 angstroms, 1000 angstroms, 1500 angstroms, 2000 angstroms, or the like.
In step S30, referring to step S30 in fig. 1 and fig. 4, the ion blocking material layer 300 is formed on the surface of the hard mask material layer 200 away from the substrate 10.
Specifically, the ion blocking material layer 300 may be formed on the surface of the hard mask material layer 200 away from the substrate 10 by, but not limited to, a spin coating process. The present embodiment does not limit the method for forming the ion blocking material layer 300 on the surface of the hard mask material layer 200 away from the substrate 10.
In some examples, the ion blocking material layer 300 comprises a photoresist layer. The material of the ion blocking material layer 300 may include, but is not limited to, any photosensitive material, such as a photoresist layer. Taking the ion blocking material layer 300 as a photoresist material layer as an example, the ion blocking material layer 300 may be formed by a spin coating process, but not limited to, in this embodiment, of course, in other examples, the ion blocking material layer 300 may also be formed by a deposition process, but not limited to, and the ion blocking material layer 300 covers the hard mask material layer 200.
Specifically, taking the ion blocking material layer 300 as an example of the photoresist material layer, if the ion blocking material layer 300 is formed by a spin coating process, after the photoresist material layer is formed by the spin coating process, the method further includes a step of performing a baking process on the ion blocking material layer 300 to harden the ion blocking material layer 300; the shape of the ion blocking material layer 300 can be better maintained through the baking process, and the film is harder and less prone to deformation, so that the ion blocking material layer has a better light blocking effect.
Specifically, the temperature of the baking process is generally 180 ℃ to 300 ℃, and specifically, the temperature of the baking process can be 180 ℃, 200 ℃, 250 ℃ or 300 ℃ and the like.
In step S40, referring to step S40 in fig. 1, fig. 4 and fig. 5, the ion-blocking material layer 300 and the hard mask material layer 200 are patterned to form the patterned ion-blocking layer 30 and the patterned hard mask layer 20.
Specifically, in step S40, referring to fig. 4, 5 and 7, the method for forming the patterned ion blocking layer 30 and the patterned hard mask layer 20 includes the following steps:
s401: exposing and developing the ion barrier material layer 300 by adopting an exposure and development process to obtain a patterned ion barrier layer 30;
s402: the hard mask material layer 200 is etched for a mask based on the patterned ion blocking layer 30 to obtain the patterned hard mask layer 20.
Here, the patterned hard mask layer 20 has a first opening 21, and the first opening 21 exposes the surface of the substrate 10; the patterned ion blocking layer 30 has a second opening 31, and the second opening 31 is disposed corresponding to the first opening 21 and exposes the first opening 21.
In some examples, the second opening 31 may define the shape and location of the patterned ion barrier 30; the hard mask material layer 200 is etched down based on the patterned ion blocking layer 30, so that the patterned hard mask layer 20 forming the first opening 21 can be provided.
Specifically, in step S401, the ion blocking material layer 300 is exposed based on a photomask; the exposed ion blocking material layer 300 is developed to obtain a patterned ion blocking layer 300.
In one example, the ion blocking material layer 300 may be a positive photoresist layer, and after development, the exposed regions of the ion blocking material layer 300 are removed to form the second openings 31.
In another example, the ion blocking material layer 300 may be a negative photoresist layer, and after development, the unexposed region of the ion blocking material layer 300 is removed to form the second opening 31.
Specifically, in step S402, the hard mask material layer 200 may be etched by, but not limited to, a dry etching process based on the patterned ion blocking layer 30 as a mask, so as to obtain the patterned hard mask layer 20. The embodiment of the present application does not limit the method for forming the patterned hard mask layer 20. The etching gas for dry etching may be selected according to the material of the hard mask material layer 200, and when the material of the hard mask material layer 200 is silicon oxide, the etching gas for dry etching may include, but is not limited to, carbon tetrafluoride (CF)4) Oxygen (O)2) And argon (Ar). The etching gas may be selected based on the particular material of the patterned hard mask layer 20.
In some examples, the cross-sectional area shape of the first opening 21 and the cross-sectional area shape of the second opening 31 may be set according to actual needs; the shape of the cross-sectional area of the first opening 21 and the shape of the cross-sectional area of the second opening 31 may include, but are not limited to, a circle, a rectangle, or the like. In the present embodiment, the cross-sectional shape of the first opening 21 and the cross-sectional shape of the second opening 31 are rectangular. The cross-sectional area shape of the first opening 21 and the cross-sectional area shape of the second opening 31 are not limited in the embodiments of the present application.
Optionally, the second opening 31 penetrates the patterned ion blocking layer 30 in the thickness direction. The first opening 21 may penetrate through the hard mask material layer 200 along the thickness direction, that is, the depth of the first opening 21 may be 300 to 2000 angstroms, specifically, the depth of the first opening 21 may be 300 angstroms, 500 angstroms, 1000 angstroms, 1500 angstroms, 2000 angstroms, or the like.
In step S50, referring to step S50 in fig. 1 and fig. 6, the substrate 10 is ion implanted based on the patterned ion blocking layer 30 and the patterned hard mask layer 20 to form an ion implantation region 101 in the substrate 10.
Specifically, the arrows in fig. 6 indicate the direction of ion implantation; the ions in the ion implantation process can be selected according to actual needs, and are not limited herein.
Specifically, the ion implantation region 101 may include, but is not limited to, at least one of a source region, a drain region, or a well region.
Based on the same inventive concept, please continue to refer to fig. 5 and fig. 6, the present application further provides a semiconductor structure, comprising: a substrate 10; the patterned hard mask layer 20 is positioned on the surface of the substrate 10, the patterned hard mask layer 20 is provided with a first opening 21, and the first opening 21 exposes the surface of the substrate 10; the patterned ion blocking layer 30 is located on the surface of the patterned hard mask layer 20 away from the substrate 10, the patterned ion blocking layer 30 has a second opening 31, and the second opening 31 is disposed corresponding to the first opening 21 and exposes the first opening 21.
In the semiconductor structure, the special patterned hard mask layer is designed between the substrate and the ion blocking material layer, so that ions penetrating through the patterned ion blocking layer can be blocked by the patterned hard mask layer under the condition of line width reduction. That is, due to the reduction of the line width, the thickness of the patterned ion blocking layer needs to be reduced to achieve higher resolution, however, the blocking capability of the patterned ion blocking layer with different thicknesses for ion implantation is different, the too thin thickness makes the ions easily penetrate through the blocking layer, and the too thick photoresist layer has difficulty in controlling the critical dimension during the photolithography. Therefore, the semiconductor structure prevents ions from penetrating through the patterned ion blocking layer under the condition of line width reduction by introducing a special patterned hard mask layer, so that the semiconductor structure avoids the failure of a semiconductor device and optimizes the performance of the semiconductor device.
In some examples, substrate 10 may include, but is not limited to, a silicon substrate. Of course, in other examples, the material of the substrate 10 may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 10 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate on which a dielectric layer or an epitaxial layer is grown; the dielectric layer may include, but is not limited to, an oxide layer. The material of the substrate 10 is not limited in the embodiments of the present application. Substrate 10 is a semiconductor structure that provides mechanical support and electrical performance for the fabrication of semiconductor devices.
In one example, the substrate 10 has an ion implantation region 101 therein, and the first opening 21 and the second opening 31 both expose the ion implantation region 101.
Specifically, the ion implantation region 101 may include, but is not limited to, at least one of a source region, a drain region, or a well region.
Optionally, the patterned hard mask layer 20 includes an oxide layer, a nitride layer, or an oxynitride layer.
In an alternative embodiment, taking the substrate 10 as a silicon substrate as an example, the patterned hard mask layer 20 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like. Of course, in other examples, the patterned hard mask layer 20 may be other material layers. In this embodiment, the patterned hard mask layer 20 may comprise a silicon oxide layer.
Optionally, the thickness of the hard mask material layer 200 may be set according to actual requirements, and in this embodiment, the thickness of the hard mask material layer 200 may be, but is not limited to, 300 to 2000 angstroms. Specifically, the thickness of the hard mask material layer 300 may be 300 angstroms, 500 angstroms, 1000 angstroms, 1500 angstroms, 2000 angstroms, or the like.
Optionally, the patterned ion blocking layer 30 may include a patterned photosensitive material layer, and in particular, in the present embodiment, the patterned ion blocking layer 30 may include a patterned photoresist layer.
In some examples, the second opening 31 may define the shape and location of the patterned ion barrier 30;
in some examples, the cross-sectional area shape of the first opening 21 and the cross-sectional area shape of the second opening 31 may be set according to actual needs; the shape of the cross-sectional area of the first opening 21 and the shape of the cross-sectional area of the second opening 31 may include, but are not limited to, a circle, a rectangle, or the like. In the present embodiment, the cross-sectional shape of the first opening 21 and the cross-sectional shape of the second opening 31 are rectangular. The cross-sectional area shape of the first opening 21 and the cross-sectional area shape of the second opening 31 are not limited in the embodiments of the present application.
Optionally, the second opening 31 penetrates the patterned ion blocking layer 30 in the thickness direction. The first opening 21 may penetrate through the patterned hard mask layer 20 along the thickness direction, that is, the depth of the first opening 21 may be 300 to 2000 angstroms, and specifically, the depth of the first opening 21 may be 300 angstroms, 500 angstroms, 1000 angstroms, 1500 angstroms, 2000 angstroms, or the like.
In the description of the present specification, various technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments are not described, but should be considered as being within the scope of the description, as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present disclosure, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that various changes and modifications can be made by one skilled in the art without departing from the spirit of the disclosure, and these changes and modifications are all within the scope of the disclosure. Therefore, the protection scope of the present disclosure should be subject to the appended claims.

Claims (10)

1. A semiconductor structure, comprising:
a substrate;
the patterned hard mask layer is positioned on the surface of the substrate and provided with a first opening, and the surface of the substrate is exposed out of the first opening;
the patterned ion blocking layer is positioned on the surface, far away from the substrate, of the patterned hard mask layer and provided with a second opening, and the second opening is arranged corresponding to the first opening and is exposed out of the first opening.
2. The semiconductor structure of claim 1, wherein the substrate comprises a silicon substrate.
3. The semiconductor structure of claim 1, wherein said substrate has an ion implanted region therein; the first opening and the second opening are exposed out of the ion implantation area.
4. The semiconductor structure of claim 1, wherein the patterned hard mask layer comprises an oxide layer, a silicon nitride layer, or an oxynitride layer; the patterned ion blocking layer comprises a photoresist layer.
5. The semiconductor structure of claim 1, wherein the patterned hard mask layer has a thickness of 300 to 2000 angstroms.
6. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a hard mask material layer on the surface of the substrate;
forming an ion blocking material layer on the surface of the hard mask material layer far away from the substrate;
patterning the ion blocking material layer and the hard mask material layer to form a patterned ion blocking layer and a patterned hard mask layer; the patterned hard mask layer is provided with a first opening, and the surface of the substrate is exposed out of the first opening; the patterned ion blocking layer is provided with a second opening, and the second opening is arranged corresponding to the first opening and exposes the first opening;
and performing ion implantation on the substrate based on the patterned ion blocking layer and the patterned hard mask layer so as to form an ion implantation area in the substrate.
7. The method of claim 6, wherein the ion blocking material layer comprises a photoresist layer, and the hard mask material layer comprises an oxide layer, a silicon nitride layer, or an oxynitride layer; the method for forming the patterned ion blocking layer and the patterned hard mask layer comprises the following steps:
exposing and developing the ion barrier material layer by adopting an exposure and development process to obtain the patterned ion barrier layer;
and etching the hard mask material layer based on the patterned ion barrier layer as a mask to obtain the patterned hard mask layer.
8. The method of claim 7, wherein the hard mask material layer is etched using a dry etch process based on the patterned ion blocking layer as a mask to obtain the patterned hard mask layer.
9. The method of claim 6, wherein the patterned hard mask layer comprises an oxide layer, a silicon nitride layer, or an oxynitride layer; the patterned ion blocking layer comprises a photoresist layer.
10. The method of claim 6, wherein the patterned hard mask layer has a thickness of 300 to 2000 angstroms.
CN202210660372.1A 2022-06-13 2022-06-13 Semiconductor structure and preparation method thereof Pending CN114743867A (en)

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US7341956B1 (en) * 2005-04-07 2008-03-11 Spansion Llc Disposable hard mask for forming bit lines
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