CN114388355A - Method for forming semiconductor device - Google Patents
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- CN114388355A CN114388355A CN202011117357.XA CN202011117357A CN114388355A CN 114388355 A CN114388355 A CN 114388355A CN 202011117357 A CN202011117357 A CN 202011117357A CN 114388355 A CN114388355 A CN 114388355A
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000005468 ion implantation Methods 0.000 claims abstract description 64
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 150000002500 ions Chemical class 0.000 claims description 67
- 229920002120 photoresistant polymer Polymers 0.000 claims description 43
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000010884 ion-beam technique Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052787 antimony Inorganic materials 0.000 description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention provides a method for forming a semiconductor device, which comprises the following steps: providing a substrate; forming a patterned first hard mask layer on the substrate; the patterned first hard mask layer is provided with a first opening; taking the patterned first hard mask layer as a first barrier layer, and carrying out first ion implantation on the substrate; filling the first opening to form a first mask layer; removing part of the first mask layer to expose the patterned first hard mask layer; removing the patterned first hard mask layer to form a patterned first mask layer; the first patterned mask layer is provided with a second opening; taking the patterned first mask layer as a second barrier layer, and performing secondary ion implantation on the substrate; and removing the patterned first mask layer. The invention realizes self-alignment and high-energy ion implantation with high depth-to-width ratio through one or more first hard mask layers.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor device.
Background
When a semiconductor device is manufactured, multiple times of ion implantation are needed to form doping units of different types of impurity ions which are distributed alternately. For example, N-type doped cells are isolated by P-type doped cells. On the one hand, when ion implantation is performed twice, there is a high demand for alignment accuracy, and on the other hand, when ion implantation with high energy having a high aspect ratio is performed, there is a high demand for the morphology of the barrier layer.
Disclosure of Invention
The invention provides a method for forming a semiconductor device, which aims to reduce the difficulty of an ion implantation alignment process, improve the precision of ion implantation and realize high-energy ion implantation with a high aspect ratio. The method comprises the following steps:
providing a substrate;
forming a patterned first hard mask layer on the substrate; the patterned first hard mask layer is provided with a first opening; the first hard mask layer comprises at least one hard mask layer;
taking the patterned first hard mask layer as a first barrier layer, and carrying out first ion implantation on the substrate;
filling the first opening to form a first mask layer;
removing part of the first mask layer to expose the patterned first hard mask layer;
removing the patterned first hard mask layer to form a patterned first mask layer; the first patterned mask layer is provided with a second opening;
taking the patterned first mask layer as a second barrier layer, and performing secondary ion implantation on the substrate;
and removing the patterned first mask layer.
In some embodiments, the forming a patterned first hard mask layer on the substrate comprises:
forming a first hard mask layer on the substrate;
forming a patterned first photoresist on the first hard mask layer;
removing a part of the first hard mask layer which is not covered by the patterned first photoresist by taking the patterned first photoresist as a third barrier layer;
removing the patterned first photoresist to form the patterned first hard mask layer; the first hard mask layer comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon or polycrystalline silicon.
In some embodiments, the patterned first hard mask layer is a stacked structure comprising: the graphical second hard mask layer and the graphical third hard mask layer;
the forming a patterned first hard mask layer on the substrate includes:
forming a patterned second hard mask layer on the substrate; the second patterned hard mask layer is provided with the first opening;
filling the first opening with a sacrificial layer;
removing part of the sacrificial layer to form a patterned sacrificial layer and expose the patterned second hard mask layer;
forming a third hard mask layer;
removing a part of the third hard mask layer above the patterned sacrificial layer to form the patterned third hard mask layer;
and removing the patterned sacrificial layer.
In some embodiments, the second and third hard mask layers comprise at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon, or polysilicon.
In some embodiments, the sacrificial layer is a hard mask or a photoresist;
the removing of the part of the sacrificial layer to form the patterned sacrificial layer and expose the patterned second hard mask layer comprises the following steps:
when the sacrificial layer is a hard mask, removing part of the sacrificial layer through CMP to form a patterned sacrificial layer and expose the patterned second hard mask layer; or
When the sacrificial layer is a light resistor, removing part of the light resistor through reverse etching to form a patterned sacrificial layer and expose the patterned second hard mask layer;
wherein the hard mask comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon, or polysilicon.
In some embodiments, the forming a patterned second hard mask layer on the substrate comprises:
forming a patterned second photoresist on the second hard mask layer;
and removing the part of the second hard mask layer which is not covered by the patterned second photoresist by taking the patterned second photoresist as a fourth barrier layer.
In some embodiments, said removing a portion of said third hard mask layer over said patterned sacrificial layer to form said patterned third hard mask layer comprises:
forming a third patterned photoresist on the third hard mask layer;
and removing part of the third hard mask layer which is not covered by the patterned third photoresist by taking the patterned third photoresist as a fifth barrier layer.
In some embodiments, the removing the patterned sacrificial layer comprises:
and removing the patterned sacrificial layer by dry etching and/or wet etching.
In some embodiments, the first mask layer is a hard mask or a photoresist;
the removing a portion of the first mask layer to expose the patterned first hard mask layer includes:
when the first mask layer is a hard mask, removing part of the first mask layer through CMP to expose the patterned first hard mask layer; or
When the first mask layer is a photoresist, removing part of the first mask layer through reverse etching to expose the patterned first hard mask layer;
the hard mask comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon or polycrystalline silicon.
In some embodiments, the ions of the first ion implantation are P-type and the ions of the second ion implantation are N-type; or, the ions of the first ion implantation are of an N type, and the ions of the second ion implantation are of a P type.
In some embodiments, performing a first ion implantation on the substrate comprises implanting ions into the substrate by a high energy ion beam;
performing a second ion implantation on the substrate includes implanting ions into the substrate with a high energy ion beam.
The invention also provides another method for forming the semiconductor device. The method comprises the following steps:
providing a substrate;
forming a patterned first hard mask layer on the substrate; the patterned first hard mask layer is provided with a first opening; the first hard mask layer comprises at least two hard mask layers;
and performing first high-energy ion implantation on the substrate by taking the patterned first hard mask layer as a first barrier layer.
In some embodiments, the method further comprises:
filling the first opening to form a first mask layer;
removing part of the first mask layer to expose the patterned first hard mask layer;
removing the patterned first hard mask layer to form a patterned first mask layer; the first patterned mask layer is provided with a second opening;
taking the patterned first mask layer as a second barrier layer, and performing second high-energy ion implantation on the substrate;
and removing the patterned first mask layer.
Compared with the prior art, the invention has the following beneficial effects:
(1) in the method for forming the semiconductor device, after the first ion implantation, the patterned first hard mask layer with the first opening is reserved, then the patterned first hard mask layer is filled through the first mask layer, the patterned first hard mask layer is exposed through Chemical Mechanical Planarization (CMP) or reverse etching of the first mask layer, then the patterned first hard mask layer between the first mask layers is removed, and then the second ion implantation is carried out, so that the self-alignment process is realized, the difficulty of the alignment process is reduced, and the process precision of the ion implantation is improved.
(2) The invention also realizes high-energy ion implantation with high depth-to-width ratio by using the multiple first hard mask layers.
Drawings
Fig. 1 is a flow chart illustrating a method of forming a semiconductor device according to one embodiment of the present invention;
fig. 2 through 9 are cross-sectional views of a structure during the formation of a semiconductor device according to an embodiment of the present invention;
fig. 10 is a flowchart of a method of forming a semiconductor device according to a second embodiment of the present invention;
FIGS. 11 through 23 are cross-sectional views of structures during formation of a semiconductor device according to embodiments of the present invention;
fig. 24 is a flowchart of a method for forming a semiconductor device according to a third embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the invention, from which it is possible for a person skilled in the art, without inventive effort, to apply the invention to other similar contexts. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
As used in this disclosure and in the claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are inclusive in the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
Flow charts are used in the present invention to illustrate the operations performed by a system according to embodiments of the present invention. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, the various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to the processes, or a certain step or several steps of operations may be removed from the processes.
It is to be expressly understood that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the invention. It should be understood that the drawings are not to scale.
Example one
Fig. 1 is a flow chart illustrating a method 100 of forming a semiconductor device in accordance with one embodiment of the present invention;
by describing a method 100 of forming a semiconductor device of the present invention in conjunction with fig. 2 through 9, the method 100 includes the steps of:
step 101: a substrate 201 is provided.
Step 102: forming a patterned first hard mask layer 203 on the substrate 201; wherein the patterned first hard mask layer 203 has a first opening 204; the first hard mask layer includes at least one hard mask layer.
Step 103: and performing first ion implantation on the substrate 201 by using the patterned first hard mask layer 203 as a first barrier layer.
Step 104: the first opening 204 is filled to form a first mask layer 206.
Step 105: a portion of the first mask layer 206 is removed to expose the patterned first hard mask layer 203.
Step 106: removing the patterned first hard mask layer 203 to form a patterned first mask layer 207; the patterned first mask layer 207 has a second opening 208.
Step 107: and performing second ion implantation on the substrate 201 by using the patterned first mask layer 207 as a second barrier layer.
Step 108: the patterned first mask layer 207 is removed.
As shown in fig. 2, in step 101, the substrate 201 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a gallium arsenide (GaAs) substrate, or the like. By way of illustration, the present invention employs a silicon substrate.
In some embodiments, as shown in fig. 2, a buffer layer 202 may be formed on the surface of the substrate 201 before step 102. The buffer layer 202 may include one or more layers of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon, or polysilicon.
As shown in fig. 3, in step 102, a patterned first hard mask layer 203 may be formed on the substrate 201.
The step of forming the patterned first hard mask layer 203 may specifically include the following steps:
forming a first hard mask layer on the substrate 201;
forming a patterned first photoresist on the first hard mask layer;
removing a part of the first hard mask layer which is not covered by the patterned first photoresist by taking the patterned first photoresist as a third barrier layer;
and removing the patterned first photoresist to form the patterned first hard mask layer 203. The first hard mask layer 203 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon, or polysilicon.
As shown in fig. 4, after the first ion implantation is performed on the substrate 201, the substrate 201 may form a doped ion region 205. The ions of the first ion implantation can be P-type or N-type. The N-type ions may include phosphorus (P) ions, arsenic (As) ions, antimony (Sb), and the like. The P-type ions may include boron (B) ions, gallium (Ga) ions, indium (In) ions, and the like.
As shown in fig. 5, the first opening 204 is filled, and the patterned first hard mask layer 203 is covered by a first mask layer 206. The first mask layer 206 may be a hard mask or a photoresist.
As shown in fig. 6, a portion of the first mask layer 206 may be removed by CMP or an etch back to expose the patterned first hard mask layer 203.
When the first mask layer 206 is a hard mask, a portion of the first mask layer 206 is removed by CMP to expose the patterned first hard mask layer 203. The hard mask includes at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon, or polysilicon.
When the first mask layer 206 is a photoresist, a portion of the first mask layer 206 is removed by an etch back to expose the patterned first hard mask layer 203.
As shown in fig. 7, the patterned first hard mask layer 203 is removed to form a patterned first mask layer 207; the patterned first mask layer 207 has a second opening 208. For example, when the first hard mask layer 203 is silicon nitride, it can be removed by hot phosphoric acid.
As shown in fig. 8, after performing the second ion implantation on the substrate 201, the substrate 201 may be formed to include a doped ion region 209. The ions of the second ion implantation can be of a P type or an N type. The N-type ions may include phosphorus (P) ions, arsenic (As) ions, antimony (Sb), and the like. The P-type ions may include boron (B) ions, gallium (Ga) ions, indium (In) ions, and the like.
In some embodiments, the ions of the first ion implantation are P-type and the ions of the second ion implantation are N-type; or, the ions of the first ion implantation are of an N type, and the ions of the second ion implantation are of a P type.
As shown in fig. 9, after the patterned first mask layer 207 is removed by dry etching and/or wet etching, doped regions doped with different ions, such as the doped region 205 and the doped region 209 in fig. 9, are formed in the substrate 201.
In the present embodiment, since the first opening 204 and the second opening 208 are nested with each other, it is achieved that the first ion implantation and the second ion implantation are self-aligned, thereby achieving different semiconductor devices with self-aligned ion implantation. In some embodiments, the semiconductor device may be a CMOS image sensor.
By way of example only, the patterned first hard mask layer 203 in the above embodiments is a layer. And the first hard mask layer 203 may include a multi-layer stack structure, which may be, for example, two, three, or more layers. Through the structure of the multiple hard mask layers, ion implantation with high aspect ratio can be realized.
Example two
Fig. 10 is a flow chart illustrating a method 300 of forming a semiconductor device in accordance with one embodiment of the present invention;
another method 300 of forming a semiconductor device of the present invention is described in conjunction with fig. 11-23. The first hard mask layer 203 depicted in fig. 11 through 23 includes a two-layer stack structure including a second hard mask layer 203a and a third hard mask layer 203 b.
The method 300 of forming a semiconductor device includes the steps of:
step 301: a substrate 201 is provided.
Step 302: forming a patterned second hard mask layer 203a on the substrate; the patterned second hard mask layer 203a has the first opening 204.
Step 303: the first opening 204 is filled with a sacrificial layer 401.
Step 304: and removing part of the sacrificial layer 401 to form a patterned sacrificial layer 402 and expose the patterned second hard mask layer 203 a.
Step 305: a third hard mask layer 203b-1 is formed.
Step 306: removing a portion of the third hard mask layer 203b-1 above the patterned sacrificial layer 402 to form a patterned third hard mask layer 203 b.
Step 307: the patterned sacrificial layer 402 is removed.
Step 308: the patterned second hard mask layer 203a and the patterned third hard mask layer 203b (or collectively referred to as the first hard mask layer 203) are used as a first blocking layer, and the substrate 201 is subjected to first ion implantation.
Step 309: the first opening 204 is filled to form a first mask layer 206.
Step 310: a portion of the first mask layer 206 is removed to expose the patterned third hard mask layer 203 b.
Step 311: removing the patterned second hard mask layer 203a and the patterned third hard mask layer 203b to form a patterned first mask layer 207; the patterned first mask layer 207 has a second opening 208.
Step 312: and performing second ion implantation on the substrate 201 by using the patterned first mask layer 207 as a second barrier layer.
Step 313: the patterned first mask layer 207 is removed.
Specifically, step 301 is similar to step 101 in the first embodiment, and the description of step 101 may be specifically referred to.
In some embodiments, as shown in fig. 2, a layer of silicon oxide 202 may be formed on the surface of the substrate 201 before step 302.
In step 302, as shown in fig. 11, a patterned second hard mask layer 203a may be formed, which may specifically include the following steps:
forming a patterned second photoresist on the second hard mask layer;
and removing part of the second hard mask layer which is not covered by the patterned second photoresist by taking the patterned second photoresist as a fourth barrier layer to form a patterned second hard mask layer 203 a.
The second hard mask layer 203a may include at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon, or polysilicon.
In step 303, the patterned second hard mask layer 203a is covered with a sacrificial layer 401, as shown in FIG. 12. The sacrificial layer may be a hard mask or a photoresist.
In step 304, as shown in fig. 13, a portion of the sacrificial layer 401 may be removed by CMP or an etch back to form a patterned sacrificial layer 402 and expose the patterned second hard mask layer 203 a.
When the sacrificial layer 401 is a hard mask, a part of the sacrificial layer 401 is removed by CMP to form a patterned sacrificial layer 402 and expose the patterned second hard mask layer 203 a. The hard mask comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon or polycrystalline silicon.
When the sacrificial layer 401 is a photoresist, a portion of the photoresist is removed by an etch back process to form a patterned sacrificial layer 402 and expose the patterned second hard mask layer 203 a.
In step 305, a complete third hard mask layer 203b-1 may be formed over the patterned second hard mask layer 203a, as shown in FIG. 14.
As shown in fig. 15, in step 306, removing a portion of the third hard mask layer 203b-1 above the patterned sacrificial layer 402 to form the patterned third hard mask layer 203b may be performed by:
forming a patterned third photoresist on the third hard mask layer 203 b-1;
and removing part of the third hard mask layer which is not covered by the patterned third photoresist by taking the patterned third photoresist as a fifth barrier layer.
As shown in fig. 16, in step 307, the patterned sacrificial layer 402 may be removed by dry etching and/or wet etching.
As shown in fig. 17, in step 308, the patterned second hard mask layer 203a and the patterned third hard mask layer 203b (or collectively referred to as the first hard mask layer 203) may be used as a first blocking layer to perform a first high-energy ion implantation on the substrate 201, so that the substrate 201 may form a doped ion region 205. The ions of the first ion implantation can be P-type or N-type. The N-type ions may include phosphorus (P) ions, arsenic (As) ions, antimony (Sb), and the like. The P-type ions may include boron (B) ions, gallium (Ga) ions, indium (In) ions, and the like. The energy range of the high-energy ions is not lower than 1000 keV.
The second hard mask layer 203a and the third hard mask layer 203b may be the same material or different materials. For example, the second hard mask layer 203a may be silicon nitride and the third hard mask layer 203b may be silicon oxide. High-energy ion implantation with high aspect ratio can be realized through the multiple hard mask layers.
As shown in fig. 18, in step 309, the first opening 204 is filled to form a first mask layer 206. The first mask layer 206 may be a hard mask or a photoresist.
As shown in fig. 19, in step 310, a portion of the first mask layer 206 may be removed to expose the patterned third hard mask layer 203 b. A portion of the first mask layer 206 may be removed by CMP or an etch back to expose the patterned first hard mask layer 203.
When the first mask layer 203 is a hard mask, a portion of the first mask layer 203 is removed by CMP to expose the patterned second hard mask layer 203a and the patterned third hard mask layer 203 b. The hard mask may include at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon, or polysilicon.
When the first mask layer 206 is a photoresist, a portion of the first mask layer 206 is removed by an etch back to expose the patterned first hard mask layer 203.
As shown in fig. 20, in step 311, the patterned second hard mask layer 203a and the third hard mask layer 203b may be removed to form a patterned first mask layer 207; the patterned first mask layer 207 has a second opening 208. For example, when the second hard mask layer 203a and the third hard mask layer 203b are silicon nitride, they may be removed by hot phosphoric acid.
As shown in fig. 21, in step 312, a second high-energy ion implantation may be performed on the substrate 201 by using the patterned first mask layer 207 as a second blocking layer, so that a doped ion region 209 may be formed in the substrate 201. The energy range of the high-energy ions is not lower than 1000 keV.
As shown in fig. 22, in step 313, after the patterned first mask layer 207 is removed, doped regions doped with different ions, such as the doped region 205 and the doped region 209 in fig. 22, are formed in the substrate 201.
It is noted that, in some embodiments, as shown in fig. 23, the patterned first mask 207 may include a hole region 207 a. Therefore, after the second high-energy ion implantation is performed on the substrate 201, the region of the hole region 207a corresponding to the substrate 201 is doped with the doping ions of the second high-energy ion implantation. So that a part of the doped ion region 205 formed by the first high-energy ion implantation forms a doped ion region 209. The ions of the second ion implantation can be of a P type or an N type. The N-type ions may include phosphorus (P) ions, arsenic (As) ions, antimony (Sb), and the like. The P-type ions may include boron (B) ions, gallium (Ga) ions, indium (In) ions, and the like. The embodiment is particularly important in the field of CMOS Image Sensors (CIS), and can realize the filling of a certain gap by controlling the process, and realize the injection of partial inversion type P-type ions in the middle of an N-well region of a photodiode, thereby reducing the depletion voltage of the well region, and being beneficial to obtaining the high full well capacity and avoiding the occurrence of charge retention (Lag).
In some embodiments, the ions of the first high energy ion implantation are of P-type, and the ions of the second high energy ion implantation are of N-type; or, the ions implanted by the first high-energy ions are of an N type, and the ions implanted by the second high-energy ions are of a P type.
In the present embodiment, since the first opening 204 and the second opening 208 are nested with each other, the first ion implantation and the second ion implantation are self-aligned, thereby achieving self-alignment of different semiconductor device processes.
It is noted that the first hard mask layer 203 may comprise a stack of multiple hard mask layers to form a barrier layer with a higher aspect ratio, resulting in a higher energy ion implantation with a narrower line width.
EXAMPLE III
Fig. 24 is a flow chart of a method 500 for forming a semiconductor device according to a third embodiment of the present invention. The method 500 includes the steps of:
step 501: a substrate is provided.
Step 502: forming a patterned first hard mask layer on the substrate; the patterned first hard mask layer is provided with a first opening; the first hard mask layer comprises at least two hard mask layers.
The at least two hard mask layers may include: including at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon, or polysilicon. The at least two hard mask layers may be the same material or different materials. For example, the first hard mask layer may be two silicon nitride hard mask layers. For another example, the first hard mask layer may be a stacked structure of a silicon nitride hard mask layer, a silicon oxide hard mask layer, and a silicon nitride hard mask layer.
Step 503: and performing first high-energy ion implantation on the substrate by taking the patterned first hard mask layer as a first barrier layer.
In some embodiments, the method 500 may further include the steps of:
step 504: and filling the first opening to form a first mask layer.
Step 505: and removing part of the first mask layer to expose the patterned first hard mask layer.
Step 506: removing the patterned first hard mask layer to form a patterned first mask layer; the patterned first mask layer has a second opening.
Step 507: and performing second high-energy ion implantation on the substrate by taking the patterned first mask layer as a second barrier layer.
Step 508: and removing the patterned first mask layer.
For the related description of step 501 to step 508, reference may be made to the related description in the first embodiment and the second embodiment, and details are not repeated here.
It should be noted that one or more steps in the above embodiments may be adjusted according to the actual process, for example, some steps may be combined or omitted.
It is to be noted that the drawings are in simplified form and are not to precise scale, which is for the purpose of facilitating and distinctly claiming some embodiments of the invention.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (13)
1. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a patterned first hard mask layer on the substrate; the patterned first hard mask layer is provided with a first opening; the first hard mask layer comprises at least one hard mask layer;
taking the patterned first hard mask layer as a first barrier layer, and carrying out first ion implantation on the substrate;
filling the first opening to form a first mask layer;
removing part of the first mask layer to expose the patterned first hard mask layer;
removing the patterned first hard mask layer to form a patterned first mask layer; the first patterned mask layer is provided with a second opening;
taking the patterned first mask layer as a second barrier layer, and performing secondary ion implantation on the substrate;
and removing the patterned first mask layer.
2. The method of claim 1, wherein forming the patterned first hard mask layer on the substrate comprises:
forming a first hard mask layer on the substrate;
forming a patterned first photoresist on the first hard mask layer;
removing a part of the first hard mask layer which is not covered by the patterned first photoresist by taking the patterned first photoresist as a third barrier layer;
removing the patterned first photoresist to form the patterned first hard mask layer; the first hard mask layer comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon or polycrystalline silicon.
3. The method of claim 1, wherein the patterned first hard mask layer is a stacked structure comprising: the graphical second hard mask layer and the graphical third hard mask layer;
the forming a patterned first hard mask layer on the substrate includes:
forming a patterned second hard mask layer on the substrate; the second patterned hard mask layer is provided with the first opening;
filling the first opening with a sacrificial layer;
removing part of the sacrificial layer to form a patterned sacrificial layer and expose the patterned second hard mask layer;
forming a third hard mask layer;
removing a part of the third hard mask layer above the patterned sacrificial layer to form the patterned third hard mask layer;
and removing the patterned sacrificial layer.
4. The method of claim 3, wherein the second hard mask layer and the third hard mask layer comprise at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon, or polysilicon.
5. The method of claim 3, wherein the sacrificial layer is a hard mask or a photoresist;
the removing of the part of the sacrificial layer to form the patterned sacrificial layer and expose the patterned second hard mask layer comprises the following steps:
when the sacrificial layer is a hard mask, removing part of the sacrificial layer through CMP to form a patterned sacrificial layer and expose the patterned second hard mask layer; or
When the sacrificial layer is a light resistor, removing part of the light resistor through reverse etching to form a patterned sacrificial layer and expose the patterned second hard mask layer;
wherein the hard mask comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon, or polysilicon.
6. The method of claim 3, wherein forming the patterned second hard mask layer on the substrate comprises:
forming a patterned second photoresist on the second hard mask layer;
and removing the part of the second hard mask layer which is not covered by the patterned second photoresist by taking the patterned second photoresist as a fourth barrier layer.
7. The method of claim 3, wherein the removing a portion of the third hard mask layer over the patterned sacrificial layer to form the patterned third hard mask layer comprises:
forming a third patterned photoresist on the third hard mask layer;
and removing part of the third hard mask layer which is not covered by the patterned third photoresist by taking the patterned third photoresist as a fifth barrier layer.
8. The method of claim 3, wherein the removing the patterned sacrificial layer comprises:
and removing the patterned sacrificial layer by dry etching and/or wet etching.
9. The method of claim 1, wherein the first mask layer is a hard mask or a photoresist;
the removing a portion of the first mask layer to expose the patterned first hard mask layer includes:
when the first mask layer is a hard mask, removing part of the first mask layer through CMP to expose the patterned first hard mask layer; or
When the first mask layer is a photoresist, removing part of the first mask layer through reverse etching to expose the patterned first hard mask layer;
the hard mask comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, amorphous silicon, amorphous carbon or polycrystalline silicon.
10. The method of claim 1, wherein the ions of the first ion implantation are P-type and the ions of the second ion implantation are N-type; or, the ions of the first ion implantation are of an N type, and the ions of the second ion implantation are of a P type.
11. The method according to any one of claims 1 to 10,
performing a first ion implantation on the substrate comprises implanting ions into the substrate by a high energy ion beam;
performing a second ion implantation on the substrate includes implanting ions into the substrate with a high energy ion beam.
12. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a patterned first hard mask layer on the substrate; the patterned first hard mask layer is provided with a first opening; the first hard mask layer comprises at least two hard mask layers;
and performing first high-energy ion implantation on the substrate by taking the patterned first hard mask layer as a first barrier layer.
13. The method of claim 12, further comprising:
filling the first opening to form a first mask layer;
removing part of the first mask layer to expose the patterned first hard mask layer;
removing the patterned first hard mask layer to form a patterned first mask layer; the first patterned mask layer is provided with a second opening;
taking the patterned first mask layer as a second barrier layer, and performing second high-energy ion implantation on the substrate;
and removing the patterned first mask layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114743867A (en) * | 2022-06-13 | 2022-07-12 | 合肥新晶集成电路有限公司 | Semiconductor structure and preparation method thereof |
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| CN114743867A (en) * | 2022-06-13 | 2022-07-12 | 合肥新晶集成电路有限公司 | Semiconductor structure and preparation method thereof |
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