CN114695123A - Preparation method of vertical GaN-based groove field effect transistor - Google Patents

Preparation method of vertical GaN-based groove field effect transistor Download PDF

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CN114695123A
CN114695123A CN202210268219.4A CN202210268219A CN114695123A CN 114695123 A CN114695123 A CN 114695123A CN 202210268219 A CN202210268219 A CN 202210268219A CN 114695123 A CN114695123 A CN 114695123A
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vertical
electrode
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刘新科
黄正
刘潇
林峰
吴钧烨
黄双武
黎晓华
贺威
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Shenzhen University
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Abstract

The embodiment of the invention discloses a preparation method of a vertical GaN-based groove field effect transistor, which comprises the following steps: growing a heteroepitaxial film on a double-side polished n-type highly doped self-supporting GaN substrate; etching the epitaxial film to form a vertical groove and a vertical mesa structure, and evaporating metal film in the vertical groove to form a p body layer electrode; p body layer in vertical trenchPreparation of Al on the surface of the device outside the electrode region2O3The film is used as a grid electrode and is pickled and passivated with Al2O3Evaporating a metal film on the surface of the film, and annealing to form an ohmic contact electrode; evaporating S on the surface of the p body layer electrode, depositing a passivation layer isolation table-board on the metal film of the ohmic contact electrode, and eliminating the peak electric field gathered at the edge of the PN junction around the isolation table-board by adopting a field plate termination method.

Description

Preparation method of vertical GaN-based groove field effect transistor
Technical Field
The embodiment of the invention relates to the technical field of electronics, in particular to a preparation method of a vertical GaN-based groove field effect transistor.
Background
Gallium nitride (GaN) is an important third-generation semiconductor material, and has excellent application prospect and market potential value in the fields of solid-state light sources, power electronics, microwave radio-frequency devices and the like due to the superior performances of large forbidden band width, high breakdown electric field, large heat conductivity, high electron saturation drift rate, strong radiation resistance and the like. AlGaN/GaN has high two-dimensional electron gas concentration and large electron saturation velocity, so that the AlGaN/GaN can work under the condition of large current, and meanwhile, the material has high critical breakdown electric field which is higher than that of a Si material by one amount, so that the device can bear higher voltage under the same size. In addition, the large forbidden band width determines that the high-temperature-resistant high-frequency-resistant high-power-resistant high-frequency-resistant high-power-resistant high-voltage power transformer can bear higher working temperature.
At present, with excellent material characteristics such as high electron mobility, large breakdown field strength and high thermal stability, wide-bandgap gallium nitride-based power devices have been considered as potential candidates for next-generation high-efficiency power electronics and compact power systems. GaN-based trench Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are more competitive in achieving intrinsically normally-off operation, with higher current density, than High Electron Mobility Transistors (HEMTs) and Current Aperture Vertical Electron Transistors (CAVETs). Lower on-resistance (Ron, sp) and lower current collapse. The development of lateral gallium nitride based field effect transistors is approximately saturated because the breakdown Voltage (VBR) is limited by the length of the lateral drift region, and although an increase in length may increase VBR, the size of the device increases, resulting in a reduction in the effective current density per unit chip area. In contrast, vertical gallium nitride based devices have been completely advanced under the same breakdown voltage and amperage rating, MOSFETs on stand-alone GaN substrates can greatly reduce the occurrence of high density trap states and mismatch when operated at non-linear high power due to the crystal lattice, compared to Si, sapphire, SiC and diamond.
In recent years, research on VBR, Ron, sp, device reliability, and the like of GaN vertical MOSFETs has been greatly advanced. In order to improve the VBR performance of the enhancement mode vertical GaN, a p-body is introduced into an N-GaN drift region, and a 'p-body/N drift' junction is formed through TCAD simulation. The vertical GaN interlevel-based trench MOSFET (OG-FET) had a threshold voltage (Vth) of 2.5V, Ron, sp of 0.98m Ω cm2, VBR of 700V, with the regenerated 10nm unintentionally doped GaN interlayer as the channel, and 50nm in situ Al2O3 as the gate dielectric. Vertical GaN trench MOSFETs with MBE regenerative UID-GaN channels were investigated, which avoided the need to reactivate the buried body p-GaN and guaranteed the same channel mobility benefits as MOCVD regeneration. Device characteristics of vertical GaN trench MOSFETs are improved using a Silvaco ATLAS two-dimensional simulation technique to obtain the best compromise between VBR and Ron, sp. By adopting a polarization-induced doping mode, unintentionally doped AlGaN is formed on the p-GaN with the thickness of about 100-300nm and the concentration of 0-7%, and then the p-AlGaN is grown on the UID AlGaN with the thickness of about 100-300nm and the concentration of 0-7%. Polarization-induced doping is to enable AlGaN to gradually change the composition of the AlGaN material, accumulate fixed polarization charges and induce the generation of three-dimensional holes/electrons through the difference of the polarizability of AlN and GaN, wherein AlN is larger than GaN, so that three-dimensional holes/electrons are generated. Pi doping has 1): immunity to hydrogen deactivation; 2): higher breakdown voltage for buried p-type layers; 3) a property of being able to activate the Mg acceptor completely and being not affected by temperature. Normal off operation in vertical GaN-based trench gate MOSFETs (GaNtg-MOSFETs) high power applications is demonstrated on a 4 inch freestanding GaN substrate. The transmission, output and breakdown voltage characteristic curves obtained through TCAD simulation are well matched with experimental data.
Although existing products have been developed with a great deal of reverse breakdown capability, the problem of heat dissipation in the device is still not sufficiently addressed; meanwhile, when p-GaN is doped, higher activation energy is brought by Mg doping, so that the activation performance of the device is poor.
Disclosure of Invention
The embodiment of the invention provides a preparation method of a vertical GaN-based groove field effect transistor, which comprises the following steps:
growing a heteroepitaxial film on the double-side polished n-type high-doping self-supporting GaN substrate;
etching the epitaxial film to form a vertical groove and a vertical mesa structure, and evaporating metal film in the vertical groove to form a p body layer electrode;
al preparation on device surface outside p body layer electrode area in vertical trench2O3The film is used as a grid electrode and is pickled and passivated with Al2O3Evaporating a metal film on the surface of the film, and annealing to form an ohmic contact electrode;
evaporating S on the surface of the p body layer electrode, depositing a passivation layer isolation table-board on the metal film of the ohmic contact electrode, and eliminating the peak electric field gathered at the edge of the PN junction around the isolation table-board by adopting a field plate termination method.
In one embodiment of the present invention, when S is deposited on the surface of the p-body layer electrode, the source electrode (Ti/Al,15nm/35nm) and the drain electrode (Al.50nm) are at N2Annealing at 550 ℃ for 5 minutes in the atmosphere to form good ohmic contact; wherein the gate electrode and the p-body layer electrode are respectively composed of Ti (10nm)/Au (40nm) and Pd.
Further, growing a heteroepitaxial thin film on a double-side polished n-type highly doped self-supporting GaN substrate, comprising:
the thickness of the growth on the n-type GaN substrate is 10-15 μm, and the concentration of the light doping carrier is about 5.0 multiplied by 1015cm-3～9.0×1015cm-3The n-type light Si-doped n-type GaN is used as a drift layer;
growing p-type AlGaN with the thickness of 200-300 nm on an n-type GaN substrate and formed by heavy doping, wherein the content of Al of the p-type AlGaN of a buried layer is in a linear gradient from 7% to 0%, and the Al is stored as a channel region;
growing heavily doped n + type GaN with the thickness of 0.1-0.3 mu m on the p-type AlGaN to be used as a source contact layer, wherein the doping density is 2 multiplied by 1018cm-3To 5X 1018cm-3。
Further, etching is performed on the epitaxial film, including: by Cl2The flow is 15-50sccm, and the power is 50-100W to carry out ion etching on the epitaxial film.
Further, etching is performed on the epitaxial film, including: by Cl2The flow rate is 40-60 sccm, and the power is 10-30W to perform the inductively coupled plasma on the epitaxial thin film to etch the epitaxial thin film.
Furthermore, the width of the vertical trench is 0.1 to 0.3 μm.
Furthermore, the height of the vertical table-board is 1.5-2 μm.
Further, when the grid electrode is prepared, an electron beam evaporation process is adopted to evaporate the alloy with the metal structure of Ni/Au.
Further, the passivation isolation mesa is SiO2Film or SiN4A film.
Further, the thickness of the passivation isolation table top is 200-600 nm.
Further, the gate and p bulk layer electrodes were Ti/Au and Pd, respectively.
The embodiment of the invention has the beneficial effects that: the polarization-induced doping growth p + AlGaN is used for replacing p + GaN in the TG-MOS device with the stepped doping channel structure to serve as a p body layer, the influence of H ions caused by Mg doping is avoided, the on-resistance of the device can be effectively reduced, the electric field at the edge of a p-n junction around the periphery of an isolation table top is effectively reduced, the device has the characteristic of realizing higher breakdown, and the device has good heat conductivity.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a plan view of a GaN-based device with vertical mesas and vertical trenches etched in an epitaxial growth layer of a TG-MOS device by ICP according to an embodiment of the present invention.
FIG. 2 is a plan view of a GaN-based device having a gate and an ALD deposited gate dielectric in accordance with an embodiment of the invention.
Fig. 3 is a plan view of a GaN-based device with source, drain, gate and passivation layers according to an embodiment of the present invention.
Fig. 4 is a plan view of a TG-MOS device structure with a group-doped channel after polarization-induced doping to replace p + -GaN according to an embodiment of the present invention.
Fig. 5 is an electrical property test chart provided by an embodiment of the invention.
Fig. 6 is an electron distribution performance test chart according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.
Fig. 1 to fig. 4 are schematic diagrams of step flow structures of an embodiment of the present invention, which specifically include the following steps:
step one, growing n-GaN/p-AlGaN/n + GaN on a double-side polished n-type highly-doped self-supporting GaN substrate, namely growing a heteroepitaxial film by using a chemical vapor deposition (MOCVD) method.
The method specifically comprises the following steps:
1) preparing a dislocation density of 1 × 106-2×106cm-2A range of commercially available n + -type GaN substrates.
2) Growth of 12 μm lightly doped carrier concentration, preferably 8.0 × 10, on n-type + -GaN substrates using Metal Organic Chemical Vapor Deposition (MOCVD)15cm-3N-type light S ofi-doped n-GaN as a drift layer.
3) P + -AlGaN which is preferably formed by heavy doping at 250nm is grown on an n-GaN substrate by Metal Organic Chemical Vapor Deposition (MOCVD), and the Al content of the p-type AlGaN of the buried layer is linearly graded from 7% to 0% and stored as a channel region. On the basis of the above, heavily doped n + GaN with the thickness of 0.2 μm is preferably grown as the source contact layer, and the doping density is preferably 3 × 1018cm-3。
Step two, forming a table top and etching a channel: cl was used at a flow rate of 50sccm and a power of 20W2Inductively coupled plasma etching (ICP) was performed to form vertical trenches of preferably 0.2 μm width and vertical mesas of preferably 1.7 μm height.
Step three, preparing Al with the thickness of 16nm by utilizing an atomic layer deposition method (ALD)2O3The thin film serves as a gate dielectric. The epitaxial wafer is first subjected to a simple acid wash and then to a (NH) wash4)2And S, passivating, and depositing a film in an ALD vacuum coating instrument.
Step four, the source electrode and the drain electrode are positioned at N2Annealing at 550 deg.c for 5 min to form excellent ohmic contact electrode.
Step five, depositing SiO with the thickness of 200-1000nm, preferably 400nm by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method2The film acts as a passivation isolation mesa.
And sixthly, eliminating the peak electric field gathered at the edge of the PN junction around the isolated platform by adopting a field plate termination method, and connecting the aluminum-based field plate with the source electrode.
As shown in fig. 5, the performance test of the prepared device resulted in the following test results:
1. transmission I-V characteristic (ID-VG) at VDS 0.5V
2. Output I-V characteristics (ID-VD) when VGS is 0V, 5V, 10V, 15V, and 20V
3. The off-state I-V characteristics of the GaN TG-MOSFET were measured at VG ═ 0V.
And (4) conclusion: the low density of interface states is beneficial for reducing Ron, sp and switching losses, and the transmission, output and breakdown characteristics curve GaN TG-MOSFET, which defines the interface state in the simulation as 1011cm-2 · eV-1, was tested by experiment (Exp) and simulation (Sim), respectively, as shown in fig. 5. Fig. 5(a) shows the ID-VG characteristics when VDS is 0.5V, and the Vth value is determined from the measured ID VG characteristics using several extraction methods. Fig. 5(b) shows output I-V characteristics when VGS is 0V, 5V, 10V, 15V, and 20V, respectively. When VDS is 0.5V and VGS is 20V, Ron, sp value of the linear region is 1.93m Ω · cm 2. Fig. 5(c) shows that the I-V characteristic in the off state is measured when VGS is 0V. The corresponding obtained merit values (FOM) were 0.88GW/cm2 and 1.68GW/cm2, respectively, obtained by experiments and simulations, respectively.
As shown in fig. 6, the performance test of the prepared device resulted in the following test results:
1. electron concentration distribution when VGS is 0V and VDS is 0.5V
2. Energy band of VGS 20V and VDS 0.5V (on-state)
3. Off state and (d) on state profile
And (4) conclusion: first, Vth (IDS ═ 1 μ a/mm) is normally 3.15V. Therefore, the p-GaN channel region has no electron distribution at VGS < Vth, as shown in fig. 6 (a).
Second, current cannot be conducted between the source and drain because the channel has not yet formed a conductive path. In fig. 6(b), only VGS > Vth, and thus a drain-source current is generated. The electrons easily jump to CB and produce a conduction current. Output I V characteristics when VGS is 0V, 5V, 10V, 15V and 20V are shown as fig. 6(b), respectively. When VDS is 0.5V and VGS is 20V, Ron, sp value of the linear region is 1.93m Ω · cm 2.
Again, the energy band distributions along the a-line and the B-line in the off-and on-states are shown in fig. 6(c) and 6(d), respectively. From the off-state to the on-state, the conduction band energy decreases significantly until it approaches the quasi-fermi level (QFL).
According to the invention, a vertical trench gate MOS transistor is prepared on a large-size independent GaN wafer by improving the preparation method of a buried p body layer (namely p-GaN) in a PI doping mode, so that the embarrassment that the device is difficult to activate due to high activation energy brought by Mg-H can be greatly reduced, the reverse breakdown voltage is enhanced, the device can be completely activated and is not influenced by temperature, and the vertical trench gate MOS transistor has better temperature stability. Polarization-induced doping is utilized in a TG-MOS device with a stepped doping channel structure, p + AlGaN is grown by MOCVD, p + GaN is replaced by the MOCVD device to serve as a p body layer, the influence of H ions caused by Mg doping is avoided, the on-resistance of the device can be effectively reduced, the electric field at the edge of a p-n junction around the periphery of an isolation table top is effectively reduced, the device has the characteristic of realizing higher breakdown, and has good heat conductivity.
The foregoing is only a partial embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and embellishments can be made without departing from the principle of the present invention, and these should also be construed as the scope of the present invention.

Claims (10)

1. A preparation method of a vertical GaN-based groove field effect transistor is characterized by comprising the following steps:
growing a heteroepitaxial film on the double-side polished n-type high-doping self-supporting GaN substrate;
etching the epitaxial film to form a vertical groove and a vertical table structure, and evaporating metal film in the vertical groove to form a p body layer electrode;
al preparation on device surface outside p body layer electrode area in vertical trench2O3The film is used as a grid electrode and is subjected to acid cleaning and passivation on Al2O3Evaporating a metal film on the surface of the film, and annealing to form an ohmic contact electrode;
evaporating S on the surface of the p body layer electrode, depositing a passivation layer isolation table-board on the metal film of the ohmic contact electrode, and eliminating the peak electric field gathered at the edge of the PN junction around the isolation table-board by adopting a field plate termination method.
2. The method of claim 1, wherein growing a heteroepitaxial thin film on a double-side polished n-type highly doped self-supporting GaN substrate comprises:
the thickness of the growth on the n-type GaN substrate is 10-15 μm, and the concentration of the light doping carrier is about 5.0 multiplied by 1015cm-3～9.0×1015cm-3The n-type light Si-doped n-type GaN is used as a drift layer;
growing p-type AlGaN with the thickness of 200-300 nm on an n-type GaN substrate and formed by heavy doping, wherein the content of Al of the p-type AlGaN of a buried layer is in a linear gradient from 7% to 0%, and the Al is stored as a channel region;
growing heavily doped n + type GaN with the thickness of 0.1-0.3 mu m on the p-type AlGaN to be used as a source contact layer, wherein the doping density is 2 multiplied by 1018cm-3To 5X 1018cm-3。
3. The method of claim 1, wherein etching on the epitaxial film comprises: by Cl2The epitaxial film is subjected to ion etching with the flow rate of 15-50sccm and the power of 50-100W.
4. The method of claim 1, wherein etching is performed on the epitaxial film, comprising: by Cl2The flow rate is 40-60 sccm, and the power is 10-30W to perform the inductively coupled plasma on the epitaxial thin film to etch the epitaxial thin film.
5. The method of claim 1, wherein the vertical trench has a width of 0.1 to 0.3 μm.
6. The method of claim 1 or 5, wherein the height of the vertical mesa is 1.5 to 2 μm.
7. The method of claim 1, wherein the alloy having a metal structure of Ni/Au is evaporated by an electron beam evaporation process when the gate electrode is manufactured.
8. The method of claim 1, wherein the passivated isolation mesa is SiO2Film or SiN4A film.
9. The method according to claim 1 or 8, wherein the thickness of the passivated isolation mesa is 200 to 600 nm.
10. The method of claim 1, wherein the gate and p-body layer electrodes are Ti/Au and Pd, respectively.
CN202210268219.4A 2022-03-17 2022-03-17 Preparation method of vertical GaN-based groove field effect transistor Pending CN114695123A (en)

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