CN114616662A - 使用超细paa改性全加成法制造精细间距走线的方法 - Google Patents
使用超细paa改性全加成法制造精细间距走线的方法 Download PDFInfo
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- CN114616662A CN114616662A CN202080057766.7A CN202080057766A CN114616662A CN 114616662 A CN114616662 A CN 114616662A CN 202080057766 A CN202080057766 A CN 202080057766A CN 114616662 A CN114616662 A CN 114616662A
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- Prior art keywords
- layer
- copper
- paa
- dielectric substrate
- traces
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Abstract
一种适于扩散接合的衬底的制造方法,其提供柔性介电衬底,并对于介电衬底进行碱性改性,以在介电衬底的表面上形成聚酰胺酸(PAA)固定层,再将Ni‑P种晶层以无电镀方式镀在PAA层上,将铜走线镀在Ni‑P种晶层上的光阻图案内,将表面抛光层以电解方式镀在铜走线上,再将光阻图案和未被铜走线覆盖的Ni‑P种晶层予以移除,以完成适于扩散接合的衬底。
Description
本申请案是2018年2月2日提交的美国专利申请案序号第15/887,346号的部分连续申请案,其转让给共同受让人,并且其所有内容在此以参照的方式引入本文中。
技术领域
本申请案是有关于具有精细铜走线的柔性衬底的制造方法,更特别地,是有关于使用具有精细铜走线的柔性衬底制造具有固态扩散接合的半导体封装的方法。
背景技术
对于更小体积和低成本电子产品的需求的提升,促进了衬底技术中微细线路和高产量制程的新发展。为了因应未来更高功能、更低功耗和小型化需求,薄膜覆晶(COF)封装是一项重要技术;特别于高解析度以及增加输入/输出端口数量的触控集成电路(IC)以及显示驱动集成电路整合模块(TDDI)所需求的极细间距的COF封装。一般来说,柔性电路是利用减成法来制作,其铜走线图案是通过蚀刻来形成,然而,此减成法于侧壁的几何控制上有个固有的问题,于现有半加成制程(SAP)中,通常使用具有Ni/Cr的2-3μm厚的铜来作为种晶层,当去除此些层时,因湿蚀刻制程具有等向性,而无法于同时蚀刻铜以及种晶层时进行有效控制,因而产生“底切”的主要制程限制,这反过来给细线以及精准图案带来了诸多挑战,并导致了弱化精细走线的失败。
覆晶组件于扩散接合过程中,有许多独立的因素需要考量,可形变层必须提供具有良好走线完整性的必要的电性,其必须承受接触的压力,因此走线需具有足够的顶面宽度,如此可达成在结合区上具有适当蠕动变形并消除空隙的完整接触界面。随着结合间距的降低,半加成法与减成法用来在合理产量下维持顶面对底面宽度(T/B)比至接近1时具有限制。
另一个方法为全加成法(FAP),其中铜图案通过无电镀方法来形成,于电化学沉积前,无电镀Ni-P的薄种晶层形成于具有碱性改性表面的聚酰亚胺(PI)上,具有酰亚胺环的PI可轻易的被进入的亲核氢氧根离子开启,而形成聚酰胺酸盐(PAA)。由于聚酰胺酸上的羧酸基是离子交换基,当将其在钯(Pd(II))离子水溶液中进行处理时,其可被还原并使钯催化剂沉积,一旦催化剂沉积,则能继续进行无电镀;然而,如此的方法在热处理后会降低剥离强度,因此无法确实于实际上应用。
美国专利第9,089,062号(Janssen)以及第9,324,733号(Rogers等人)公开了有关聚酰胺酸以及碱性电镀浴的方法。
发明内容
本发明的主要目的是提供一种用于柔性薄膜覆晶(COF)封装中在柔性衬底上制造多个精细走线的方法。
本发明的另一目的是提供一种用于柔性薄膜覆晶(COF)封装中在柔性衬底上镀上精细且坚固的铜走线的全加成法。
本发明的再一目的是提供一种用于柔性薄膜覆晶(COF)封装中在柔性衬底上镀上精细且坚固的铜走线的全加成法,其在介电材料/Ni-P界面上使用无电镀Ni-P和可靠的纳米尺寸聚酰胺酸(PAA)固定层。
根据本发明的目的,提供了一种适用于各种互连方法的衬底的制造方法,这些互连方法包括有热压接合、引线接合、黏接和焊接。首先,提供柔性介电衬底,对于介电衬底进行碱性改性,以在介电衬底的表面上形成聚酰胺酸(PAA)固定层,再以无电镀方式在PAA层上镀上Ni-P种晶层,将铜走线镀在Ni-P种晶层上的光阻图案内,以电解方式在铜走线上镀上表面抛光层,然后,将光阻图案和未被铜走线覆盖的Ni-P种晶层予以移除,以完成适于扩散接合的衬底。
同样根据本发明的目的,提供了一种适用于各种互连方法的2ML(金属层)衬底的制造方法,这些互连方法包括有热压接合、引线接合、黏接和焊接。首先,提供柔性电介衬底,以激光钻孔方式形成至少一穿孔完全通过介电衬底,再对于介电衬底进行碱性改性,以在介电衬底的顶面和底面上形成聚酰胺酸(PAA)固定层,以无电镀方式在PAA层的顶部和底部上镀上Ni-P种晶层,将光阻(干式光阻/湿式光阻)予以施加、曝光和显影,以形成电路图案,再将铜走线镀在Ni-P种晶层的顶部和底部上的光阻图案内并贯穿前述至少一穿孔,然后,以电解方式将表面抛光层镀在铜走线的至少一侧上,再将光阻图案和未被铜走线覆盖的Ni-P种晶层予以移除,以完成适于扩散接合的衬底。
同样根据本发明的目的,提供了一种适用于各种互连方法的多层衬底的制造方法,这些互连方法包括有热压接合、引线接合、黏接和焊接。首先,提供柔性电介衬底,以激光钻孔方式形成至少一穿孔完全通过介电衬底,再对于介电衬底进行碱性改性,以在介电衬底的顶面和底面上形成聚酰胺酸(PAA)固定层,以无电镀方式在PAA层的顶部和底部上镀上Ni-P种晶层,将光阻(干式光阻/湿式光阻)进行施加、曝光和显影,以形成电路图案,再将铜走线镀在Ni-P种晶层的顶部和底部上的光阻图案内并贯穿前述至少一穿孔,再将光阻图案和未被铜走线覆盖的Ni-P种晶层予以移除,然后,将接合膜层压在第一铜走线的顶面和底面上,再将介电层(PI)层压在接合膜的顶部和底部,以激光钻孔方式形成至少一第二穿孔完全通过介电衬底和接合膜至接触在衬底的顶部和底部上的第一铜走线,然后,对于介电层进行碱性改性,以将第二聚酰胺酸(PAA)固定层形成在介电层的顶面和底面上以及在前述至少一第二穿孔内,再以无电镀方式将第二Ni-P种晶层镀在第二PAA层的顶部和底部上,并将第二光阻图案形成在第二Ni-P种晶层的顶部和底部,将第二铜走线镀在第二光阻图案内并贯穿前述至少一第二穿孔,再将表面抛光层镀在第二铜走线上,将第二光阻图案和未被第二铜走线覆盖的第二Ni-P种晶层予以移除,以完成柔性衬底。
同样根据本发明的目的,还提供了一种2ML(金属层)的薄膜覆晶(COF)。此COF包括柔性介电衬底、至少一第一铜走线及至少一晶粒,此柔性介电衬底在其顶面上具有第一聚酰胺酸(PAA)固定层,此至少一第一铜走线位于第一PAA层上的第一Ni-P种晶层上,且在此至少一第一铜走线的顶面上具有表面抛光层,此至少一晶粒通过与前述至少一第一铜走线的扩散接合被设置在介电衬底上。
同样根据本发明的目的,提供了多层的薄膜覆晶(COF)。此COF包括柔性介电衬底、至少一第一铜走线、至少一第二铜走线及至少一晶粒,此柔性介电衬底在其顶表面上具有第一聚酰胺酸(PAA)固定层,在其底面上具有第二PAA层,此至少一第一铜走线位于第一PAA层上的第一Ni-P种晶层上,此至少一第二铜走线位于第二PAA层上的第二Ni-P种晶层上,其中第一和第二铜走线通过穿过介电衬底的穿孔互连,且至少一第一铜走线的顶面上具有表面抛光层,此至少一晶粒通过与前述至少一第一铜走线的扩散接合被设置在介电衬底上。
附图说明
本发明附图构成说明书的一部分,其说明如下:
图1为本发明第一较佳实施例的第一替代态样中步骤的流程图。
图2A-2G为本发明第一较佳实施例的第一替代态样中各步骤的斜视图。
图2H-2J为本发明第一较佳实施例的第一替代态样中附加步骤的斜视图。
图3为本发明第一较佳实施例的第二替代态样中步骤的流程图。
图2K-2M为本发明第一较佳实施例的第二替代态样中附加步骤的斜视图。
图4为本发明第二较佳实施例的第一替代态样中步骤的流程图。
图5A-5H为本发明第二较佳实施例中各步骤的斜视图。
图5I-5K为本发明第二较佳实施例的第一替代态样中附加步骤的斜视图。
图6为本发明第二较佳实施例的第二替代态样中步骤的流程图。
图5L-5N为本发明第二较佳实施例的第二替代态样中附加步骤的斜视图。
图7A-7K为本发明第三较佳实施例中附加步骤的斜视图。
图7L-7N为本发明第三较佳实施例的第一替代态样中附加步骤的斜视图。
图7O-7Q为本发明第三较佳实施例的第二替代态样中附加步骤的斜视图。
图8为本发明第二较佳实施例的完成的柔性衬底的斜视图。
图9显示通过本发明的方法所产生的走线在可靠性测试前后的剥离强度。
图10显示相较于现有减成法本发明的柔性衬底于退火前后的弯曲耐久性。
图11显示相较于现有减成法本发明中应变作为压力的函数的关系图。
图12显示相较于现有减成法本发明中应变作为温度的函数的关系图。
图13为使用本发明的柔性衬底的完成的COF的斜视图。
具体实施方式
随着输入/输出增加和装置尺寸减小以及更多功能和更高速度的趋势出现,对于衬底技术的需求比起以往任何时候都更具有挑战性。而随着电路间距的减小,现有的减法和半加成技术不再能够以合理的良率生产20μm以下并同时保持走线的顶部对底部的宽度比为1的精细走线。坚固的精细走线的生产对于高密度互连相当重要,以因应显示器驱动器、医疗设备、智能可穿戴设备、物联网(IoT)等的未来需求。
本发明公开了一种在柔性衬底上制造多个精细走线的方法,特别是用于柔性薄膜覆晶(COF)封装。此方法将提供可靠且坚固的铜走线,其具有精细到8μm的走线间距以及接近1的顶部宽度比。铜走线是通过全加成法来构成的,其于改性的介电材料上使用无电镀Ni-P作为种晶层,此介电材料具有特定厚度,使能够在介电材料/Ni-P界面上产生可靠的纳米尺寸的聚酰胺酸(PAA)固定层。利用所提出的制造方法,尽管铜走线具有光滑的表面,还是能够保持可靠的界面黏着,这有利于电路中的信号传输。就制程能力而言,所提出的制程可广泛与各种介电和表面抛光材料兼容。就组装能力而言,所形成的走线适用于各种互连方法,这些互连方法包括IC/晶片的热压接合、引线接合、黏接和焊接,以形成半导体封装。这种精细间距COF的产生是针对未来的小型化需求,包括有机发光二极体(OLED)、主动矩阵有机发光二极体(AMOLED)、液晶显示薄膜电晶体(LCD/TFT)、智能可穿戴装置、医学成像和IoTs封装。
在本发明中,精细间距的柔性薄膜覆晶(COF)是使用完全加成法来形成的,其能够形成可靠的黏着,以确保在柔性衬底上牢固地精确形成精细走线,并提供对于超细间距及高电性互连的独特机会。
下面将描述本发明的方法中的三个较佳实施例,第一较佳实施例使用一个金属层柔性衬底,第二较佳实施例使用两个金属层柔性衬底,第三较佳实施例使用超过两个叠层的导电金属层。另外,每个实施例可包括电解表面抛光或无电镀表面抛光。
现在请参照图1中的流程图和图2A-2J,将详细描述本发明所公开的方法中的第一较佳实施例。此方法首先是提供一柔性介电衬底10,其介电材料可以是任何种类的聚酰亚胺(PI),例如,Kapton PI或Upisel PI,改性PI(MPI),环烯烃聚合物(COP),或液晶聚合物(LCP)。介电衬底10的较佳厚度为约12.5至100μm,如图2A所示。
现在,在图1的步骤101中,通过向PI表面施加KOH/碱性化学品来改性聚酰亚胺表面。这样会改变分子键形成聚酰胺酸(PAA)层12,如图2B所示。为了达成所期望的走线的完整性能,优化改性化学品的浓度,以产生厚度小于10nm的PAA层。本发明的改性层非常薄(<10nm),其可以通过减少热处理期间在层上的水份吸收量来防止化学键合的降解,并因而将由吸湿膨胀系数引起的影响最小化。因此,在热处理后仍可保持高的黏合性。在某些不考虑热处理的情况下,PAA层可以超过10nm,但应小于100nm。超薄PAA层(厚度较佳为<10nm)包含有羧基和酰胺键,其对应于O=C-NH(酰胺)和O=C-OH(羧基),并能够用以增强聚酰亚胺和上覆的Ni-P层间的界面黏着。
接着,在步骤102中,通过浸入离子金属溶液中,将图中未示出的催化层沉积在PAA层上。通常上,沉积钯(Pd)或镍(Ni)来活化表面,以用于随后的无电镀Ni-P的施镀。在步骤103和图2C中,使用无电镀方式将自催化的镍-磷(Ni-P)种晶层14施加在改性的聚酰亚胺膜上。Ni-P层的厚度理想上为0.1μm+/-10%。种晶层中Ni-P的组成为Ni:96.5~97.5重量%,P:2.5~3.5重量%。
在步骤104中,将衬底在约200℃下退火持续至少10分钟至最多2小时。在步骤105中,如图2D所示,将光阻层16施加到衬底的种晶层表面,此光阻层16较佳为正向光阻。光阻可以是干膜或液态光阻。在光蚀刻过程中,光阻经曝光(步骤106和图2E)并显影(步骤107和图2F)以形成用于电路化的精细间距的走线。
在步骤108与图2G中,导电金属层20使用电解铜电镀形成至预定的厚度,其包含有主动接合的多个走线及焊垫,此电镀仅施加于没有覆盖光阻剂的区域。在部分应用中,电镀层的长宽比被控制在接近1,使用此方法的走线的顶面至底面宽度比也可接近于1。铜是具有高延展特性的精细晶粒沉积,铜的厚度约为8μm;于部分应用中,电解铜的厚度可以约为2-18μm。沉积铜的拉伸强度超过15%、抗拉强度在290-340N/mm2之间,电解铜的维氏硬度为100、纯度超过99.9%。电解铜电镀制程可以达成高速电镀,而可达成精细间距COP的量产。
在步骤109中,通过镀上电解Ni/Au、电解钯、电解钛、电解锡或电解铑,来完成走线的表面,如图2H中的22所示。
将光阻层16剥离,如步骤110和图2I所示,接着,使用过氧化氢酸性溶液蚀刻掉Ni-P种晶层14,此溶液被严格控制以单向蚀刻Ni-P种晶层的方式,在铜走线上没有或具有最少蚀刻,使铜走线保持长宽比接近1,如步骤111和图2J所示。这样就完成了于柔性衬底上的走线的形成。
走线间的内引线接合(ILB)间距是定义两个相邻走线间的中心距离的间距,每个相应的走线具有相应的表面层。本发明所公开的衬底的ILB小于约8μm。在部分应用中,ILB间距可以是4-30μm。
在完成形成柔性衬底上的走线后,将COF予以组装。走线与各种互连方法兼容,这些互连方法包括单颗或多颗晶粒的热压接合、黏接、引线接合和焊接,以形成半导体封装。
例如,图13显示了使用本发明的柔性衬底的完成的COF。位于使用PAA表面处理的衬底10上的具有表面抛光22的铜走线20是用来连接多个部件。图中显示了晶粒204为通过铜走线20a与金凸块202热压接合,且显示了阻焊层200和底部填充物205,而晶粒206是使用环氧树脂来接合到铜走线20b,金线208接合到铜走线20c,并将部件212焊接(210)到铜走线20d。
现在请参考图3中的流程图和图2A-2G与图2K-2M,以下将说明本发明的第一实施例中的第二替代态样。第一替代态样的制程包括电解表面抛光。第二替代态样的制程包括无电镀表面抛光。图3显示了第二替代态样的制程中的步骤,此些步骤直到步骤108,即如图2G所示的镀铜步骤,其与第一替代态样相同。
现在,在第二替代态样中,在步骤112中,从衬底剥离光阻16,在Ni-P层14上留下铜走线20,如图2K所示。接着,在步骤113中,将Ni-P层从衬底蚀刻掉,如图2L所示。
最后,在步骤114中,通过浸锡(Sn)、无电镀Ni/Au、无电镀镍/浸金(ENIG)、无电镀镍/无电镀钯/浸金(ENEPIG)、无电镀钯/自催化金(EPAG)或浸金/无电镀钯/浸金(IGEPIG)的全面或选择性表面抛光来完成走线的表面,如图2M中的22所示。在全面电镀中,电镀在基板上电路的所有区域上进行,而在选择性电镀中,电镀仅在需要表面处理的某些功能区域上进行。
第二替代态样的无电镀制程需要更薄的表面抛光厚度,但比起电解电镀则具有较低的析镀速率。
第一实施例显示一种具有至少一个金属层的柔性衬底的制造方法。金属层可以是一层导电金属层或超过一层的导电金属层。另外,柔性衬底可具有双面导电金属层或多于两个叠层的导电金属层。
本发明的第二实施例显示了双面(2ML)金属层的制程。现在请再参照图4中的流程图和图5A-5H,将详细描述本发明所公开的制程中的第二较佳实施例。此制程首先提供柔性介电衬底10,介电材料可以是任何种类的聚酰亚胺(PI),例如,Kapton PI或Upisel PI,改性PI(MPI),环烯烃聚合物(COP),或液晶聚合物(LCP),介电材料10的较佳厚度在约12.5至100μm,如图5A所示。
现在,在图4的步骤401中,以激光钻孔方式来钻穿衬底10形成穿孔11,如图5B所示。穿孔将电性连接在衬底任一侧上的金属层。在步骤402中,通过向聚酰亚胺表面施加KOH/碱性化学品,将PI表面进行改性。这样会改变分子键,而在衬底的顶侧上形成聚酰胺酸(PAA)层12,在衬底的底侧上形成PAA层13,如图5C所示,同时也将其形成在穿孔内。优化改性剂化学品的浓度,来产生小于10nm的PAA层厚度,以实现期望的走线的完整性能。在某些情况下,PAA层可以超过10nm,但应小于100nm。超薄PAA层(较佳厚度<10nm)含有羧基和酰胺键,其对应于O=C-NH(酰胺)和O=C-OH(羧基),并用于增强在聚酰亚胺和上覆的Ni-P层间的界面黏着。
接着,在步骤403中,通过浸入离子金属溶液中,将图中未示出的催化层沉积在PAA层12和13上。通常上,沉积钯(Pd)或镍(Ni)以活化表面,用于随后的无电镀Ni-P镀覆。在步骤404和图5D中,使用无电镀制程,将自催化镍-磷(Ni-P)种晶层14、15施加在改性聚酰亚胺薄膜的两侧和穿孔11内。Ni-P层的厚度理想上为0.1μm+/-10%。种晶层中Ni-P的组成为Ni:96.5~97.5wt%,P:2.5~3.5wt%。
在步骤405中,将衬底在约200℃下退火至少10分钟且最多2小时。在步骤406中,如图5E所示,将光阻层16、17分别施加到衬底的顶部和底部的种晶层表面,此光阻层16、17较佳为正向光阻。光阻可以是干膜或液体光阻。在光蚀刻制程中,将光阻曝光(步骤407和图5F)并显影(步骤408和图5G),以形成用于电路化的精精细间距的走线。
在步骤409和图5H中,使用电解铜电镀方式,将导电金属层20、21,包括用于主动接合的多个走线和焊垫,分别在衬底顶部和底部上镀上一个预期厚度。此电镀仅用于未被光阻覆盖的区域上。在部分应用中,控制此电镀层的长宽比接近1。使用此方法的走线的顶部宽度与底部宽度的比率可接近1。继续通过穿孔施镀,使在顶部和底部铜层间电性连接。铜是具有高延展性的细晶沉积物。铜的厚度约为8μm。在部分应用中,电解铜的厚度可以在2-18μm的范围内。铜沉积物的伸长强度超过15%,拉伸强度介于290-340N/mm2。电解铜的维氏硬度为100、纯度大于99.9%。
在步骤410中,通过电镀Ni/Au、电解钯、电解钛、电解锡或电解铑来完成走线20的表面,如图5I中的22所示。在衬底的顶部走线和底部走线中的至少一个完成了表面抛光22。
将光阻层16、17剥除,如步骤411和图5J所示,然后,使用过氧化氢酸性溶液将Ni-P种晶层14、15蚀刻掉,此溶液被严格控制以单向蚀刻Ni-P种晶层的方式,在铜走线上没有蚀刻或具有最少蚀刻,以保持铜走线的长宽比接近1,如步骤412和图5K所示。这样就完成了柔性衬底上的走线的形成。
现在请参照图6中的流程图和图5A-5H与图5L-5N,以下将说明本发明的第二实施例中的第二替代态样。第一替代态样的制程包括电解表面抛光。第二替代态样的制程包括无电镀表面抛光。图6显示了第二替代态样的制程中的步骤,此些步骤直到步骤409,即如图5H所示的镀铜步骤,其与第一替代态样相同。
现在,在第二替代态样中,在步骤413中,从衬底剥离光阻16、17,在Ni-P层14、15上留下铜走线20、21,如图5L所示。接着,在步骤414中,将Ni-P层从衬底蚀刻掉,如图5M所示。
最后,在步骤415中,通过浸锡(Sn)、无电镀Ni/Au、无电镀镍/浸金(ENIG)、无电镀镍/无电镀钯/浸金(ENEPIG)、无电镀钯/自催化金(EPAG)或浸金/无电镀钯/浸金(IGEPIG)的全面或选择性表面抛光来完成走线的表面,如图5N中的22所示。
本发明的第三实施例显示了超过两个叠层的导电金属层。现在请参考图5A-5H和图7A-7N,将详细描述本发明所公开的方法中的第三较佳实施例。第三实施例的制程步骤直到步骤409的镀铜步骤是与第二实施例相同,如图5H所示。
现在,如图7A所示,将光阻层16、17剥离,接着,使用过氧化氢酸性溶液蚀刻掉Ni-P种晶层14、15,此溶液被严格控制以单向蚀刻Ni-P种晶层的方式,在铜走线上没有或具有最少蚀刻,使铜走线保持长宽比接近1,如图7B所示。
现在,如图7C所示,将接合膜70、71分别层压在顶面和底面上。接合膜可以是任何种类的介电材料,包括聚酰亚胺、含氟聚合物、聚酯等。接合材料可以是用纤维增强的任何种类的改性环氧树脂或热固性黏着薄膜,例如,环氧树脂、氰化酯或丙烯酸黏着剂。接合膜具有低的热膨胀系数(CTE)和高的玻璃化转变温度(Tg)。或者,接合膜可以是味精接合膜(ABF),即一种由以下组成的环氧树脂基膜:双酚A环氧树脂:9wt%,石脑油:少于5.0wt%,环己酮:1.1wt%,N,N-二甲基甲酰胺:0.5wt%,甲苯:少于5.0wt%,乙醇:少于5.0wt%,甲基乙基酮:少于5.0wt%,以及二氧化硅粉:30~40wt%。或者,接合膜可以是由改性的丙烯酸制成的杜邦FR0100接合膜:N,N'-乙基双:>=10-<20%,以及三氧化二砷:>=1-<10%。
另一聚酰亚胺基膜73、74分别于接合膜上、下形成薄层,见图7D,另外也可选择聚酰亚胺、液晶高分子(LCP)作为层73、74,介电层73、74较佳厚度介于12.5-100μm,如图7D所示。
接着,以激光钻孔穿过位于衬底10顶面与底面的PI层以及接合层形成穿孔75,如图7E所示,穿孔会电性连接于衬底任一侧的附加金属层至金属层20。
聚酰亚胺表面73、74通过施加KOH/碱性化学品至PI表面来进行改性,改变分子键结以形成PAA固定层76、77,如图7F所示,优化改性化学品的浓度,使产生PAA层的厚度小于10nm,来达成预定的走线整合效能。
接着,图中未示的催化层通过沉浸于离子金属溶液中来沉积于PAA层76、77,一般通过沉积钯或镍来活化表面用于后续无电镀Ni-P;于图7G中,使用无电镀的施镀程序将自催化镍磷(Ni-P)种晶层78、79分别施加于位于衬底顶面与底面的改性聚酰亚胺薄膜76、77上,Ni-P层的厚度理想上为0.1+/-10%μm,种晶层的Ni-P组成为Ni:96.2-97.5wt%,P:2.5-3.5wt%。
衬底以约为200℃持续至少10分钟至最多2小时来进行退火,如图7H所示,将光阻层82、83分别施加于位于衬底底面与顶面的种晶层78、79上,此光阻层82、83较佳为正向光阻。光阻可为干膜或是液态光阻。于光蚀刻制程中,光阻曝光(见图7I)并显影(见图7J),以形成用于衬底的顶面与底面电路化的精细间距走线。
现在,请参阅图7K,使用电解铜电镀方式,将导电金属90、91,包括用于主动接合的走线及焊垫,分别镀于衬底的顶面与底面至预定的厚度,此电镀仅施加于没有覆盖光阻的区域。在部分应用中,控制电镀层的长宽比接近1。使用此方法的走线的顶面至底面宽度比也可接近于1。铜是具有高延展特性的精细晶粒沉积物,铜的厚度约为8μm,铜的成分细节如前面内容所详述。
走线的表面是通过镀上浸锡(Sn)、电解Ni/Au、电解钯、电解钛、电解锡或电解铑来完成,请参阅图7L,至少一个位于衬底顶面或是底面的走线完成了表面抛光92。
光阻层82、83形成条状,见图7M,并接着使用过氧化氢酸性溶液来蚀刻Ni-P种晶层78、79,其是以单向严格控制的方式来蚀刻Ni-P种晶层,而能够不蚀刻或是最少蚀刻至铜走线,以维持铜走线长宽比接近1,如图7N所示,其于柔性衬底完成了四层金属走线。
本发明所公开的第三实施的第二替代态样例如图5A-5H、图7A-7K以及图7O-7Q所示,第一替代态样的制程包含电解表面抛光,而第二替代态样的制程包含无电镀表面抛光,第二替代态样的制程步骤中直到镀铜步骤是与第一替代态样一致,如图7K所示。
现在,于第二替代态样中,光阻78、79于衬底上形成条状,而留下铜走线90、91于Ni-P层78、79上,如图7O所示,接着,Ni-P层会由衬底上蚀刻去除,如图7P所示。
最后,走线的表面可通过下列表面抛光方式来完成,譬如浸锡(Sn)、无电镀镍/金、无电镀镍/浸金(ENIG)、无电镀镍/无电镀钯/浸金(ENEPIG)、无电镀钯/自催化金(EPAG)、或浸金/无电镀钯/浸金(IGEPIG),如图7Q的92所述,至少一个位于衬底顶面或是底面的走线完成了表面抛光92。
制造完走线后,再形成譬如阻焊剂或覆盖层的覆盖涂层,来作为相邻铜走线间的阻障,以保护走线避免短路;本发明所公开的柔性衬底适用各种的覆盖涂层材料。
图8显示了第三实施例的四层导电层的柔性衬底的完整斜视图。可以看出,金属层90、20、21、91(由上到下)通过穿孔75和11电性连接。图中显示表面抛光92在暴露的顶部铜走线90上。例如阻焊剂的覆盖涂层93覆盖部分的顶部铜走线90并覆盖底部铜走线91。在此实施例中,这些区域不用于接合,因此它们不需要较为昂贵的表面抛光92。
此外,通过在第三实施例的完成的铜形成物上依序地重复第三实施例的步骤,可以实现具有四层以上的多层导电层的柔性衬底。
本发明的方法可以实现非常光滑的表面(Ra<100nm)而不损害走线的黏着。此光滑表面能够将信号传输期间的导体损耗予以最小化。走线与各种互连方法兼容,而互连方法包括与单颗晶粒或多颗晶粒的热压接合、黏接、引线接合和焊接,以形成半导体封装。
在本发明的方法中,衬底的TEM图像显示,在300℃退火前和退火后,Ni-P种晶层的厚度为约100nm,PAA固定层的厚度为约3-4nm,且退火后未观察到PAA固定层的降解。
图9显示了在可靠性测试前(T=0)和后通过本发明的方法所制造的走线的剥离强度。这些可靠性测试包括HTS-高温储存(150℃,500小时)、MSL-3(-60℃至60℃持续48小时,且于254℃峰值3x回流)、TST-热冲击(-40℃至125℃,500次循环,1小时/循环)和LTS-低温储存(-40℃,500小时)。
图10显示了与使用溅射型基膜材料的传统减成法制程比较,本发明所提出的方法(全加成法)使用直接金属化的柔性衬底于退火前和退火后的弯曲耐久性。传统方法显示在图式的左侧。图中显示了在退火前(301),在200℃退火24小时后(302),以及在300℃退火24小时后(303)的弯曲耐久性。右边则显示了本发明的全加成法在退火前(305),在200℃退火24小时后(306),以及在300℃退火24小时后(307)的结合耐久性。可以看出,本发明的方法在所有情况下都提供了弯曲耐久性的改善。
图11显示与现有减成法(溅射)制程313相较,本发明所公开的全加成法制程311的热压接合的塑性变形特性。在图式中,温度固定在345℃,压力是变化的。
图12显示了与现有减成法制程323相较,本发明所公开的制程321在140MPa的固定压力下随着温度变化的变形应变。
本发明所公开的方法中,走线黏着强度和弯曲耐久性即使没有比通过现有减成法用溅射型基膜材料所制造的衬底更好,也会是相当的。同样地,相较于通过使用溅射型基膜材料的常规减成法所制造的衬底,已观察到热压接合后类似的塑性变形行为。特别是由于在300℃热处理24小时后PAA固定层的稳定性,保持了可靠的黏着强度(在两个或两个以上的金属层衬底的两侧)。
本发明所公开的柔性衬底适用于各种互连方法,这些互连方法包括IC/晶片的热压接合、引线接合、黏接和焊接,以形成半导体封装。本发明所公开的制造方法使得铜走线会具有极其光滑的表面(Ra<100nm),而不损害走线的黏着性。此光滑表面能够将信号传输期间的导体损耗予以最小化。
本发明公开了一种用于COF具有精细走线的柔性衬底的制造方法,其可以整合到AMOLED、OLED、TFT/LCD以及后面所列的至少一种:智能电话装置、便携式装置、IoT封装、智能可穿戴装置、平板电脑、UHD TV、微型显示器、光电产品、医疗装置、工业产品(建筑和机械监控)以及IC封装/3D IC集成模块。
唯以上所述者,仅为本发明的较佳实施例而已,并非用来限定本发明实施的范围。故即凡依本发明权利要求书所述的特征及精神所为的均等变化或修饰,均应包括于本发明的范围内。
Claims (20)
1.一种柔性衬底的制造方法,包括:
提供一柔性介电衬底,该柔性介电衬底包括任何种类的聚酰亚胺(PI),包括Kapton PI或Upisel PI,改性PI(MPI),环烯烃聚合物(COP)或液晶聚合物(LCP);
对于该介电衬底进行碱性改性,以在该介电衬底的一表面上形成一聚酰胺酸(PAA)固定层;
在该PAA层上无电镀镀上一Ni-P种晶层;
在该Ni-P种晶层上形成一光阻图案;
在该光阻图案内镀上多个铜走线;
在该些铜走线上镀上一表面抛光层;及
移除该光阻图案并蚀刻掉未被该些铜走线覆盖的该Ni-P种晶层,以完成该柔性衬底。
2.如权利要求1所述的方法,其中该碱性改性包括将KOH/碱性化学品施加到该介电衬底上,其中该PAA层的厚度小于100nm,较佳小于10nm。
3.如权利要求1所述的方法,还包括将包含钯(Pd)或镍(Ni)的一催化层通过浸入一离子金属溶液中来沉积在该PAA层上,以活化该PAA层,用于随后的无电镀镀上Ni-P种晶层的步骤。
4.如权利要求1所述的方法,其中该无电镀镀上该Ni-P种晶层的步骤是自催化过程,且其中该Ni-P种晶层的厚度为0.1μm+/-10%,组成为Ni:96.5~97.5wt%,P:2.5~3.5wt%。
5.如权利要求1所述的方法,其中该形成该光阻图案的步骤包括:
施加一光阻在该Ni-P种晶层上;及
对于该光阻进行曝光和显影,以形成用于电路化的精细间距走线的一图案。
6.如权利要求1所述的方法,还包括在形成该Ni-P种晶层的步骤后,将该衬底较佳在200℃下退火至少10分钟至最多2小时。
7.如权利要求1所述的方法,其中该镀上该些铜走线的步骤,包括无电镀镀上铜至介于约2至18μm的厚度,其中该些铜走线的顶部宽度与底部宽度的比率接近1,其中该些铜走线的伸长强度超过15%,其中该些铜走线的拉伸强度介于约290和340N/mm2,且其中该些铜走线的维氏硬度为100,纯度大于99.9%。
8.如权利要求1所述的方法,其中该表面抛光层包括浸锡、电解Ni/Au、无电镀镍/浸金(ENIG)、无电镀镍/无电镀钯/浸金(ENEPIG)、电解钯、电解钛、电解锡、电解铑、无电镀钯/自催化金(EPAG)或浸金/无电镀钯/浸金(IGEPIG)。
9.如权利要求1所述的方法,还包括:
激光钻孔形成至少一第一穿孔完全通过该介电衬底,其中该对于该介电衬底进行碱性改性,无电镀该第一Ni-P种晶层以及形成该第一光阻图案的步骤是执行在顶面和底面上,且其中该镀上多个第一铜走线是位于该第一光阻图案内并贯穿该至少一第一穿孔。
10.如权利要求9所述的方法,还包括:
在该些第一铜走线的顶面和底面上层压一接合膜;
在该接合膜的顶部和底部层压一介电层;
激光钻孔形成至少一第二穿孔完全通过该介电衬底和该接合膜至接触在该衬底的顶部和底部上的该些第一铜走线;
然后对于该介电层进行碱性改性,以在该介电层的顶面和底面上以及在至少一该第二穿孔内形成一第二聚酰胺酸(PAA)固定层;
在该第二PAA层的顶部和底部上无电镀镀上一第二Ni-P种晶层;
在该第二Ni-P种晶层的顶部和底部形成一第二光阻图案;
在该第二光阻图案内镀上多个第二铜走线,并贯穿该至少一第二穿孔;
在该些第二铜走线上镀上一表面抛光层;及
去除该第二光阻图案并蚀刻掉未被该些第二铜走线覆盖的该第二Ni-P种晶层,以完成该柔性衬底。
11.一种薄膜覆晶,包括:
一柔性介电衬底,在其顶面上具有第一聚酰胺酸(PAA)固定层;
至少一第一铜走线,位于该第一PAA层上的一第一Ni-P种晶层上,且在该至少一第一铜走线的一顶面上具有一表面抛光层,其中该表面抛光层包括电解Ni/Au,无电镀镍/浸金(ENIG),无电镀镍/无电镀钯/浸金(ENEPIG),电解钯,电解钛,浸锡,电解锡,电解铑,无电镀钯/自催化金(EPAG)或浸金/无电镀钯/浸金(IGEPIG);及
至少一晶粒,设置在该介电衬底上至该至少一第一铜走线上。
12.如权利要求11所述的薄膜覆晶,其中该柔性介电衬底包括任何种类的聚酰亚胺(PI),包括Kapton PI或Upisel PI,或液晶聚合物(LCP)。
13.如权利要求11所述的薄膜覆晶,更包括:
一第二PAA层,位于该介电衬底的一底面上;及
至少一第二铜走线,位于该第二PAA层上的一第二Ni-P种晶层上,其中该第一铜走线和该第二铜走线通过穿过该介电衬底的一铜穿孔互连,其中该铜穿孔还包括接触该介电衬底的一第三PAA层和在该第三PAA层与该铜穿孔间的一第三Ni-P晶种层。
14.如权利要求13所述的薄膜覆晶,其中该第一PAA层和该第二PAA层的厚度小于100nm,较佳小于10nm。
15.如权利要求13所述的薄膜覆晶,其中该第一Ni-P种晶层和该第二Ni-P种晶层的厚度为0.1μm+/-10%,表面粗糙度的Ra值小于100nm,且组成为Ni:96.5~97.5wt%,P:2.5~3.5wt%。
16.如权利要求13所述的薄膜覆晶,其中该至少一第一铜走线和该至少一第二铜走线上的厚度介于约2至18μm,其中该至少一第一铜走线和该至少一第二铜走线的顶部宽度与底部宽度的比率接近1,其中该至少一第一铜走线的伸长强度超过15%,其中该至少一第一铜走线的拉伸强度介于约290和340N/mm2,且其中该至少一第一铜走线和该至少一第二铜走线的维氏硬度为100,纯度大于99.9%。
17.如权利要求13所述的薄膜覆晶,其中两个相邻的该些第一铜走线间和两个相邻的该些第二铜走线间的中心距离小于8μm。
18.如权利要求13所述的薄膜覆晶,其中在低温存储,高温存储,湿气敏感度等级3和热冲击的可靠性测试后,该薄膜覆晶在薄膜上的第二剥离强度等于或大于在该可靠性测试前在该薄膜覆晶上的第一剥离强度。
19.如权利要求13所述的薄膜覆晶,更包括:
在该至少一第一铜走线上的一第一接合膜和在该至少一第二铜走线上的一第二接合膜;及
在该第一和第二接合膜上的附加的柔性介电衬底层,以及至少一第三和第四铜走线分别在该第三和第四附加的柔性介电衬底层上的第三和第四PAA锚定层的第三和第四Ni-P晶种层上,其中该至少一第三和第四铜走线分别通过第二和第三铜穿孔穿过该第三和第四附加的PI或LCP层和该第一和第二接合膜,分别在该第一和第二至少一铜走线底层互连,其中该第二和第三铜穿孔还包括分别接触该第三和第四附加的柔性介电衬底层以及该第一和第二接合膜的一第四PAA层,以及在该第四PAA层与该第二和第三铜穿孔间的一第四Ni-P晶种层,其中该至少一晶粒设置并结合在该至少一第三和第四铜走线的最顶部上。
20.如权利要求19所述的薄膜覆晶,更包括在该薄膜覆晶的顶部和底部的任意数量的接合层、附加的柔性介电衬底层以及铜走线。
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KR20220061992A (ko) | 2022-05-13 |
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