CN114609858B - Optical proximity correction method and device and electronic equipment - Google Patents
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Abstract
The invention provides an optical proximity correction method, an optical proximity correction device and electronic equipment. The invention provides an optical proximity correction method, which classifies all main graphs in a test layout according to different graph sizes, and then sets different cycle iteration times of optical proximity correction for the main graphs in various classified main graph sets according to different graph sizes, thereby avoiding the problems of overlong integral execution time of the test layout and waste of manpower and material resources caused by the fact that the cycle iteration times of the same optical proximity correction (OPC cycle iteration times with more times determined by the convergence degree of the main graphs with small graph sizes) is adopted for any main graph in the test layout in the prior art.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to an optical proximity correction method, an optical proximity correction device, and an electronic apparatus.
Background
With the development of the semiconductor industry, people have increasingly stringent requirements on performance and energy consumption of chips, and in order to obtain chips with smaller area, higher performance and lower energy consumption, the size of each pattern on the chip and the distance between the patterns need to be further reduced, and the reduction of the distance can cause the design distance between some patterns on the layout to be smaller than the wavelength of light. Therefore, the layout needs to be corrected before the layout is imprinted on the mask, so as to prevent Optical Proximity Effect (OPE) from being generated in the photolithography process, and avoid the distortion of the pattern caused by the inconsistency between the pattern imprinted on the chip and the design.
A technique of correcting the layout in order to avoid the optical proximity effect is an Optical Proximity Correction (OPC) technique, i.e., adjusting the edges of part or all of the main patterns in the layout or adding auxiliary patterns in the vicinity thereof. However, under the existing lithography process conditions, the main pattern of the small critical dimension CD (line width of the main pattern) in the layout conforming to the design rule has a smaller critical dimension CD, so the adjustable spatial range around the main pattern is smaller, which results in that the main pattern of the small critical dimension CD in one layout is more difficult to converge than the main pattern of the large critical dimension CD.
For the problem, in the prior art, all the main patterns in the layout are set to have the same OPC iteration cycle number, and the OPC iteration cycle number is determined based on the convergence degree of the main patterns satisfying the CD with the small critical dimension, so as to ensure the convergence degree of the main patterns of the CD with the small critical dimension in the layout. Theoretically, the greater the number of iterations of the OPC loop, the better the OPC accuracy that can be achieved. However, the running time of the OPC execution process must be within a reasonable range, limited by the product publishing cycle. Therefore, the method for determining the number of OPC loop iterations by using the convergence of the main graph of the small-critical-size CD in the prior art will result in an excessively long OPC correction time for the main graph of the large-critical-size CD without such a number of loop iteration correction times, which further causes problems of an excessively long overall OPC execution time for the layout, and waste of manpower and resources.
Disclosure of Invention
The invention aims to provide an optical proximity correction method, an optical proximity correction device and electronic equipment, which are used for reducing the total OPC iteration cycle times of a layout while ensuring the convergence of main graphs of various key sizes in the layout, so that the OPC correction time of the layout is reduced on the premise of not reducing the OPC precision.
In a first aspect, to solve the above technical problem, the present invention provides an optical proximity correction method, which specifically includes the following steps:
and determining a test layout corresponding to the pre-manufactured layout, wherein the test layout has a plurality of main graphs with different graph sizes.
And carrying out graph size classification on all main graphs in the test layout to form a first main graph set and a second main graph set.
And screening a main graph from the first main graph set and/or the second main graph set, carrying out multiple times of optical proximity correction on the main graph, and recording the edge placement error of the main graph after each time of optical proximity correction on the main graph.
And determining the number of loop iterations of the optical proximity correction executed by the main graph when the edge placement error of the main graph which is subjected to the optical proximity correction for a plurality of times does not change within a preset range.
And taking the determined cycle iteration number as a target cycle iteration number of optical proximity correction to be performed on the main graph in the first main graph set or the second main graph set containing the main graph for performing optical proximity correction for multiple times, and performing optical proximity correction of the target cycle iteration number on each main graph in the first main graph set and the second main graph set.
Further, the step of performing graph size classification on all main graphs in the test layout to form a first main graph set and a second main graph set includes: determining the graph size of each main graph in the test layout, and forming a first main graph set by using all main graphs of which the graph sizes are smaller than a graph size threshold; and forming the second main pattern set by using all the main patterns of which the pattern sizes of the main patterns in the test layout are not smaller than the pattern size threshold.
Further, the value range of the graph size threshold is as follows: 250nm to 350 nm.
Furthermore, the target loop iteration number of the optical proximity correction to be performed on the main graph in the first main graph set is larger than that of the optical proximity correction to be performed on the main graph in the second main graph set.
Further, the pattern size includes a line width or a pitch of the pattern.
Further, the preset range of the edge placement error of the main graph in the first main graph set is as follows: -1nm to 1 nm.
Further, the preset range of the edge placement error of the main graph in the second main graph set is as follows: -2nm to 2 nm.
In a second aspect, based on the optical proximity correction method, the present invention further provides an optical proximity correction apparatus, which is characterized by specifically including the following modules:
and the test layout determining module is used for determining a test layout corresponding to the prefabricated layout, and the test layout is provided with a plurality of main graphs with different graph sizes.
And the graph set forming module is used for carrying out graph size classification on all the main graphs in the test layout so as to form a first main graph set and a second main graph set.
And the first optical proximity correction module is used for screening out a main graph from the first main graph set and/or the second main graph set, performing multiple optical proximity corrections on the main graph, and recording the edge placement error of the main graph after performing each optical proximity correction on the main graph.
And the cycle iteration number determining module is used for determining the cycle iteration number of the optical proximity correction executed by the main graph when the edge placement error of the main graph subjected to the optical proximity correction for multiple times does not change any more within a preset range.
And the second optical proximity correction module is used for taking the determined cycle iteration number as a target cycle iteration number of optical proximity correction to be performed on the main graph in the first main graph set or the second main graph set containing the main graph subjected to the multiple optical proximity correction, and performing the optical proximity correction of the target cycle iteration number on each main graph in the first main graph set and the second main graph set.
Further, the graph set forming module includes:
the first main graph set forming unit is used for determining the graph size of each main graph in the test layout and forming the first main graph set by all the main graphs of which the graph size is smaller than a graph size threshold value.
And the second main pattern set forming unit is used for forming the second main pattern set by determining all main patterns of which the pattern sizes are not smaller than the pattern size threshold in the test layout.
In a third aspect, based on the optical proximity correction method, the invention further provides an electronic device, which includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus.
A memory for storing a computer program.
And the processor is used for realizing the steps of the optical proximity correction method when executing the program stored in the memory.
Compared with the prior art, the technical scheme provided by the invention has at least one of the following beneficial effects:
the invention provides an optical proximity correction method, which classifies all main graphs in a test layout according to different graph sizes, and then sets different cycle iteration times of optical proximity correction for the main graphs in various classified main graph sets according to different graph sizes, thereby avoiding the problems of overlong integral execution time of the test layout and waste of manpower and material resources caused by the fact that the cycle iteration times of the same optical proximity correction (OPC cycle iteration times with more times determined by the convergence degree of the main graphs with small graph sizes) is adopted for any main graph in the test layout in the prior art.
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FIG. 1 is a flowchart illustrating an optical proximity correction method according to an embodiment of the present invention.
Fig. 2 is a graph illustrating an edge placement error of a main graph in the first main graph set after performing multiple optical proximity corrections according to an embodiment of the present invention.
Fig. 3 is a graph illustrating an edge placement error of a main graph in the second main graph set after performing multiple optical proximity corrections according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of an optical proximity correction apparatus according to an embodiment of the present invention.
Detailed Description
The optical proximity correction method, apparatus and electronic device according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" are intended to cover only the explicitly identified steps or elements as not constituting an exclusive list and that the method or apparatus may comprise further steps or elements. In describing embodiments of the present invention in detail, the cross-sectional views illustrating the device structures are not enlarged partially in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background, at present, under the existing lithography process conditions, the main pattern of the small critical dimension CD (line width of the main pattern) in the layout conforming to the design rule has a smaller critical dimension CD, so that the adjustable spatial range around the main pattern is smaller, which makes it more difficult to converge the main pattern of the small critical dimension CD in one layout than the main pattern of the large critical dimension CD.
For the problem, in the prior art, all main patterns in the layout are not distinguished, but the same OPC iteration cycle times are directly set for all main patterns in the layout according to empirical values, and the OPC iteration cycle times are determined based on the convergence degree of the main patterns satisfying the small critical dimension CD, so as to ensure the convergence degree of the main patterns of the small critical dimension CD in the layout. Theoretically, the more the number of OPC loop iterations, the better the OPC accuracy that can be achieved. However, the running time of the OPC execution process must be within a reasonable range, limited by the product publishing cycle. Therefore, the method for determining the number of OPC loop iterations by using the convergence of the main pattern of the small-critical-size CD in the prior art will result in an excessively long OPC correction time of the main pattern of the large-critical-size CD without such a number of loop iteration correction times, thereby causing problems of an excessively long overall OPC execution time of the layout and waste of manpower and resources.
Based on the above, the researchers of the present invention propose to classify the pattern sizes of the main patterns in the layout, and then set different optical proximity correction loop iteration times for the main patterns with different pattern sizes according to the actual requirements of the main patterns, for example, a main pattern with a small pattern size whose convergence rate is difficult to reach a preset target value due to a small surrounding space, and set a loop iteration time for the main pattern with a loop iteration time greater than that of the main pattern with a large pattern size according to the actual convergence rate, so as to reduce the total execution time of OPC correction of the layout without reducing the accuracy of optical proximity correction.
Therefore, the invention provides an optical proximity correction method, an optical proximity correction device and electronic equipment, which are used for reducing the total OPC iteration cycle times of a layout while ensuring the convergence of main graphs of various key sizes in the layout, thereby reducing the OPC correction time of the layout on the premise of not reducing the OPC precision.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for optical proximity correction according to an embodiment of the present invention, the method including the following steps:
and S100, determining a test layout corresponding to the prefabricated layout, wherein the test layout is provided with a plurality of main graphs with different graph sizes.
In this embodiment, a corresponding test layout is determined according to the prefabricated layout, so as to verify whether the convergence degree of each main pattern in the prefabricated layout meets the design requirement through subsequent steps, and if not, OPC correction can be performed in time, so that the product yield is effectively improved, and the research and development progress is promoted. The test layout comprises a plurality of main patterns, the sizes of the main patterns are different, the main patterns are partially the same, and the main patterns are partially different, so that the main patterns can be classified in the subsequent step S200. Illustratively, the main graph in the test layout is a line end point graph and is a polygon graph of any other shape.
Step S200, carrying out graph size classification on all main graphs in the test layout to form a first main graph set and a second main graph set.
Wherein the pattern size includes a line width or a pitch of the pattern. Illustratively, in this embodiment, the pattern size is preferably a line width of the main pattern in the test layout (or referred to as a critical dimension CD of the main pattern).
In this embodiment, after the test layout is determined in step S100, for each main pattern in the test version, determine each pattern line width CD of the main pattern first, then determine a pattern line width CD threshold according to actual conditions, and determine that the pattern line width CD of the main pattern is smaller than all main patterns of the pattern line width CD threshold, form the first main pattern set, and determine that the pattern line width CD of the main pattern in the test layout is not smaller than all main patterns of the pattern line width CD threshold, form the second main pattern set. Illustratively, the value range of the pattern line width CD threshold provided in the embodiment of the present invention is: 50nm to 350 nm. Preferably, the value of the line width CD threshold of the pattern provided in the embodiment of the present invention is 300 nm.
It should be noted that, in the embodiment of the present invention, when the main pattern in the test layout is classified into the first main pattern set and the second main pattern set, no matter what shape the main pattern is, the main pattern is taken as a whole to measure the line width CD of the pattern. In addition, in the embodiment of the present invention, two main pattern sets determined by using all the main patterns in the test version according to a pattern line width CD threshold are shown only as an example, then a uniform number of iterations of optical proximity correction is set for all the main patterns corresponding to each main pattern set, and different numbers of iterations of optical proximity correction are set for different main pattern sets. In other embodiments, the embodiment of the present invention further divides all the main patterns in the test layout into a plurality of main pattern sets according to the pattern line width CD according to two or more pattern line width CD thresholds, and sets a cycle iteration number of optical proximity correction for each main pattern set, that is, divides different main pattern sets according to the pattern size, and then sets different cycle iteration numbers of optical proximity correction for different main pattern sets respectively belongs to the protection scope of the present invention.
Step S300, selecting a main pattern from the first main pattern set and/or the second main pattern set, performing multiple optical proximity corrections on the main pattern, and recording an edge placement error of the main pattern after each optical proximity correction on the main pattern.
In this embodiment, after exemplarily classifying all main graphics in the test layout into the first main graphics set and the second main graphics set, a main graphics is screened from the first main graphics set, and in order to facilitate distinction from the main graphics in the second main graphics set, in this embodiment of the present invention, the main graphics in the first main graphics set are referred to as first main graphics, and the main graphics in the second main graphics set are referred to as second main graphics; then, a plurality of times of OPC corrections are performed on a first main pattern selected from the first main pattern set, and an edge placement error EPE of the first main pattern after each OPC correction is calculated and recorded, and then, a graph of the edge placement error with the edge placement error EPE as a vertical coordinate and with the number of OPC loop iterations as a horizontal coordinate is drawn for the first main pattern, for example, fig. 2. Then, it is determined according to the graph of the edge placement error of the first main graph that after the edge placement error EPE of the first main graph is corrected for a certain number of OPC iterations, the edge placement error EPE of the first main graph will not change within a preset range, for example, when the number of OPC loop iterations in fig. 2 is 14 and later, the edge placement error EPE of the first main graph will be maintained at-1 nm, and the number of OPC loop iterations corresponding to the edge placement error EPE when it does not change within the preset range is used as the target number of loop iterations a for optical proximity correction to be performed on the first main graph and each main graph in the first main graph set including the first main graph. Then, using the same method and with reference to fig. 3, a target number of loop iterations B of optical proximity correction to be performed on each second main pattern included in the second main pattern set is determined. And, a is necessarily different from B.
Further, in this embodiment of the present invention, the target number a of iterations of optical proximity correction to be performed on the main graphics in the first main graphics set is greater than the target number B of iterations of optical proximity correction to be performed on the main graphics in the second main graphics set.
It should be noted that, as can be seen from fig. 2 and 3, whether it is a graph of the edge placement error corresponding to the first main pattern (small CD) in the first main pattern set or a graph of the edge placement error corresponding to the second main pattern (large CD) in the second main pattern set, after a certain number of OPC loop iterations, the corresponding edge placement error EPE does not change within its respective preset range, that is, for example, fig. 2, when the number of OPC loop iterations is between 14 and 19, the edge placement error EPE does not change within the preset range, at this time, in order to ensure the convergence of main patterns with different pattern sizes, one OPC loop iteration number is selected from 14 to 19 as the target loop iteration number a, and in the embodiment of the present invention, it is preferable to select the minimum number of OPC loop iterations when the edge placement error EPE does not change within the preset range, for example, 14, as a target number of loop iterations a of the optical proximity correction to be performed subsequently for each of the first main patterns in the first main pattern set. Similarly, using the same method, the target cycle iteration number B of the optical proximity correction to be subsequently performed on each second main graph in the second main graph set is preferably selected, which is not described in detail herein.
In step S400, the number of iterations of the loop of the optical proximity correction performed on the main graph is determined when the edge placement error of the main graph subjected to the optical proximity correction for multiple times does not change within the preset range.
Wherein, the preset range of the edge placement error of the main graphics in the first main graphics set is as follows: -1nm to 1 nm. The preset range of the edge placement error of the main graph in the second main graph set is as follows: -2nm to 2 nm.
Step S500, using the determined number of loop iterations as a target number of loop iterations for optical proximity correction to be performed on the main graph in the first main graph set or the second main graph set including the main graph subjected to optical proximity correction for multiple times, and performing optical proximity correction on each main graph in the first main graph set and the second main graph set for the target number of loop iterations.
In this embodiment, since all the main patterns in the test layout are classified according to different pattern sizes, and then the main patterns in the various classified main pattern sets are set with different optical proximity correction loop iteration times according to different pattern sizes, the optical proximity correction times B of each second main pattern with the pattern size larger than the pattern size threshold included in the test layout is reduced while the convergence degree of all the main patterns in the first main pattern set with the small pattern size in the test layout is ensured, so that the total OPC execution time of the test layout is reduced, and the purpose of saving manpower and material resources is achieved.
Based on the above-mentioned optical proximity correction method, the present embodiment further provides an optical proximity correction apparatus, which specifically refers to fig. 4, where fig. 4 is a schematic structural diagram of the optical proximity correction apparatus in an embodiment of the present invention, and the apparatus includes:
and a test layout determining module 410, configured to determine a test layout corresponding to the pre-fabricated layout, where the test layout has a plurality of main patterns with different pattern sizes.
The graph set forming module 420 is configured to perform graph size classification on all the main graphs in the test layout to form a first main graph set and a second main graph set.
The first optical proximity correction module 430 is configured to screen out a main graph from the first main graph set and/or the second main graph set, perform multiple optical proximity corrections on the main graph, and record an edge placement error of the main graph after each optical proximity correction on the main graph.
The loop iteration number determining module 440 is configured to determine the number of loop iterations of optical proximity correction that have been performed on the main graph when the edge placement error of the main graph subjected to multiple optical proximity corrections no longer changes within a preset range.
A second optical proximity correction module 450, configured to determine the number of cycle iterations as a target number of cycle iterations for optical proximity correction to be performed on the main graph in the first main graph set or the second main graph set that includes the main graph for performing multiple optical proximity correction, and perform optical proximity correction on the target number of cycle iterations for each main graph in the first main graph set and the second main graph set.
Optionally, the graph set forming module 420 includes: a first main pattern set forming unit and a second main pattern set forming unit; wherein,
the first main graph set forming unit is used for determining the graph size of each main graph in the test layout, and forming the first main graph set by using all main graphs of which the graph sizes are smaller than a graph size threshold;
and the second main pattern set forming unit is used for forming the second main pattern set by all the main patterns of which the pattern sizes of the main patterns in the determined test layout are not less than the pattern size threshold.
In summary, in the optical proximity correction method provided by the present invention, all main graphs in the test layout are classified according to different graph sizes, and then different cycle iteration times of optical proximity correction are set for the main graphs in the various main graph sets after classification according to different graph sizes, so that problems of overlong total overall OPC execution time of the test layout and waste of manpower and resources due to the fact that the same cycle iteration times of optical proximity correction (OPC cycle iteration times with more times determined by using the convergence of the main graphs with small graph sizes) are adopted for any main graphs in the test layout in the prior art are avoided.
The embodiment of the invention also provides electronic equipment which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus,
a memory for storing a computer program.
The processor, when being used for executing the program stored in the memory, is used for implementing the optical proximity correction method provided by the embodiment of the invention, and specifically comprises the following steps:
and determining a test layout corresponding to the prefabricated layout, wherein the test layout is provided with a plurality of main graphs with different graph sizes.
And carrying out graph size classification on all main graphs in the test layout to form a first main graph set and a second main graph set.
And screening a main graph from the first main graph set and/or the second main graph set, carrying out multiple times of optical proximity correction on the main graph, and recording the edge placement error of the main graph after each time of optical proximity correction on the main graph.
And determining the cycle iteration number of the optical proximity correction executed by the main graph when the edge placement error of the main graph which is subjected to the optical proximity correction for a plurality of times does not change within a preset range.
And taking the determined cycle iteration number as a target cycle iteration number of optical proximity correction to be performed on the main graph in the first main graph set or the second main graph set containing the main graph for performing optical proximity correction for multiple times, and performing optical proximity correction of the target cycle iteration number on each main graph in the first main graph set and the second main graph set.
In addition, other implementation manners of the optical proximity correction method implemented by the processor executing the program stored in the memory are the same as the implementation manners mentioned in the foregoing method embodiment section, and are not described herein again.
The communication bus mentioned in the above control terminal is a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus is divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface is used for communication between the electronic equipment and other equipment.
The Memory includes a Random Access Memory (RAM) and a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory is also at least one storage device located remotely from the processor.
The Processor is a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; or a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components.
In another embodiment of the present invention, there is also provided a computer-readable storage medium having stored therein instructions, which when run on a computer, cause the computer to execute the optical proximity correction method according to any one of the above embodiments.
In the above embodiments, all or part is implemented by software, hardware, firmware, or any combination thereof. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer is a general purpose computer, special purpose computer, computer network, or other programmable device. The computer instructions are stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions are transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium is a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus, the electronic device, and the computer-readable storage medium embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference may be made to the partial description of the method embodiments for relevant points.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. An optical proximity correction method, comprising:
determining a test layout corresponding to the prefabricated layout, wherein the test layout is provided with a plurality of main graphs with different graph sizes;
carrying out graph size classification on all main graphs in the test layout to form a first main graph set and a second main graph set;
screening a main figure from the first main figure set and/or the second main figure set, carrying out multiple times of optical proximity correction on the main figure, and recording the edge placement error of the main figure after each time of optical proximity correction on the main figure;
determining the number of loop iterations of the optical proximity correction executed by the main graph when the edge placement error of the main graph subjected to the optical proximity correction for multiple times does not change within a preset range;
taking the determined cycle iteration number as a target cycle iteration number of optical proximity correction to be performed on the main graph in the first main graph set or the second main graph set containing the main graph subjected to optical proximity correction for multiple times, and performing optical proximity correction of the target cycle iteration number on each main graph in the first main graph set and the second main graph set, wherein the target cycle iteration number of optical proximity correction to be performed on the main graph in the first main graph set is larger than the target cycle iteration number of optical proximity correction to be performed on the main graph in the second main graph set;
the method comprises the following steps of carrying out graph size classification on all main graphs in the test layout to form a first main graph set and a second main graph set, wherein the steps comprise:
determining the graph size of each main graph in the test layout, and forming a first main graph set by using all main graphs of which the graph size is smaller than a graph size threshold; and forming the second main pattern set by using all the main patterns of which the pattern sizes of the main patterns in the test layout are not smaller than the pattern size threshold.
2. The optical proximity correction method according to claim 1, wherein the pattern size threshold has a value range of: 250nm to 350 nm.
3. The optical proximity correction method according to claim 1, wherein the pattern size includes a line width or a pitch of the pattern.
4. The optical proximity correction method of claim 1, wherein the predetermined range of the edge placement error of the main graphics in the first main graphics set is: -1nm to 1 nm.
5. The method as claimed in claim 1, wherein the predetermined range of the edge placement error of the main graphics in the second main graphics set is: -2nm to 2 nm.
6. An optical proximity correction apparatus, comprising:
the test layout determining module is used for determining a test layout corresponding to the prefabricated layout, and the test layout is provided with a plurality of main graphs with different graph sizes;
the graph set forming module is used for carrying out graph size classification on all main graphs in the test layout so as to form a first main graph set and a second main graph set;
the first optical proximity correction module is used for screening out a main graph from the first main graph set and/or the second main graph set, carrying out multiple optical proximity corrections on the main graph, and recording the edge placement error of the main graph after each optical proximity correction on the main graph;
the system comprises a cycle iteration number determining module, a calculating module and a calculating module, wherein the cycle iteration number determining module is used for determining the cycle iteration number of the optical proximity correction executed by the main graph when the edge placement error of the main graph subjected to the optical proximity correction for multiple times does not change in a preset range;
the second optical proximity correction module is used for taking the determined cycle iteration number as a target cycle iteration number of optical proximity correction to be carried out on the main graph in the first main graph set or the second main graph set containing the main graph which is subjected to optical proximity correction for multiple times, and carrying out optical proximity correction on the target cycle iteration number on each main graph in the first main graph set and the second main graph set, wherein the target cycle iteration number of optical proximity correction to be carried out on the main graph in the first main graph set is greater than the target cycle iteration number of optical proximity correction to be carried out on the main graph in the second main graph set;
wherein the graphics set forming module comprises:
the first main pattern set forming unit is used for determining the pattern size of each main pattern in the test layout and forming a first main pattern set by all the main patterns of which the pattern size is smaller than a pattern size threshold;
and the second main pattern set forming unit is used for forming the second main pattern set by all the main patterns of which the pattern sizes of the main patterns in the determined test layout are not smaller than the pattern size threshold.
7. An electronic device is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing mutual communication by the memory through the communication bus;
a memory for storing a computer program;
a processor for implementing the optical proximity correction method according to any one of claims 1 to 5 when executing a program stored in a memory.
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