JP2008040294A - Verification method for mask layout figure and optical image - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid generation of a pseudo error and to efficiently extract only an error by a simplified verification method of verification figures according to the characteristics of deviation occurring in the figures relating to a verification method for a mask layout figure and an optical image. <P>SOLUTION: Each vertex of a mask layout figure 1 is classified into at least tips, corners and minute level difference; the mask layout figure 1 and an optical image 2 by optical simulation are compared with each other; and only a projection or a recess is validated at a tip, only a constricted portion is verified in a corner, and only deviation from a dimension of the mask layout figure is verified in a minute level difference. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for verifying a mask layout graphic and an optical image, and in particular, a simple algorithm is used to verify the difference between the mask layout graphic and the optical image in the previous stage of performing optical proximity effect correction or process correction on the mask layout graphic. The present invention relates to a method for verifying a mask layout figure and an optical image, which is characteristic in a technique for performing and avoiding the occurrence of a pseudo error.

  When a mask layout figure, which is a circuit diagram of a semiconductor device, is transferred onto a wafer by an optical exposure machine such as a stepper, the physical pattern shape formed (resolved) on the wafer due to various optical factors There is a divergence.

  Along with the progress of miniaturization of semiconductor integrated circuit devices, a decrease in pattern size controllability and a deformation of pattern shape due to such a divergence cause a decrease in yield in the manufacture of advanced semiconductor integrated circuit devices.

  Therefore, in order to reduce such divergence and avoid problems after transfer in advance and improve the yield, it is necessary to correct the optical layout effect of the mask layout figure or to correct the process. It is necessary to obtain the physical pattern shape after the wafer transfer as an optical image by optical simulation and to compare and verify the deviation between the optical image and the mask layout figure (for example, see Patent Document 1 or Patent Document 2).

Here, a conventional mask layout figure and simulation optical image verification method will be described with reference to FIG.
See FIG.
FIG. 9 is an explanatory diagram of a conventional mask layout graphic and a simulation optical image. As shown in the upper diagram, when an optical simulation is performed on the mask layout graphic 50, an optical image 60 is obtained.

  In this case, the optical image 60 is inevitably rounded at the corners 51 to 53 of the mask layout graphic 50, and the backward divergence 54 occurs at the corners 51 and 53 of the mountain folds. At 52, an expansion divergence 55 inevitably occurs.

  Further, the optical image 60 shown in the lower stage has a backward deviation 56 at the tip, an expansion deviation 57 at the side of the line, or a backward deviation 58, as compared with the ideal optical image 61 shown in the middle figure.

Therefore, in the verification method of the mask layout and the simulation optical image, it is necessary to verify the above-described various divergences in advance, but if the comparison verification between the mask layout figure 50 and the optical image 60 is performed as it is, as described above,
a. Optically inevitable deviations at corners, that is, a large amount of pseudo errors are detected, which is impractical.

On the other hand, when performing verification ignoring the divergence of the corner to avoid a pseudo error,
b. Neck that tends to occur near corners cannot be detected,
c. By treating corners and minute steps equally without distinguishing them, errors near minute steps cannot be detected.
JP 2004-054052 A JP 2005-017551 A

  As described above, when the divergence between the mask layout figure, which is a two-dimensional geometric figure, and the optical image is verified, optically inevitable pseudo errors and unavoidable actual errors are mixed, but verification accuracy so as not to miss small divergences. If the error rate is increased, many pseudo errors are picked up. On the other hand, if the accuracy is lowered, there is a risk of overlooking the actual error. This situation will be described with reference to FIG.

See FIG.
FIG. 10 is an explanatory diagram of problems in comparison verification between a mask layout figure and an optical image. As shown in the upper diagram, when the verification accuracy is increased so as not to miss even a small deviation, the backward deviation 54 and expansion of the corners 51 to 53 are illustrated. There is a problem that the divergence 55, that is, a pseudo error is detected as an error.

  On the other hand, as shown in the figure below, when the accuracy is lowered, the pseudo errors at the corners 51 to 53 are not detected, but the backward deviation 56 at the tip, the constriction 59 likely to occur near the corner, or the backward deviation at the side of the line There is a problem that an actual error such as 58 is not detected.

  Accordingly, an object of the present invention is to avoid the generation of pseudo errors and efficiently extract only errors by a simplified verification method in which verification is performed according to characteristics of divergence occurring in each.

FIG. 1 is a block diagram showing the principle of the present invention, and means for solving the problems in the present invention will be described with reference to FIG.
In order to solve the above problems, the present invention classifies each vertex of the mask layout graphic 1 into at least a tip, a corner, and a minute step in the mask layout graphic and optical image verification method, and mask layout Compare figure 1 with optical image 2 by optical simulation to verify only protrusion and retraction at the tip, only constriction at the corner, and only deviation from the dimensions of mask layout figure 1 at the minute step. It is characterized by.

  In this way, the mask layout figure 1 is classified into a tip, a corner, a minute step, and the like, and according to the characteristics of the divergence that occurs in each, only the protrusion and retraction at the tip, only the constriction at the corner, and In the case of a minute step, it is possible to avoid detection of the pseudo error 7 and efficiently extract only the error by simplifying the verification so that only the deviation from the dimension of the mask layout figure 1 is verified. Become.

  In this case, in the verification of the divergence, the tip auxiliary graphic 3 that defines the allowable amount of protrusion and retraction of the tip, the contour auxiliary graphic 4 that defines the allowable amount of dimensional deviation, the protruding and retracted position of the tip, and the constriction risk area It is desirable to combine the dangerous area auxiliary figure 5 defining

  Thus, highly accurate verification is possible by combining the auxiliary figures 3 to 5 in which the allowable amount is defined according to the characteristics of the divergence occurring in each.

  Further, in the verification of the divergence using the various auxiliary figures 3 to 5, the verification error 6 is caused by the graphic logic operation using only the AND / OR by the combination of the layout figure 1, the optical image 2, and the various auxiliary figures 3 to 5. By extracting, the logical operation for verification becomes very simple, and verification can be performed in a short time.

  In this case, in the verification of the divergence, it is desirable to verify the divergence while ignoring the corner portion defined in advance based on the minimum line width rule, so that the detection of the pseudo error 7 can be avoided.

  Further, it is desirable that a correction auxiliary pattern is generated based on the verification error 6 detected by the above-described mask layout figure and optical image verification method, and re-verification is performed by optical simulation incorporating the correction auxiliary pattern. The mask layout figure 1 optimum for exposure can be easily created.

  Further, based on the verification error 6 detected by the above-described mask layout graphic and optical image verification method, re-verification may be performed by changing the process conditions in the optical simulation, thereby correcting the mask layout graphic 1. The optical image 2 close to the ideal can be transferred onto an exposed substrate such as a semiconductor wafer.

  According to the present invention, it is possible to simplify the verification method by performing verification according to the characteristics of the generated divergence, thereby avoiding detection of a pseudo error and efficiently only the actual error. It is possible to extract well.

  The present invention classifies each vertex of a mask layout figure into at least a tip, a corner, and a minute step, compares the mask layout figure and an optical image obtained by optical simulation by a graphic logic operation using only AND / OR, In the above, only the protrusion and retraction are verified using the tip auxiliary figure that defines the allowable amount of protrusion and retraction of the tip, and the risk area auxiliary figure that defines the constriction danger area and the protrusion and retraction position of the tip is used in the corner. Only the constriction is verified, and for minor steps, only the deviation from the dimensions of the mask layout figure is verified using an auxiliary contour figure that defines the allowable amount of dimensional deviation, and pre-defined based on the minimum line width rule The deviation is verified by ignoring the corners and minute steps.

Here, with reference to FIG. 2 thru | or FIG. 6, the verification method of the mask layout figure and optical image of Example 1 of this invention is demonstrated.
See Figure 2
FIG. 2 is an explanatory diagram for identifying the tip and corner of the vertex in the mask layout figure. When the minimum line width rule is 90 nm, the upper end of the end in the major axis direction of the L-shaped linear pattern is shown in FIG. As shown in
W ₁ <0.2 μm
H ₁ > 0.2 μm
H ₂ > 0.2 μm
Only if all the conditions of

On the other hand, as shown in the middle diagram,
W ₂ ≧ 0.2μm
H ₂ ≧ 0.2μm
If the condition is met, it is certified as a corner.
In addition,
W ₂ ≧ 0.2μm
H ₂ <0.2 μm
In this case, H ₂ is recognized as the tip.

Also, for the mountain folds of the L-shaped linear pattern, as shown in the lower figure, if the figure is reversed on the Y axis and rotated 90 °, it becomes equivalent to the left figure.
W ₁ ≧ 0.2μm
H ₂ ≧ 5nm
If the conditions are met, it is recognized as a corner.
In addition,
W ₁ ≧ 0.2μm
H ₁ <0.2 μm
In this case, H ₁ is recognized as the tip.

See Figure 3
FIG. 3 is an explanatory diagram for identifying the corners of the vertices and the minute steps in the mask layout figure. When the minimum line width rule is 90 nm, the valley folds of the L-shaped linear pattern are shown in the upper diagram. H ₁ and H ₂ are not facing each other, and
W ₃ ≧ 5nm
If the condition is met, it is certified as a corner.

On the other hand, as shown in the figure below, H ₁ and H ₂ are not facing each other, and
W ₃ <5nm
If the condition is satisfied, it is recognized as a small step.

See Figure 4
FIG. 4 is an explanatory diagram of the auxiliary graphic, and an optical image 20 is obtained by optical simulation with respect to the mask layout graphic 10 shown in the upper part.
On the other hand, with respect to the mask layout figure 10, the tip auxiliary figure 11 is generated based on the tip allowable intersection for the portion recognized as the tip portion, and the width allowable intersection is provided for the portion recognized as the corner and the minute step. The contour auxiliary figure 12 is generated based on the above.

Further, a dangerous area auxiliary graphic 13 for verifying the constricted portion is generated.
Specifically, a dangerous area auxiliary graphic 13 is formed by a center line having a predetermined width with respect to the mask layout graphic 10, and both end portions of the dangerous area auxiliary graphic 13 are in contact with the inner edge of the tip auxiliary graphic 11. .

  Incidentally, when the minimum line width rule is 90 nm, for example, the allowable width of the tip auxiliary graphic 11, the contour auxiliary graphic 12, and the dangerous area auxiliary graphic 13 is 10 μm.

See Figure 5
FIG. 5 is an explanatory diagram of a specific verification method. First, as shown in the upper diagram, in order to detect the backward deviation of the constricted portion of the tip,
a. An AND graphic logic operation is performed on the optical image 20 (B) and the dangerous area auxiliary graphic 13 (D).
As a result of the AND logic operation, if the figure does not match as shown at the right end, '0' is output and it is detected as a backward divergence error. 0 'is output and detected as a backward deviation error.

Next, in order to detect the backward divergence other than the corner of the corner and the portion recognized as the minute step, as shown in the middle diagram,
b. After performing an OR graphic logic operation on the optical image 20 (B), the tip auxiliary figure 11 (C ₁ ) and the contour auxiliary figure 12 (C ₂ ) to obtain an OR auxiliary figure (B + C),
c. An AND graphic logic operation is performed on the OR auxiliary graphic (B + C) and the mask layout graphic 10 (A).

As a result of AND graphic logic operation, if the figures do not match like the lower right part and the right part of the minute step, '0' is output and detected as a backward deviation error.
Note that “0” is also output in the corner portion, but this is an optically unavoidable pseudo error, and therefore, the “0” output in the region recognized as a corner in the above definition of the corner is ignored. .

Next, in order to detect the expansion divergence other than the corner portion of the corner and the portion recognized as the minute step, as shown in the lower diagram,
d. After performing an OR graphic logic operation on the mask layout graphic 10 (A), the tip auxiliary graphic 11 (C ₁ ), and the contour auxiliary graphic 12 (C ₂ ) to obtain an OR auxiliary graphic (A + C),
c. An AND graphic logic operation is performed on the OR auxiliary graphic (A + C) and the optical image 20 (B).

As a result of AND graphic logic operation, if the figures do not match like the left part and the left part of the small step, '0' is output and detected as an expansion divergence error.
In this case, “0” may be output at the corner portion of the valley fold, but this is also an optically unavoidable pseudo error. Ignore '0' output.

See FIG.
FIG. 6 is an explanatory diagram of the verification result. The backward deviation error 31 is at the right end, the backward deviation error 32 is at the lower right, the backward deviation error 33 is at the constricted part, and the backward deviation is at the right part of the minute step. The error 34 was detected as an expansion divergence error 35 at the left part of the minute step and an expansion divergence error 36 at the left end part.

  Thus, in Example 1 of the present invention, in order to perform verification according to the characteristics of the generated divergence, each vertex of the mask layout figure is classified into at least a tip, a corner, and a minute step, The verification can be simplified, it is possible to avoid the false error 37 being erroneously detected, and it is possible to efficiently extract only the actual error.

  In addition, a tip auxiliary figure defining the allowable amount of protrusion and retraction of the tip is generated at the tip, and a danger area auxiliary figure defining the protrusion and retreat position of the tip and the constriction risk area is generated at the corner, In the straight line part other than the above, the contour auxiliary figure defining the allowable amount of dimensional deviation is generated. It is possible to accurately detect errors in the constricted portion, and dimensional deviation errors in minute steps and linear portions other than those described above.

Next, with reference to FIG. 7, a mask layout pattern and an optical image verification method according to the second embodiment of the present invention will be described.
See FIG.
FIG. 7 is a flowchart of the mask layout figure and optical image verification method of the second embodiment of the present invention. First, in the procedure of the first embodiment,
α. Define tips, corners, minute steps, etc. Then
β. A tip auxiliary figure that defines the allowable amount of protrusion and retraction of the tip with respect to the tip, a dangerous area auxiliary figure that defines the protrusion and retraction position of the tip and the constriction danger area with respect to the corner, the other straight part and the minute For the step, a contour auxiliary figure defining the allowable amount of dimensional deviation is generated.

Then
γ. By the graphic logic operation using only AND / OR, the error of the protrusion and retreat of the tip, the error in the constricted part of the corner, and the deviation error of the dimension in the minute step and the straight part other than the above are detected. Then
δ. For each detected error, a correction assist pattern is generated for the mask layout graphic so as to cancel each error.

After that, again,
ε. The above steps α to δ are performed on the mask layout figure corrected by the correction auxiliary pattern, and are repeated until no error is detected.

Next, with reference to FIG. 8, a method for verifying a mask layout figure and an optical image according to the third embodiment of the present invention will be described.
See FIG.
FIG. 8 is a flowchart of the mask layout figure and optical image verification method according to the third embodiment of the present invention. First, in the procedure of the first embodiment,
α. Define tips, corners, minute steps, etc. Then
β. A tip auxiliary figure that defines the allowable amount of protrusion and retraction of the tip with respect to the tip, a dangerous area auxiliary figure that defines the protrusion and retraction position of the tip and the constriction danger area with respect to the corner, the other straight part and the minute For the step, a contour auxiliary figure defining the allowable amount of dimensional deviation is generated.

Then
γ. By the graphic logic operation using only AND / OR, the error of the protrusion and retreat of the tip, the error in the constricted part of the corner, and the deviation error of the dimension in the minute step and the straight part other than the above are detected.

Then
δ ′. For each detected error, process conditions in the optical simulation are changed so as to cancel each error, and a corrected optical image is generated.
The process conditions in this case are exposure wavelength, exposure intensity, resist photosensitivity, and the like.

After that, again,
ε ′. The steps α to δ ′ are performed using the optical image obtained by the optical simulation with the process conditions changed, and are repeated until no error is detected.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the conditions, numerical values, and the like described in the above embodiments, and various modifications can be made. The line width of 10 μm of each auxiliary figure in Example 1 is merely an example, and may be appropriately changed based on experiments according to the minimum line width rule, the photosensitive sensitivity of the resist to be used, and the like.

  In the second and third embodiments, the correction is performed only by correcting the mask layout graphic or the process condition. However, the correction is made by combining the correction of the mask layout graphic and the correction of the process condition. Needless to say, it may be eliminated.

  Further, although not mentioned in each of the above-described embodiments, for the backward divergence and the expansion divergence that inevitably occur in the corner portion, a correction assist pattern that cancels the backward divergence or the expansion divergence as in the past is used. It is generated and corrected.

Here, the detailed features of the present invention will be described again with reference to FIG.
See Figure 1 again
(Additional remark 1) Each vertex of the mask layout figure 1 is classified into at least a tip, a corner, and a minute step, and the mask layout figure 1 is compared with the optical image 2 by optical simulation. A method for verifying a mask layout graphic and an optical image, characterized by verifying only a constriction at a corner and only a deviation from a dimension of the mask layout graphic 1 at a minute step.
(Supplementary Note 2) In the verification of the divergence, the tip auxiliary graphic 3 that defines the allowable amount of protrusion and retraction of the tip, the contour auxiliary graphic 4 that defines the allowable amount of dimensional deviation, and the protrusion and retraction of the tip The mask layout graphic and the optical image verification method according to appendix 1, wherein a dangerous area auxiliary graphic 5 defining a position and a constricted dangerous area is combined.
(Supplementary Note 3) In the verification of the divergence using the various auxiliary figures 3 to 5, the graphic logic using only the AND / OR by the combination of the layout figure 1, the optical image 2, and the various auxiliary figures 3 to 5 3. A method for verifying a mask layout figure and an optical image according to appendix 2, wherein a verification error 6 is extracted by calculation.
(Supplementary Note 4) In the verification of the divergence, the mask layout figure according to any one of the supplementary notes 1 to 3, wherein the divergence is verified while ignoring a corner portion defined in advance based on a minimum line width rule. And optical image verification method.
(Supplementary Note 5) A correction auxiliary pattern is generated based on the verification error 6 detected by the mask layout figure and the optical image verification method according to any one of Supplementary notes 1 to 4, and the optical simulation is performed by incorporating the correction auxiliary pattern. A mask layout figure and an optical image verification method characterized by performing re-verification.
(Additional remark 6) Based on the verification error 6 detected by the mask layout figure of any one of Additional remarks 1 thru | or 4, and the verification method of an optical image, it re-verifies by changing the process conditions in optical simulation. The mask layout figure and optical image verification method.

  As a practical example of the present invention, a verification process for an exposure process of a semiconductor integrated circuit device is typical. However, the present invention is not limited to a semiconductor integrated circuit device, but an active matrix substrate, a superconducting device, a magnetoresistive device. The present invention is also applied to an exposure process accompanying an etching process or an ion implantation process of an effect element or another electronic device such as a ferroelectric device.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the identification reference | standard of the front-end | tip and corner of a vertex in a mask layout figure. It is explanatory drawing of the identification reference | standard of the corner of a vertex and a micro level | step difference in a mask layout figure. It is explanatory drawing of an auxiliary figure. It is explanatory drawing of the specific verification method. It is explanatory drawing of a verification result. It is a flowchart of the verification method of the mask layout figure and optical image of Example 2 of this invention. It is a flowchart of the verification method of the mask layout figure and optical image of Example 3 of this invention. It is explanatory drawing of the conventional mask layout figure and a simulation optical image. It is explanatory drawing of the problem in the comparison verification of a mask layout figure and an optical image.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Mask layout figure 2 Optical image 3 Tip auxiliary figure 4 Contour auxiliary figure 5 Hazardous area auxiliary figure 6 Verification error 7 Pseudo error 10 Mask layout figure 11 Tip auxiliary figure 12 Contour auxiliary figure 13 Hazardous area auxiliary figure 20 Optical images 31-34 Backward Deviation error 35 Expansion deviation error 36 Expansion deviation error 37 Pseudo error 50 Mask layout figure 51-53 Corner part 54 Backward deviation 55 Expansion deviation 56 Backward deviation 57 Expansion deviation 58 Backward deviation 59 Constriction 60 Optical image 61 Ideal optical image

Claims (5)

Each vertex of the mask layout figure is classified into at least a tip, a corner, and a minute step, and the mask layout figure is compared with an optical image obtained by optical simulation, and only protrusion or retraction at the tip and only constriction at the corner. A method for verifying a mask layout graphic and an optical image, wherein only a deviation from the dimension of the mask layout graphic is verified at a minute step. In the verification of the divergence, the tip auxiliary figure defining the allowable amount of protrusion or retraction of the tip, the contour auxiliary figure defining the allowable amount of dimensional deviation, the protruding or retracting position of the tip, and the constriction risk area 2. The mask layout graphic and optical image verification method according to claim 1, wherein the defined dangerous area auxiliary graphic is combined. In verification of divergence using the various auxiliary figures, a verification error is extracted by a graphic logic operation using only AND / OR based on a combination of the mask layout figure, the optical image, and the various auxiliary figures. A method for verifying a mask layout figure and an optical image according to claim 2. A correction auxiliary pattern is generated based on a verification error detected by the mask layout figure and optical image verification method according to any one of claims 1 to 3, and re-verification is performed by an optical simulation incorporating the correction auxiliary pattern. A method for verifying a mask layout figure and an optical image, characterized in that: A mask characterized by performing re-verification by changing a process condition in an optical simulation based on a verification error detected by the mask layout figure and the optical image verification method according to any one of claims 1 to 3. Verification method for layout figures and optical images.

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