CN114582744B - 一种高密度铜柱凸点键合互连的方法 - Google Patents

一种高密度铜柱凸点键合互连的方法 Download PDF

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CN114582744B
CN114582744B CN202210154507.7A CN202210154507A CN114582744B CN 114582744 B CN114582744 B CN 114582744B CN 202210154507 A CN202210154507 A CN 202210154507A CN 114582744 B CN114582744 B CN 114582744B
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凌云志
马建国
李朋飞
胡川
陈志涛
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Abstract

本发明公开了一种高密度铜柱凸点键合互连的方法,属于芯片封装领域。本发明所述方法创造性地在铜柱凸点阵列中引入铜‑焊料嵌段纳米线结构代替传统的焊料结构作为键合结构,使其在低温低压条件下即可实现铜柱凸点的键合互连,其生成的互连微结构也具有更高的可靠性,也不会在器件中产生热应力,且可以避免由于焊料的过度溢出、服役过程中的焊料生长或柯肯达尔孔洞形成等问题造成芯片的短路及可靠性问题,实现高密度键合互连;所述方法基于基板电镀方式,可实现一次连续铜柱凸点、嵌段纳米线的合成及键合互连,操作工艺简单,可工业化规模实施。

Description

一种高密度铜柱凸点键合互连的方法
技术领域
本发明涉及芯片封装领域,具体涉及一种高密度铜柱凸点键合互连的方法。
背景技术
微凸点互连技术主要应用于倒装、晶圆级封装以及2.5D/3D封装中,随着微凸点和微组装技术的发展,为提高2.5D/3D堆叠封装的集成度,微凸点尺寸和节距需要不断缩小。
现阶段,小尺寸细节距的芯片间微凸点互连技术主要采用铜柱加锡帽实现键合互连,其工艺步骤主要涉及铜柱制备、钎料沉积以及热压回流等,这些工艺相互独立且非常繁琐,无法一体化快速完成;而且所述键合互连过程中涉及的高温高压环境会使得器件产生热应力,影响器件的可靠性。
为解决上述问题,急需开发出一种低温低压的铜柱凸点键合互连的方法。
发明内容
基于现有技术的不足,本发明的目的在于提供了一种高密度铜柱凸点键合互连的方法,该方法在高密度铜柱凸点上生长嵌段纳米线,经过预处理后以嵌段纳米线代替传统的焊料结构作为键合结构,在较低温低压条件下完成铜柱凸点的高强度键合互连,该方法操作步骤简单,且实施过程中不会使得器件产生热应力,可靠性高。
为了达到上述目的,本发明采取的技术方案为:
一种高密度铜柱凸点键合互连的方法,包括以下步骤:
(1)在硅基板器件上镀上种子层;
(2)在种子层上设置光刻胶层,经曝光显影处理至暴露出铜柱凸点的生长位点后,在光刻胶层表面设置纳米线生长模板;
(3)在铜柱凸点的生长位点内电镀填充铜柱,并随后在纳米线生长模板内依次电镀铜纳米线和焊料金属纳米线,生成铜-焊料嵌段纳米线;
(4)依次去除纳米线生长模板、光刻胶层和种子层,经还原剂还原处理后,得含有铜-焊料嵌段纳米线的高密度铜柱凸点阵列;
(5)将所述铜-焊料嵌段纳米线的高密度铜柱凸点阵列与另一具有类似结构的器件对位并令嵌段纳米线间发生键合互连,使得高密度铜柱凸点阵列与器件上的铜柱凸点间形成金属间化合物。
本发明所述高密度铜柱凸点键合互连的方法创造性地在铜柱凸点阵列中引入铜-焊料嵌段纳米线结构代替传统的焊料结构作为键合结构,由于该结构的纳米尺寸带来的低熔点及高表面活性,可在低于同质焊料熔点的温度条件下即可实现铜柱凸点的键合互连,其生成的互连微结构也具有更高的可靠性,且在其超小尺寸,超细节距的铜凸点下,可以避免由于焊料的过度溢出、服役过程中的焊料生长或柯肯达尔孔洞形成等问题造成芯片的短路及可靠性问题,实现高密度键合互连;所述方法基于基板电镀方式,可实现一次连续铜柱凸点、嵌段纳米线的合成及键合互连,操作工艺简单,可工业化规模实施。
优选地,步骤(1)所述种子层包括铜种子层和银种子层。
优选地,步骤(2)所述纳米线生长模板通过热压法设置在光刻胶层上。
优选地,步骤(2)所述纳米线生长模板为多孔膜,所述多孔膜上的孔洞为纳米尺寸圆形孔洞。
通过上述方式设置特定的多孔膜生长模板,可在铜柱凸点生长位点上一次性连续完成铜柱凸点和垂直的嵌段纳米线的合成。
优选地,所述焊料包括单质金属、二元合金、三元合金中的至少一种;更优选地,所述焊料中包含锡、铟、镓中的至少一种。
根据实际情况需求,本领域技术人员可选择不同的焊料实施本发明所述铜柱凸点的键合互连。
优选地,步骤(3)所述铜-焊料嵌段纳米线为微米级别长度的纳米线,所述纳米线的直径为纳米级别。
优选地,步骤(4)所述还原剂包括甲酸、氢气中的至少一种;所述还原处理为蒸汽处理。
通过还原剂表面处理,可有效去除铜柱或嵌段纳米线表面生成的氧化物杂质,进而提高本发明所述键合互连的可靠性。
优选地,步骤(4)与步骤(5)间还包括步骤(4.1):所述含有铜-焊料嵌段纳米线的高密度铜柱凸点阵列还经过回流处理。
在进行键合互连前进行回流处理可进一步有助于最终金属间化合物的形成。
优选地,步骤(5)所述具有类似结构的器件为经步骤(1)~(4)制备的另一含有铜-焊料嵌段纳米线的高密度铜柱凸点阵列。
优选地,步骤(5)所述键合互连在真空环境或气氛保护环境下进行。
在上述环境下进行可避免铜柱或嵌段纳米线再次被氧化。
本发明的另一目的在于提供所述高密度铜柱凸点键合互连的方法在芯片封装中的应用。
本发明所述高密度铜柱凸点键合互连的方法高效连续,经处理后的铜柱键合互连程度高,可靠性强,尤其适用于芯片间的微凸点互连上。
本发明的有益效果在于:本发明提供了一种高密度铜柱凸点键合互连的方法,该方法创造性地在铜柱凸点阵列中引入铜-焊料嵌段纳米线结构代替传统的焊料结构作为键合结构,使其在低温低压条件下即可实现铜柱凸点的键合互连,其生成的互连微结构也具有更高的可靠性,也不会在器件中产生热应力,且可以避免由于焊料的过度溢出、服役过程中的焊料生长或柯肯达尔孔洞形成等问题造成芯片的短路及可靠性问题,实现高密度键合互连;所述方法基于基板电镀方式,可实现一次连续铜柱凸点、嵌段纳米线的合成及键合互连,操作工艺简单,可工业化规模实施。
附图说明
图1为本发明高密度铜柱凸点键合互连的方法中制备含有铜-焊料嵌段纳米线的高密度铜柱凸点阵列的工艺流程图;
图2为本发明高密度铜柱凸点键合互连的方法中含有铜-焊料嵌段纳米线的高密度铜柱凸点阵列实施键合互连时的流程示意图。
具体实施方式
若无特别说明,本发明实施例中所用原料均购自市场。
为了更好地说明本发明的目的、技术方案和优点,下面将结合具体实施例对本发明作进一步说明,其目的在于详细地理解本发明的内容,而不是对本发明的限制。
实施例1
一种高密度铜柱凸点键合互连的方法,包括以下步骤:
(1)在硅基板器件上镀上一层银种子层;
(2)在种子层上旋涂上一层光刻胶,经曝光显影处理至暴露出设计的铜柱凸点的生长位点后,在光刻胶层表面热压一层纳米线生长模板;所述纳米线生长模板为聚碳酸酯多孔膜,通过该膜层的厚度及孔径大小确定生长的纳米线的微米级长度及纳米级直径;
(3)在铜柱凸点的生长位点内以硫酸铜电解液电镀填充铜柱,并随后在纳米线生长模板内以硫酸铜电解液继续电镀铜纳米线,当铜纳米线的高度仍低于多孔膜高度时停止电镀,随后以硫酸亚锡电解液在多孔膜中电镀生成锡纳米线,并最终生成铜-锡嵌段纳米线,待纳米线高度生长至多孔膜顶部时停止;
(4)依次去除纳米线生长模板(将样品浸入二氯甲烷溶液中溶解所述聚碳酸酯多孔膜,随后洗涤干燥)、光刻胶层(将样品浸入丙酮溶液中溶解所述光刻胶,随后洗涤干燥)和种子层(将样品采用银刻蚀剂(氨水与双氧水等比例配制)去除所述种子层,随后洗涤干燥),以甲酸作为还原剂对样品进行蒸汽处理以去除铜柱和铜-锡嵌段纳米线上的氧化物后,得含有铜-锡嵌段纳米线的高密度铜柱凸点阵列,如图1所示;
(5)在真空环境下,将所述铜-焊料嵌段纳米线的高密度铜柱凸点阵列与另一具有相同结构的高密度铜柱凸点阵列对位并加温(150~235℃)加压(20~100MPa)令嵌段纳米线间发生键合互连,使得高密度铜柱凸点阵列与器件上的铜柱凸点间形成金属间化合物,最后在铜柱凸点间注入填充料以保护内部结构及增强整体结构强度,如图2所示。
最后所应当说明的是,以上实施例仅用以说明本发明的技术方案而非对本发明保护范围的限制,尽管参照较佳实施例对本发明作了详细说明,本领域的普通技术人员应当理解,可以对本发明的技术方案进行修改或者等同替换,而不脱离本发明技术方案的实质和范围。

Claims (3)

1.一种高密度铜柱凸点键合互连的方法,其特征在于,包括以下步骤:
(1)在硅基板器件上镀上种子层;
(2)在种子层上设置光刻胶层,经曝光显影处理至暴露出铜柱凸点的生长位点后,在光刻胶层表面设置纳米线生长模板;所述纳米线生长模板通过热压法设置在光刻胶层上;所述纳米线生长模板为多孔膜,所述多孔膜上的孔洞为纳米尺寸圆形孔洞;
(3)在铜柱凸点的生长位点内电镀填充铜柱,并随后在纳米线生长模板内依次电镀铜纳米线和焊料金属纳米线,生成铜-焊料嵌段纳米线;所述焊料中包含锡、铟、镓中的至少一种;所述铜-焊料嵌段纳米线为微米级别长度的纳米线,所述纳米线的直径为纳米级别;
(4)依次去除纳米线生长模板、光刻胶层和种子层,经还原剂还原处理后,得含有铜-焊料嵌段纳米线的高密度铜柱凸点阵列;所述还原剂包括甲酸、氢气中的至少一种;所述还原处理为蒸汽处理;所述含有铜-焊料嵌段纳米线的高密度铜柱凸点阵列还经过回流处理;
(5)将所述铜-焊料嵌段纳米线的高密度铜柱凸点阵列在真空环境或气氛保护下与另一具有类似结构的器件对位并令嵌段纳米线间在150~235℃、20~100MPa下发生键合互连,使得高密度铜柱凸点阵列与器件上的铜柱凸点间形成金属间化合物;所述具有类似结构的器件为经步骤(1)~(4)制备的另一含有铜-焊料嵌段纳米线的高密度铜柱凸点阵列。
2.如权利要求1所述高密度铜柱凸点键合互连的方法,其特征在于,步骤(1)所述种子层包括铜种子层和银种子层。
3.如权利要求1~2任一项所述高密度铜柱凸点键合互连的方法在芯片封装中的应用。
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