CN114503284A - 半导体元件和半导体装置 - Google Patents
半导体元件和半导体装置 Download PDFInfo
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- CN114503284A CN114503284A CN202080069872.7A CN202080069872A CN114503284A CN 114503284 A CN114503284 A CN 114503284A CN 202080069872 A CN202080069872 A CN 202080069872A CN 114503284 A CN114503284 A CN 114503284A
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- metal layer
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
一种半导体元件,其至少包含层叠结构体,所述层叠结构体通过在由氧化物半导体膜构成的半导体层上层叠第一金属层、第二金属层和第三金属层而成,第一金属层、第二金属层和第三金属层分别由互不相同的一种或两种以上的金属构成,第一金属层和第三金属层之间配置有第二金属层,第二金属层包含Pt或/和Pd,第一金属层与所述半导体层欧姆接触。
Description
技术领域
本发明涉及作为功率器件等有用的半导体元件、使用该半导体元件的半导体装置和半导体系统。
背景技术
氧化镓(Ga2O3)是在室温下具有4.8eV~5.3eV的宽带隙,几乎不吸收可见光和紫外光的透明半导体。因此,特别是在深紫外光线区域中操作的光电子器件和透明电子器件中使用的有前途的材料,近年来,进行基于氧化镓(Ga2O3)的光检测器、发光二极管(LED)和晶体管的开发(参见非专利文献1)。
另外,在氧化镓(Ga2O3)中存在α、β、γ、σ、ε五种晶体结构,一般最稳定的结构是β-Ga2O3。然而,由于β-Ga2O3是β-gallia结构,所以与一般用于电子材料等的晶体系不同,不一定适合用于半导体元件。另外,β-Ga2O3薄膜的生长需要较高的基板温度和较高的真空度,所以也存在制造成本也会增加的问题。另外,如在非专利文献2中也记载的那样,在β-Ga2O3中,就连是高浓度(例如1×1019/cm3以上)的掺杂剂(Si)在离子注入后,如果不在800℃~1100℃的高温下进行退火处理,也不能作为供体使用。
另一方面,α-Ga2O3由于具有与已经通用的蓝宝石基板相同的晶体结构,因此优选用于光电子器件,并且由于α-Ga2O3具有比β-Ga2O3宽的带隙,所以对功率器件特别有用,因此是期待将α-Ga2O3用作半导体的半导体元件的状况。
在专利文献1和2中,记载了如下的半导体元件:将β-Ga2O3用作半导体,作为获得与之适合的欧姆特性的电极,使用由Ti层和Au层构成的两层、由Ti层、Al层和Au层构成的三层或由Ti层、Al层、Ni层和Au层构成的四层。
另外,在专利文献3中,记载了一种半导体元件,该半导体装置将β-Ga2O3用作半导体,作为获得与之适合肖特基特性的电极,使用Au、Pt或者Ni和Au的层叠体中的任一个。
但是,在将专利文献1~3中记载的电极应用于将α-Ga2O3用作半导体的半导体元件的情况下,存在作为肖特基电极或欧姆电极没有起作用、电极没有与膜接合、半导体特性受损等问题。而且,关于专利文献1~3所述的电极结构,会导致从电极端部产生漏电流等,而无法得到作为半导体元件在实际应用上能够满意的电极结构。
特别是近年来,在将氧化镓用作半导体的情况下,Ti/Au被用作欧姆电极(专利文献4~8),虽然显示出良好的密接性,但是在欧姆特性方面还不是足够满意,期待着欧姆特性优异的氧化镓半导体元件。
【专利文献1】日本特开2005-260101号公报
【专利文献2】日本特开2009-81468号公报
【专利文献3】日本特开2013-12760号公报
【专利文献4】日本特开2019-016680号公报
【专利文献5】日本特开2019-036593号公报
【专利文献6】日本特开2019-079984号公报
【专利文献7】日本特开2018-60992号公报
【专利文献8】WO2016-13554
【非专利文献1】Jun Liang Zhao等,“UV and Visible ElectroluminescenceFrom a Sn:Ga2O3/n+-Si Heterojunction by Metal-Organic Chemical VaporDeposition”,IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.58,NO.5MAY 2011
【非专利文献2】Kohei Sasaki等,“Si-Ion Implantation Doping inβ-Ga2O3 andIts Application to Fabrication of Low-Resistance Ohmic Contacts”,AppliedPhysics Express 6(2013)086502
发明内容
本发明的目的是提供一种抑制氧化物半导体的氧等扩散到欧姆电极中,而具有良好的欧姆特性的半导体元件和半导体装置。
本发明人等为了达到上述目的而深入研究,结果发现以往作为欧姆电极使用Ti/Au,但存在Ti扩散的问题,而且,发现在Ti层和Au层之间设置了Ni等防止Ti扩散膜的情况下,在欧姆电极内会产生氧化物半导体的氧扩散的问题,并发现一种半导体元件,其至少包含层叠结构体,所述层叠结构体通过在由氧化物半导体膜构成的半导体层上层叠第一金属层、第二金属层和第三金属层而成,第一金属层、第二金属层和第三金属层分别由互不相同的一种或两种以上的金属构成,第一金属层和第三金属层之间配置有第二金属层,第二金属层包含Pt或/和Pd,第一金属层与所述半导体层欧姆接触,发现这种半导体元件抑制氧化物半导体的氧等的扩散,特别是也抑制欧姆接触的Ti等欧姆金属的扩散,从而发挥良好的欧姆特性。
另外,本发明人在获得上述见解之后,进一步经过反复研究,最终完成了本发明。
即,本发明涉及以下技术方案。
[1]一种半导体元件,其至少包含层叠结构体,所述层叠结构体通过在由氧化物半导体膜构成的半导体层上层叠第一金属层、第二金属层和第三金属层而成,第一金属层、第二金属层和第三金属层分别由互不相同的一种或两种以上的金属构成,第一金属层和第三金属层之间配置有第二金属层,第二金属层包含Pt或/和Pd,第一金属层与所述半导体层欧姆接触。
[2]根据前述[1]所述的半导体元件,其中,所述氧化物半导体膜具有刚玉结构。
[3]根据前述[2]所述的半导体元件,其中,所述氧化物半导体膜的主面为m面。
[4]根据前述[1]~[3]中任一项所述的半导体元件,其中,所述氧化物半导体膜包含氧化镓和/或氧化铱。
[5]根据前述[1]~[4]中任一项所述的半导体元件,其中,所述氧化物半导体膜包含氧化镓。
[6]根据前述[1]~[5]中任一项所述的半导体元件,其中,所述氧化物半导体膜包含掺杂剂。
[7]根据前述[1]~[6]中任一项所述的半导体元件,其中,第一金属层为Ti层或In层。
[8]根据前述[1]~[7]中任一项所述的半导体元件,其中,第三金属层为由选自Au、Ag和Cu中的至少一种或两种以上的金属构成的金属层。
[9]根据前述[1]~[8]中任一项所述的半导体装置,其中,进一步地,与第三金属层接触而配置有多孔层。
[10]根据前述[9]所述的半导体元件,其中,所述多孔层的空隙率为10%以下。
[11]根据前述[9]或[10]所述的半导体元件,其中,所述多孔层包含贵金属。
[12]根据前述[9]~[11]中任一项所述的半导体元件,其中,进一步地,在所述多孔层上配置有基板。
[13]根据前述[1]~[12]中任一项所述的半导体元件,其中,进一步地,包含肖特基电极。
[14]根据前述[13]所述的半导体元件,其中,所述肖特基电极包含Mo和/或Co。
[15]根据前述[13]或[14]中所述的半导体元件,其中,在所述氧化物半导体膜的第一面侧配置有所述肖特基电极,在处于所述第一面侧的相反侧的第二面侧配置有欧姆电极。
[16]根据前述[13]~[15]中任一项所述的半导体元件,其中,所述肖特基电极至少包含第一金属层、第二金属层和第三金属层,该第一金属层、该第二金属层和该第三金属层分别由互不相同的金属构成,在该第一金属层和该第三金属层之间配置有该第二金属层,该第一金属层比该第三金属层更靠近所述半导体层侧。
[17]根据前述[16]所述的半导体元件,其中,所述肖特基电极的第一金属层为Co层或Mo层。
[18]根据前述[16]或[17]所述的半导体元件,其中,所述肖特基电极的第二金属层为Ti层。
[19]根据前述[16]~[18]中任一项所述的半导体元件,其中,所述肖特基电极的第三金属层为Al层。
[20]一种半导体元件,至少具备由氧化物半导体膜构成的半导体层、肖特基电极和欧姆电极,其特征在于,
所述肖特基电极包含Co层或Mo层,
所述欧姆电极至少包含第一金属层、第二金属层和第三金属层,该第一金属层为Ti层或In层,该第二金属层为Pt层或Pd层,该第三金属层为由选自Au、Ag和Cu中的至少一种或两种以上金属构成的金属层。
[21]根据前述[1]~[20]中任一项所述的半导体元件,其中,所述半导体层为n型氧化物半导体层。
[22]根据前述[1]~[21]中任一项所述的半导体元件,其中,所述半导体元件为纵向型器件。
[23]根据前述[1]~[22]中任一项所述的半导体元件,其中,所述半导体元件为功率器件。
[24]一种半导体装置,至少由半导体元件与引线框、电路基板或散热基板利用接合部件接合而构成,其中,所述半导体元件为前述[1]~[23]中任一项所述的半导体元件。
[25]根据前述[24]所述的半导体装置,其中,所述半导体装置为功率模块、逆变器或转换器。
[26]根据前述[24]或[25]所述的半导体装置,其中,所述半导体装置为功率卡。
[27]一种半导体系统,具备半导体元件或半导体装置,所述半导体元件为前述[1]~[23]中任一项所述的半导体元件,所述半导体装置为前述[24]~[26]中任一项所述的半导体装置。
本发明的半导体元件抑制氧化物半导体的氧等扩散到欧姆电极中,而具有良好的欧姆特性。
附图说明
图1是示意性地表示本发明的半导体元件的一优选方式的截面图。
图2是说明图1的半导体元件的优选制造方法的一方式的图。
图3是说明图1的半导体元件的优选制造方法的一方式的图。
图4是说明图1的半导体元件的优选制造方法的一方式的图。
图5是说明图1的半导体元件的优选制造方法的一方式的图。
图6是示意性地表示本发明的半导体元件的一优选方式的截面图。
图7是作为试验例的结果表示截面SEM图像的图,(a)表示通过通常的退火形成由银构成的多孔层的情况,(b)表示进一步进行热压接,而使空隙率为10%以下的多孔层。
图8是示意性地表示电源系统的一优选例子的图。
图9是示意性地表示系统装置的一优选例子的图。
图10是示意性地表示电源装置的电源电路图的一优选例子的图。
图11是示意性地表示半导体装置的一优选例子的图。
图12是示意性地表示功率卡的一优选例子的图。
图13是表示多孔层的空隙率的图。(a)表示通过通常的退火进行接合后的多孔层的空隙率,(b)表示退火后进一步进行一小时热压接时的空隙率。
图14是表示试验例中的烧结后的欧姆电极的一部分外观的照片。(a)是表示使用Ti/Pt/Au作为欧姆电极时的烧结后的外观的照片,(b)是表示使用Ti/Ni/Au作为欧姆电极时的烧结后的外观的照片。
图15是分别表示作为试验例中的欧姆电极,使用Ti/Pt/Au时和使用Ti/Ni/Au时的接触低效率的温度依赖性(烧结温度)的图。
图16是示意性地说明作为本发明的半导体元件的主要部分的层叠结构体的图。
图17是示意性地表示本发明的半导体元件的实施例产品的截面图。
具体实施方式
本发明的半导体元件至少包含层叠结构体,所述层叠结构体通过在由氧化物半导体膜构成的半导体层上层叠第一金属层、第二金属层和第三金属层而成,其特征在于,第一金属层、第二金属层和第三金属层分别由互不相同的一种或两种以上的金属构成,第一金属层和第三金属层之间配置有第二金属层,第二金属层包含Pt或/和Pd,第一金属层与所述半导体层欧姆接触。关于所述层叠结构体,例如,如图16所示,只要在由氧化物半导体膜构成的半导体层101上层叠有第一金属层102a、第二金属层102b和第三金属层102c,就不特别限定。
所述氧化物半导体膜(以下也简称为“半导体层”或“半导体膜”)只要是包含氧化物的半导体膜就不特别限定,在本发明中,优选为包含金属氧化物的半导体膜,更优选为包含结晶性氧化物半导体的半导体膜,最优选为包含结晶性氧化物半导体作为主成分的半导体膜。另外,在本发明中,优选所述结晶性氧化物半导体含有选自元素周期表第9族(例如,钴、钡或铱等)和第13族(例如,铝、镓或铟等)中的一种或两种以上的金属,更优选含有选自铝、铟、镓和铱中的至少一种金属的金属氧化物,最优选至少包含镓或铱。所述结晶性氧化物半导体的晶体结构也不特别限定。作为结晶性氧化物半导体的晶体结构,例如,可举出刚玉结构、β-gallia结构或六方晶结构(例如,ε型结构)等。在本发明中,所述结晶性氧化物半导体优选具有刚玉结构,由于具有刚玉结构,并且主面为m面可以抑制氧等的扩散,还可以使电特性更优异,所以更优选。另外,所述结晶性氧化物半导体也可以具有偏离角。在本发明中,所述半导体膜优选包含氧化镓和/或氧化铱,更优选包含α-Ga2O3和/或α-Ir2O3。此外,“主成分”是指所述结晶性氧化物半导体相对于半导体层的全部成分,优选以原子比计包含50%以上,更优选包含70%以上,进一步优选包含90%以上,且指也可以是100%。另外,所述半导体层的厚度并不特别限定,可以为1μm以下,也可以为1μm以上,在本发明中,优选为1μm以上,更优选为10μm以上。所述半导体膜的表面积并不特别限定,可以为1mm2以上,也可以为1mm2以下,优选为10mm2~300cm2,更优选为100mm2~100cm2。另外,所述半导体膜优选为单晶膜,但也可以为多晶膜或者包含多晶的结晶膜。另外,还优选地,所述氧化物半导体膜为至少包含第一氧化物半导体膜和第二氧化物半导体膜的多层膜的半导体层,在第一氧化物半导体膜上设置有肖特基电极的情况下,所述半导体膜为第一氧化物半导体膜的载流子密度小于第二氧化物半导体膜的载流子密度的多层膜。此外,在这种情况下,至少在第二氧化物半导体膜中通常包含掺杂剂,所述半导体层的载流子密度能够通过调节掺杂量来适当地设定。
优选地,所述半导体层包含掺杂剂。所述掺杂剂并不特别限定,可以为公知的掺杂剂。作为所述掺杂剂,例如可以举出锡、锗、硅、钛、锆、钒或铌等n型掺杂剂或者镁、钙、锌等p型掺杂剂等。在本发明中,所述半导体层优选包含n型掺杂剂,更优选为n型氧化物半导体层。另外,在本发明中,所述n型掺杂剂优选为Sn、Ge或Si。关于掺杂剂的含量,在所述半导体层的组成中,优选为0.00001原子%以上,更优选为0.00001原子%~20原子%,最优选为0.00001原子%~10原子%。更具体而言,掺杂剂的浓度通常可以是约1×1016/cm3~1×1022/cm3,另外还可以将掺杂剂的浓度设为例如约1×1017/cm3以下的低浓度。另外,根据本发明的一方式,还可以以约1×1020/cm3以上的高浓度含有掺杂剂。另外,所述半导体层的固定电荷的浓度也不特别限定,在本发明中为1×1017/cm3以下时,能够通过所述半导体层良好地形成耗尽层,因此优选。
所述半导体层可以使用公知的方法形成。作为所述半导体层的形成方法,例如可以举出CVD法(化学气相沉积法)、MOCVD法(金属有机物气相外延法)、MOVPE法(有机金属气相外延法)、雾化CVD法、雾化外延法、MBE法(分子束外延法)、HVPE法(氢化物气相外延法)、脉冲生长法或ALD法(原子层沉积法)等。在本发明中,所述半导体层的形成方法优选为雾化CVD法或雾化外延法。在前述的雾化CVD法或雾化外延法中,例如通过如下工序来形成所述半导体层:使原料溶液雾化(雾化工序),使液滴飘浮并雾化后,将得到的雾化液滴用载气运送至基体上(运送工序),接着,在所述基体附近使所述雾化液滴进行热反应,从而在基体上层叠包含结晶性氧化物半导体作为主成分的半导体膜(成膜工序)。
(雾化工序)
在雾化工序中,使所述原料溶液雾化。所述原料溶液的雾化方法只要能够雾化所述原料溶液就不特别限定,可以为公知的方法,在本发明中,优选为使用超声波的雾化方法。由于使用超声波得到的雾化液滴的初速度为零,在空中飘浮,因此优选,由于不是像例如喷雾那样进行喷射,而是可飘浮在空间中并作为气体进行运送的雾化液滴(包含雾),所以不会有因碰撞能量导致的损伤,因此非常优选。液滴尺寸并不特别限定,可以是几毫米左右的液滴,优选为50μm以下,更优选为100nm~10μm。
(原料溶液)
所述原料溶液只要能够雾化且包含能够形成半导体膜的原料就不特别限定,可以是无机材料,也可以是有机材料。在本发明中,所述原料优选为金属或金属化合物,更优选包含选自铝、镓、铟、铁、铬、钒、钛、铑、镍、钴和铱中的一种或两种以上的金属。
在本发明中,作为所述原料溶液,能够优选使用使所述金属以络合物或盐的形态溶解或分散到有机溶剂或水中的物质。作为络合物的形态,例如,可举出乙酰丙酮络合物、羰基络合物、氨络合物、氢化物络合物等。作为盐的形态,例如,可以举出有机金属盐(例如金属醋酸盐、金属草酸盐、金属柠檬酸盐等)、硫化金属盐、硝化金属盐、金属磷酸盐、卤化金属盐(例如氯化金属盐、溴化金属盐、碘化金属盐等)等。
另外,优选地,在所述原料溶液中混合氢卤酸或氧化剂等添加剂。作为所述氢卤酸,例如可以举出氢溴酸、氢氯酸、氢碘酸等,其中,出于可更有效地抑制异常粒子的产生的理由,优选氢溴酸或氢碘酸。作为所述氧化剂,例如,可举出过氧化氢(H2O2)、过氧化钠(Na2O2)、过氧化钡(BaO2)、过氧化苯甲酰((C6H5CO)2O2)等过氧化物,次氯酸(HClO)、过氯酸、硝酸、臭氧水、过氧乙酸或硝基苯等有机过氧化物等。
所述原料溶液中还可以包含掺杂剂。通过使原料溶液中包含掺杂剂,从而能够良好地进行掺杂。所述掺杂剂只要不阻碍本发明的目的,就不特别限定。作为所述掺杂剂,例如可以举出锡、锗、硅、钛、锆、钒或铌等n型掺杂剂,或者Mg、H、Li、Na、K、Rb、Cs、Fr、Be、Ca、Sr、Ba、Ra、Mn、Fe、Co、Ni、Pd、Cu、Ag、Au、Zn、Cd、Hg、Ti、Pb、N或P等p型掺杂剂等。所述掺杂剂的含量通过使用校准线来适当设定,所述校准线示出掺杂剂在原料中的浓度相对于期望的载流子密度的关系。
原料溶液的溶剂不特别限定,可以是水等无机溶剂,也可以是醇等有机溶剂,还可以是无机溶剂与有机溶剂的混合溶剂。在本发明中,优选地,所述溶剂包含水,更优选为水或者水与醇的混合溶剂。
(运送工序)
在运送工序中,通过载气将所述雾化液滴运送到成膜室内。作为所述载气,只要不阻碍本发明的目的就不特别限定,例如可以举出氧、臭氧、氮或氩等非活性气体,或者氢气或合成气体等还原气体等作为优选例子。另外,载气的种类可以为一种,也可以为两种以上,还可以进一步将降低了流量的稀释气体(例如10倍稀释气体等)等作为第二载气使用。另外,载气的供给部位也可以不只一处,也可以有两处以上。载气的流量不特别限定,优选为0.01L/分钟~20L/分钟,更优选为1L/分钟~10L/分钟。在有稀释气体的情况下,稀释气体的流量优选为0.001L/分钟~2L/分钟,更优选为0.1L/分钟~1L/分钟。
(成膜工序)
在成膜工序中,通过在所述基体附近使所述雾化液滴进行热反应,从而在基体上形成所述半导体膜。热反应只要利用热使所述雾化液滴发生反应即可,反应条件等也是只要不阻碍本发明的目的,就不特别限定。在本工序中,通常以溶剂的蒸发温度以上的温度进行所述热反应,优选为不过高的温度(例如1000℃)以下,更优选为650℃以下,最优选为300℃~650℃。另外,热反应只要不阻碍本发明的目的,则可以在真空下、非氧气氛下(例如,非活性气体气氛下等)、还原气体气氛下及氧气氛下中的任一气氛下进行,优选在非活性气体气氛下或氧气氛下进行。另外,还可以在大气压下、加压下及减压下中的任一条件下进行,本发明中,优选在大气压下进行。此外,所述半导体膜的膜厚能够通过调整成膜时间来进行设定。
(基体)
所述基体只要能够支撑所述半导体膜,就不特别限定。所述基体的材料也是只要不阻碍本发明的目的,就不特别限定,可以为公知的基体,可以是有机化合物,也可以是无机化合物。作为所述基体的形状,可以是任何形状,对所有形状都有效,例如,可以举出平板或圆板等板状、纤维状、棒状、圆柱状、棱柱状、筒状、螺旋状、球状、环状等,但在本发明中,优选基板。基板的厚度在本发明中并不特别限定。
所述基板为板状,只要是作为所述半导体膜的支撑体的基板就不特别限定。可以是绝缘体基板,也可以是半导体基板,还可以是金属基板或导电性基板,优选所述基板为绝缘体基板,另外,所述基板也优选为在表面具有金属膜的基板。作为所述基板,例如可以举出包含具有刚玉结构的基板材料作为主成分的基底基板、或者包含具有β-gallia结构的基板材料作为主成分的基底基板、包含具有六方晶结构的基板材料作为主成分的基底基板等。在此,“主成分”是指具有前述特定的晶体结构的基板材料相对于基板材料的全部成分,以原子比计优选包含50%以上,更优选包含70%以上,进一步优选包含90%以上,也可以是100%。
基板材料只要不阻碍本发明的目的,就不特别限定,可以为公知的基板材料。作为前述的具有刚玉结构的基板材料,例如,可以优选举出α-Al2O3(蓝宝石基板)或α-Ga2O3,作为更优选的例子可以举出a面蓝宝石基板、m面蓝宝石基板、r面蓝宝石基板、c面蓝宝石基板、α型氧化镓基板(a面、m面或r面)等。作为以具有β-gallia结构的基板材料为主成分的基底基板,例如,可以举出β-Ga2O3基板,或者包含Ga2O3和Al2O3且Al2O3为大于0wt%且60wt%以下的混晶基板等。另外,作为以具有六方晶结构的基板材料为主成分的基底基板,例如,可以举出SiC基板、ZnO基板、GaN基板等。
在本发明中,在所述成膜工序之后,还可以进行退火处理。关于退火的处理温度,只要不阻碍本发明的目的就不特别限定,通常为300℃~650℃,优选为350℃~550℃。另外,退火的处理时间通常为1分钟~48小时,优选为10分钟~24小时,更优选为30分钟~12小时。此外,关于退火处理,只要不阻碍本发明的目的,可以在任何气氛下进行。可以为非氧气氛下,也可以为氧气氛下。作为非氧气氛下,例如,可以举出非活性气体气氛下(例如,氮气氛下)或还原气体气氛下等,在本发明中,优选为非活性气体气氛下,更优选为氮气氛下。
另外,在本发明中,可以直接在所述基体上设置所述半导体膜,也可以隔着应力松弛层(例如,缓冲层、ELO层等)、剥离牺牲层等其他层设置所述半导体膜。各层的形成方法并不特别限定,可以为公知的方法,在本发明中,优选雾化CVD法。
在本发明中,对于所述半导体膜,可以使用从所述基体等剥离等的公知的方法之后作为所述半导体层用于半导体元件,也可以直接作为半导体层用于半导体元件。
只要是所述层叠结构体中的第一金属层、第二金属层和第三金属层分别由互不相同的一种或两种以上的金属构成,第一金属层和第三金属层之间配置有第二金属层,第二金属层包含Pt或/和Pd,第一金属层与所述半导体层欧姆接触,就不特别限定。所述层叠结构体的各金属层的构成金属各自不特别限定,例如可以举出过渡金属、贫金属等。在本发明中,优选所述半导体元件至少包含第一金属层、第二金属层和第三金属层作为欧姆电极。此外,所述欧姆电极只要不阻碍本发明的目的,就可以进一步包含包括第四金属层或第五金属层的多层的导电体层,例如也可以包含1~100的导电体层。
所述欧姆电极只要至少包含与所述半导体层欧姆接触的第一金属层、第二金属层和第三金属层,该第一金属层、该第二金属层和该第三金属层分别由互不相同的一种或两种以上的金属构成,第一金属层和第三金属层之间配置有第二金属层,第二金属层为Pt层或Pd层,就不特别限定。在本发明中,优选所述欧姆电极的第一金属层为Ti层或In层。另外,优选所述欧姆电极的第三金属层是选自Au层、Ag层和Cu层中的至少一种或两种以上的由金属构成的金属层。所述欧姆电极的各个金属层的厚度不特别限定,优选0.1nm~10μm,更优选1nm~1000nm。
所述欧姆电极的形成方法不特别限定,可以为公知的方法。作为所述欧姆电极的形成方法,具体而言,例如可以举出干法、湿法等。作为干法,例如可以举出溅射、真空蒸镀、CVD等。作为湿法,例如可以是丝网印刷或模涂等。
另外,所述半导体元件既可以包含肖特基电极,也可以不包含肖特基电极。在本发明中,作为优选方式之一,优选所述半导体元件为肖特基势垒二极管。关于所述肖特基电极(以下,也简称为“电极层”),只要具有导电性并能够作为肖特基电极使用,只要不阻碍本发明的目的,就不特别限定。所述电极层的构成材料可以是导电性无机材料,也可以是导电性有机材料。在本发明中,所述电极的材料优选为金属。作为所述金属,优选地,例如可以举出选自元素周期表第4族~第10族中的至少一种金属等。作为元素周期表第4族的金属,例如可以举出钛(Ti)、锆(Zr)、铪(Hf)等。作为元素周期表第5族的金属,例如可以举出钒(V)、铌(Nb)、钽(Ta)等。作为元素周期表第6族的金属,例如可以举出铬(Cr)、钼(Mo)和钨(W)等。作为元素周期表第7族的金属,例如可以举出锰(Mn)、锝(Tc)、铼(Re)等。作为元素周期表第8族的金属,例如可以举出铁(Fe)、钌(Ru)、锇(Os)等。作为元素周期表第9族的金属,例如可以举出钴(Co)、铑(Rh)、铱(Ir)等。作为元素周期表第10族的金属,例如可以举出镍(Ni)、钯(Pd)、铂(Pt)等。在本发明中,优选地,所述电极层包含选自元素周期表第4族、第6族和第9族中的至少一种金属,更优选包含选自元素周期表第6族和元素周期表第9族的金属,最优选包含Mo和/或Co。所述电极层的层厚并不特别限定,优选为0.1nm~10μm,更优选为5nm~500nm,最优选为10nm~200nm。另外,在本发明中,所述电极层优选为由组成互不相同的两层以上构成。通过将所述电极层设为这样的优选结构,不仅能够得到肖特基特性更优异的半导体元件,还能够更好地表现出抑制漏电流的效果。
当所述电极层由包含第一电极层和第二电极层的两层以上构成时,优选第二电极层具有导电性且导电率比第一电极层高。第二电极层的构成材料可以是导电性无机材料,也可以是导电性有机材料。在本发明中,第二电极层的材料优选为金属。作为所述金属,优选地,例如可举出选自元素周期表第8族~第13族中的至少一种金属等。作为元素周期表第8族~第10族的金属,可以举出在前述的电极层的说明中作为元素周期表第8族~第10族的金属分别例举出的金属等。作为元素周期表第11族的金属,例如可以举出铜(Cu)、银(Ag)、金(Au)等。作为元素周期表第12族的金属,例如可以举出锌(Zn)、镉(Cd)等。另外,作为元素周期表第13族的金属,例如可以举出铝(Al)、镓(Ga)、铟(In)等。在本发明中,第二电极层优选包含选自元素周期表第11族和第13族金属中的至少一种金属,更优选包含选自银、铜、金和铝中的至少一种金属。此外,第二电极层的层厚并不特别限定,优选为1nm~500μm,更优选为10nm~100μm,最优选为0.5μm~10μm。此外,在本发明中,相较于从所述开口部至1μm的距离的所述绝缘体膜的膜厚,所述电极层的外端部下的所述绝缘体膜的膜厚更厚,能够使半导体元件的耐压特性更优异,因此优选。
另外,在本发明中,优选所述肖特基电极至少包含第一金属层、第二金属层和第三金属层,该第一金属层、该第二金属层和该第三金属层分别由互不相同的一种或两种以上的金属构成,该第一金属层和该第三金属层之间配置有该第二金属层,该第一金属层比该第三金属层更靠近所述半导体层侧。此外,在所述肖特基电极包含第一金属层、第二金属层和第三金属层的情况下,分别优选地,该第一金属层是包含元素周期表第6族的金属的金属层或包含第9族的金属的金属层,该第二金属层是包含元素周期表第4族的金属的金属层,该第三金属层是包含元素周期表第13族金属的金属层,分别更优选地,该第一金属层是Co层或Mo层,该第二金属层是Ti层,该第三金属层是Al层。
所述电极层的形成方法并不特别限定,可以为公知的方法。作为所述电极层的形成方法,具体而言,例如可以举出干法和湿法等。作为干法,例如可以举出溅射、真空蒸镀、CVD等。作为湿法,例如可以举出丝网印刷或模涂等。
另外,在本发明的一方式中,优选地,所述肖特基电极具有朝向所述所述半导体元件的外侧而膜厚减少的构造。在这种情况下,所述肖特基电极在侧面可以具有锥形区域,所述肖特基电极可以由包含第一电极层和第二电极层的两层以上构成,且第一电极层的外端部也可以比第二电极层的外端部更靠近外侧。在本发明的一方式中,在所述肖特基电极具有锥形区域的情况下,这样的锥形区域的锥形角只要不阻碍本发明的目的,就不特别限定,优选为80°以下,更优选为60°以下,最优选为40°以下。所述锥形角的下限也没有特别限定,优选为0.2°,更优选为1°。另外,在本发明的一方式中,在所述肖特基电极的第一电极层的外端部比第二电极层的外端部更靠近外侧的情况下,第一电极层的外端部与第二电极层的外端部的距离为1μm以上时,更加能够抑制漏电流,因此优选。另外,在本发明的一方式中,所述肖特基电极的第一电极层中的与第二电极层的外端部相比向外侧突出的部分(以下也称为“突出部分”)中的至少一部分具有朝向所述半导体元件的外侧而膜厚减少的构造,这种构造也能够使所述半导体元件的耐压性更优异,因此优选。另外,通过组合这样的优选电极结构与上述优选的所述半导体层的构成材料,能够得到更好地抑制了漏电流且损耗更低的半导体元件。
所述半导体元件优选包含氧化物半导体层和覆盖氧化物半导体层的至少侧面的介电膜。通过这样构成,能够抑制氧化物半导体膜的半导体特性因吸湿或大气中等的氧等而受到阻碍。此外,在本发明的一方式中,进一步地,通过使所述半导体层的侧面呈锥形,不仅能够提高与所述介电膜的密接性等,而且能够使应力松弛更加良好,并能够更加提高可靠性等。
所述介电膜形成于所述半导体层上,通常具有开口部,但相对介电常数等不特别限定,可以为公知的介电膜。在本发明的一方式中,所述介电膜为至少从所述开口部至1μm以上形成的介电膜,且相对介电常数优选为5以下。“相对介电常数”是膜的介电常数和真空的介电常数之比。在本发明中,优选所述介电膜是包含Si的膜。作为前述的包含Si的膜,可以举出氧化硅系的膜作为优选例子。作为所述氧化硅系膜,例如可以举出SiO2膜、磷添加SiO2(PSG)膜、硼添加SiO2膜、磷硼添加SiO2膜(BPSG膜)、SiOC膜、SiOF膜等。作为所述介电膜的形成方法,没有特别限定,例如可以举出CVD法、大气压CVD法、等离子体CVD法、雾化CVD法、热氧化法等。在本发明中,所述介电膜的形成方法优选为雾化CVD法或大气压CVD法。
另外,关于本发明的一方式中的半导体元件,进一步地,优选与所述欧姆电极的第三金属层接触而配置有多孔层。所述多孔层不特别限定,优选具有导电性,更优选包含贵金属。在本发明的一方式中,优选所述多孔层的空隙率为10%以下。通过形成这样的优选空隙率,可以在不损害半导体特性的情况下,缓和翘曲和热应力的集中等。此外,使所述多孔层的空隙率为10%的方法不特别限定,可以为公知的方法,通过适当地设定烧结时间、压力、烧结温度等烧结条件,能够容易地使所述多孔层的空隙率为10%,例如可以举出通过加热下的压接(热压接)等将空隙率调节为10%以下的方法等,更具体而言,例如可以举出在烧结时,在一定的加压下以比通常更长的烧结时间烧结等。图13的(a)表示作为试验例通过通常的退火接合由Ag构成的多孔层时的空隙率。如图13的(a)所示,多孔层的空隙率通常超过10%,而如图13的(b)所示,在例如300℃~500℃的加热下且例如在0.2MPa~10MPa的加压下进一步进行一小时的压接时,空隙率为10%以下,通过将这样的空隙率10%以下的多孔层用于半导体元件,可以在不损害半导体特性的情况下,缓和翘曲和热应力的集中等。此外,这里的“空隙率”是指由空隙产生的空间的体积占多孔层的体积(包含空隙的体积)的比例。例如,多孔层的空隙率可以根据使用扫描电子显微镜(SEM:Scanning ElectronMicroscope)拍摄的截面照片来求出。具体而言,在多个位置拍摄多孔层的截面照片(SEM图像)。接着,使用市售的图像解析软件,将拍摄的SEM像进行二值化,求出相当于SEM图像中的孔(空隙)的部分(例如黑色部)的比例。将从在多个位置拍摄的SEM图像求出的黑色部的比例进行平均,作为多孔层的空隙率。此外,所述“多孔层”不仅包含作为连续的膜状结构体的多孔膜状,还包含多孔的凝聚体状。
另外,本发明的半导体元件还优选在所述多孔层上配置有基板。此外,所述基板可以直接层叠在所述多孔层上,所述基板也可以隔着一种或两种以上的金属层(例如上述例举出的金属等)等其他层层叠在所述多孔层上。
在本发明的方式中,关于半导体元件,电流的流动方向等不特别限定,优选在所述氧化物半导体膜的第一面侧配置有肖特基电极,在处于所述第一面侧的相反侧的第二面侧配置有欧姆电极,半导体元件更优选为纵向型器件。
实施例
以下,使用附图更详细地说明本发明的优选实施方式,但本发明不限于这些实施方式。
图1示出了作为本发明优选实施方式之一的半导体元件的肖特基势垒二极管(SBD)的主要部分。图1的SBD具备欧姆电极102、半导体层101、肖特基电极103和介电膜104。欧姆电极102包含金属层102a、金属层102b和金属层102c。半导体层101包含第一半导体层101a和第二半导体层101b。肖特基电极103包含金属层103a、金属层103b和金属层103c。第一半导体层101a例如是n-型半导体层,第二半导体层101b例如是n+型半导体层101b。另外,介电膜104(以下也称为“绝缘体膜”)覆盖半导体层101的侧面(第一半导体层101a的侧面和第二半导体层101b的侧面),且具有位于半导体层101(第一半导体层101a)的上表面的开口部,开口部设置在第一半导体层101a的一部分和所述肖特基电极103的金属层103c之间。介电膜104可以以覆盖半导体层101的侧面,并覆盖半导体层101(第一半导体层101a)的上面的一部分的方式延伸设置。图1的半导体元件通过介电膜104改善了端部的晶体缺陷,以更好地形成耗尽层,并且电场缓和也更加良好,另外,可以更好地抑制漏电流。此外,在图17中示出了设置有多孔层108和基板109的SBD的一优选例子。
图6示出作为本发明优选实施方式之一的半导体元件的肖特基势垒二极管(SBD)的主要部分。图6的SBD与图1的SBD相比,不同点在于在肖特基电极103的侧面具有锥形区域。关于图6的半导体元件,作为第一金属层的金属层103b和/或金属层103c的外端部位于比作为第二金属层的金属层103a的外端部更靠近外侧的位置,因此可以更好地抑制漏电流。另外,还在金属层103b和/或金属层103c中的、比金属层103a的外端部更向外侧突出的部分具有朝向半导体元件的外侧而膜厚减少的锥形区域,因此成为耐压性更加优异的结构。
作为金属层103a的构成材料,例如可以举出上述例举出的金属等。另外,作为金属层103b和金属层103c的构成材料,例如可以举出上述例举出的金属等。图1的各层的形成方法只要不阻碍本发明的目的,就不特别限定,可以为公知的方法。例如,可以举出通过真空蒸镀法、CVD法、溅射法、各种涂覆技术来进行成膜后,通过光刻法进行图案化的方法,或者使用印刷技术等直接进行图案化的方法等。
下面将说明图17的SBD的优选制造工序,但是本发明不限于这些优选制造方法。图2的(a)示出通过上述雾化CVD法在晶体生长用基板(蓝宝石基板)110上隔着应力松弛层层叠有第一半导体层101a和第二半导体层101b的层叠体。在第二半导体层101b上,使用所述干法或所述湿法形成作为欧姆电极的金属层102a、金属层102b和金属层102c,而得到图2的(b)的层叠体。第一半导体层101a例如是n-型半导体层,第二半导体层101b例如是n+型半导体层101b。另外,隔着由贵金属构成的多孔层108将基板109层叠于图2的(b)的层叠体,而得到层叠体(c)。并且,如图3所示,利用公知的剥离方法对层叠体(c)的晶体生长用基板110和应力松弛层111进行剥离,而得到层叠体(d)。然后,如图4所示,将层叠体(d)的半导体层的侧面通过蚀刻呈锥形,而得到层叠体(e)之后,在锥形的侧面和除半导体层的开口部以外的上面层叠绝缘体膜104,而得到层叠体(f)。接着,如图5所示,在层叠体(f)的半导体层的上面开口部分,利用所述干法或所述湿法形成作为肖特基电极的金属层103a、103b和103c,而得到层叠体(g)。如上所述得到的半导体元件能够良好地抑制半导体层的氧等的扩散,从而发挥优异的欧姆特性,同时改善端部的晶体缺陷,更好地形成耗尽层,电场缓和也更加良好,另外,能够更好地抑制漏电流。
另外,在本实施例中,作为金属层102b使用了Pt或Pd,但是在作为金属层102b使用Ni的情况下,例如如图14所示,会产生变色的问题。图14的(a)是表示在使用Ti层/Pt层/Au层(Ti/Pt/Au)作为欧姆电极的情况下的烧结后的外观的照片,图14的(b)是表示在使用Ti层/Ni层/Au层(Ti/Ni/Au)作为欧姆电极的情况下的烧结后的外观的照片。从图14明显看到,在使用Ti/Ni/Au作为欧姆电极的(b)的情况下,存在发生变色的问题。另外,图7中示出了在使用Ti/Ni/Au作为欧姆电极的图14的(b)的情况下的SEM-EDS(扫描电镜能谱分析)的结果。如图7所示,可知在作为欧姆电极使用Ti/Ni/Au的情况下,会产生氧的扩散。此外,图7是示出在作为欧姆电极使用Ti/Ni/Au的情况下的SEM-EDS的结果的图,并且示出了Ti、Ni和O的分布。如图7的上层所示,可知Ni层抑制了Ti的扩散,但是如图7的下层所示,产生了氧的扩散。另外,评价了作为欧姆电极使用Ti/Pt/Au的情况和使用Ti/Ni/Au的情况的接触低效率的温度依赖性(烧结温度)。结果显示于图15。在图15的(a)的使用Ti/Pt/Au作为欧姆电极的情况下,随着烧结温度的上升,接触电阻率较好地下降,但是在图15的(b)的使用Ti/Ni/Au作为欧姆电极的情况下,会产生当烧结温度上升时接触电阻率也上升等问题。此外,通过功率循环试验对本实施例产品进行了性能评价,完成了5分钟、3000个循环,评价结果为良好。
另外,所述半导体元件优选为纵向型器件,特别还对功率器件有用。作为所述半导体元件,例如可以举出二极管(例如,PN二极管、肖特基势垒二极管、结势垒肖特基二极管等)或晶体管(例如,MOSFET、MESFET等)等,其中优选二极管,更优选肖特基势垒二极管(SBD)。
本发明的半导体元件,除了上述的事项外,还根据常用方法,利用接合部件接合于引线框、电路基板或散热基板等,而优选用作半导体装置,尤其优选用作功率模块、逆变器或转换器,进一步地,优选用作例如使用了电源装置的半导体系统等。图11示出了所述半导体装置的一优选例子。关于图11的半导体装置,半导体元件500的两个面分别通过焊料501与引线框、电路基板或散热基板502接合。通过这种构成,可以形成散热性优异的半导体装置。此外,在本发明中,优选地,焊料等接合部件的周边用树脂密封。
另外,关于所述电源装置,可以通过使用公知的方法,比如连接于布线图案等,从而由半导体装置制作电源装置,或者作为所述半导体装置制作电源装置。图8使用多个所述电源装置171、172和控制电路173,来构成电源系统170。所述电源系统,如图9所示,能够组合电子电路181和电源系统182用于系统装置180。此外,图10显示电源装置的电源电路图的一个例子。图10显示包含功率电路和控制电路的电源装置的电源电路,利用逆变器192(MOSFET:以A~D构成),将DC电压以高频进行切换,转换到AC后,用变压器193来实施绝缘及变压,用整流MOSFET194(A~B’)进行整流后,用DCL195(平滑用线圈L1和L2)及电容器进行平滑,并输出直流电压。此时,用电压比较器197将输出电压与基准电压进行比较,并且以PWM控制电路196控制逆变器192和整流MOSFET194,以获得期望的输出电压。
在本发明的一方式中,优选地,所述半导体装置为功率卡,包含冷却器和绝缘部件,更优选地,在所述半导体层的两侧分别至少隔着所述绝缘部件设置有所述冷却器,最优选地,在所述半导体层的两侧分别设置有散热层,在散热层的外侧至少隔着所述绝缘部件分别设置有所述冷却器。图12显示作为本发明的优选实施方式之一的功率卡。图12的功率卡是双面冷却型功率卡201,具备:制冷剂管202、间隔件203、绝缘板(绝缘间隔件)208、密封树脂部209、包含半导体元件的半导体芯片301a、金属传热板(突出端子部)302b、散热器和电极303、金属传热板(突出端子部)303b、焊接层304、控制电极端子305、接合线308。制冷剂管202的厚度方向剖面具有多个流路222,该流路222由彼此隔开规定间隔并在流路方向上延伸的多个分隔壁221划分。根据这种优选的功率卡,能够实现更强的散热性,能够满足更高的可靠性。
半导体芯片301a通过焊接层304被接合于金属传热板302b的内侧的主面上,在半导体芯片301a的剩余的主面上,金属传热板(突出端子部)302b通过焊接层304接合,由此在IGBT(绝缘栅双极型晶体管)的集电极面和发射极面以所谓的反向并联连接有飞轮二极管的阳极电极面和阴极电极面。作为金属传热板(突出端子部)302b和303b的材料,例如可以举出Mo或W。金属传热板(突出端子部)302b和303b具有吸收半导体芯片301a厚度差的厚度差,由此金属传热板302b和303b的外表面为平面。
树脂密封部209例如由环氧树脂构成,覆盖这些金属传热板302b和303b的侧面而进行模制,半导体芯片301a由树脂密封部209进行模制。但是,金属传热板302b和303b的外主面、即接触受热面完全露出。金属传热板(突出端子部)302b和303b从树脂密封部209向图9中的右方突出,关于作为所谓的引线框端子的控制电极端子305,例如形成有IGBT的半导体芯片301a的栅极(控制)电极面与控制电极端子305连接。
作为绝缘间隔件的绝缘板208例如由氮化铝膜构成,但也可以是其他绝缘膜。绝缘板208完全覆盖金属传热板302b和303b并密接在一起,但是绝缘板208与金属传热板302b和303b可以仅仅是接触,也可以涂布硅脂等良好的导热材料,也可以通过各种方法使它们接合。另外,也可以通过陶瓷热喷涂等形成绝缘层,也可以将绝缘板208接合在金属传热板上,还可以接合或形成在制冷剂管上。
制冷剂管202通过将板材切断为所需的长度来制作,该板材通过将铝合金用拉拔成形法或挤压成形法而成形。制冷剂管202的厚度方向剖面具有多个流路222,该流路222由彼此隔开规定间隔且在流路方向上延伸的多个分隔壁221划分。间隔件203可以是例如焊接合金等软质金属板,但也可以是通过涂布等方式在金属传热板302b和303b的接触面形成的膜(film)。这种软质的间隔件203的表面容易变形,与绝缘板208的微小凹凸或翘曲、制冷剂管202的微小凹凸或翘曲相适应,从而降低热电阻。此外,可以在间隔件203的表面等涂布公知的导热性良好的润滑脂等,也可以省略间隔件203。
产业上的可利用性
本发明的半导体元件能够用于半导体(例如化合物半导体电子器件等)、电子部件及电气设备部件、光学及电子照片关联装置、工业部件等所有领域,特别是对功率器件有用。
符号说明
101 半导体层
101a 第一半导体层
101b 第二半导体层
102 欧姆电极
102a 金属层
102b 金属层
102c 金属层
103 肖特基电极
103a 金属层
103b 金属层
103c 金属层
104 绝缘体膜
108 多孔层
109 基板
110 晶体生长用基板
170 电源系统
171 电源装置
172 电源装置
173 控制电路
180 系统装置
181 电子电路
182 电源系统
192 逆变器
193 变压器
194 整流MOSFET
195 DCL
196 PWM控制电路
197 电压比较器
201 双面冷却型功率卡
202 制冷剂管
203 间隔件
208 绝缘板(绝缘间隔件)
209 密封树脂部
221 分隔壁
222 流路
301a 半导体芯片
302b 金属传热板(突出端子部)
303 散热器及电极
303b 金属传热板(突出端子部)
304 焊接层
305 控制电极端子
308 接合线
500 半导体元件
501 焊料
502 引线框、电路基板或散热基板。
Claims (27)
1.一种半导体元件,其至少包含层叠结构体,所述层叠结构体通过在由氧化物半导体膜构成的半导体层上层叠第一金属层、第二金属层和第三金属层而成,第一金属层、第二金属层和第三金属层分别由互不相同的一种或两种以上的金属构成,第一金属层和第三金属层之间配置有第二金属层,第二金属层包含Pt或/和Pd,第一金属层与所述半导体层欧姆接触。
2.根据权利要求1所述的半导体元件,其中,所述氧化物半导体膜具有刚玉结构。
3.根据权利要求2所述的半导体元件,其中,所述氧化物半导体膜的主面为m面。
4.根据权利要求1~3中任一项所述的半导体元件,其中,所述氧化物半导体膜包含氧化镓和/或氧化铱。
5.根据权利要求1~4中任一项所述的半导体元件,其中,所述氧化物半导体膜包含氧化镓。
6.根据权利要求1~5中任一项所述的半导体元件,其中,所述氧化物半导体膜包含掺杂剂。
7.根据权利要求1~6中任一项所述的半导体元件,其中,第一金属层为Ti层或In层。
8.根据权利要求1~7中任一项所述的半导体元件,其中,第三金属层为由选自Au、Ag和Cu中的至少一种或两种以上的金属构成的金属层。
9.根据权利要求1~8中任一项所述的半导体元件,其中,进一步地,与第三金属层接触而配置有多孔层。
10.根据权利要求9所述的半导体元件,其中,所述多孔层的空隙率为10%以下。
11.根据权利要求9或10所述的半导体元件,其中,所述多孔层包含贵金属。
12.根据权利要求9~11中任一项所述的半导体元件,其中,进一步地,在所述多孔层上配置有基板。
13.根据权利要求1~12中任一项所述的半导体元件,其中,进一步地,包含肖特基电极。
14.根据权利要求13所述的半导体元件,其中,所述肖特基电极包含Mo和/或Co。
15.根据权利要求13或14所述的半导体元件,其中,在所述氧化物半导体膜的第一面侧配置有所述肖特基电极,在处于所述第一面侧的相反侧的第二面侧配置有欧姆电极。
16.根据权利要求13~15中任一项所述的半导体元件,其中,所述肖特基电极至少包含第一金属层、第二金属层和第三金属层,该第一金属层、该第二金属层和该第三金属层分别由互不相同的金属构成,在该第一金属层和该第三金属层之间配置有该第二金属层,该第一金属层比该第三金属层更靠近所述半导体层侧。
17.根据权利要求16所述的半导体元件,其中,所述肖特基电极的第一金属层为Co层或Mo层。
18.根据权利要求16或17所述的半导体元件,其中,所述肖特基电极的第二金属层为Ti层。
19.根据权利要求16~18中任一项所述的半导体元件,其中,所述肖特基电极的第三金属层为Al层。
20.一种半导体元件,至少具备由氧化物半导体膜构成的半导体层、肖特基电极和欧姆电极,其特征在于,
所述肖特基电极包含Co层或Mo层,
所述欧姆电极至少包含第一金属层、第二金属层和第三金属层,该第一金属层为Ti层或In层,该第二金属层为Pt层或Pd层,该第三金属层为由选自Au、Ag和Cu中的至少一种或两种以上金属构成的金属层。
21.根据权利要求1~20中任一项所述的半导体元件,其中,所述半导体层为n型氧化物半导体层。
22.根据权利要求1~21中任一项所述的半导体元件,其中,所述半导体元件为纵向型器件。
23.根据权利要求1~22中任一项所述的半导体元件,其中,所述半导体元件为功率器件。
24.一种半导体装置,至少由半导体元件与引线框、电路基板或散热基板利用接合部件接合而构成,其中,所述半导体元件为权利要求1~23中任一项所述的半导体元件。
25.根据权利要求24所述的半导体装置,其中,所述半导体装置为功率模块、逆变器或转换器。
26.根据权利要求24或25所述的半导体装置,其中,所述半导体装置为功率卡。
27.一种半导体系统,具备半导体元件或半导体装置,其特征在于,所述半导体元件为权利要求1~23中任一项所述的半导体元件,所述半导体装置为权利要求24~26中任一项所述的半导体装置。
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