CN114464678A - 功函数金属栅极装置 - Google Patents

功函数金属栅极装置 Download PDF

Info

Publication number
CN114464678A
CN114464678A CN202011244345.3A CN202011244345A CN114464678A CN 114464678 A CN114464678 A CN 114464678A CN 202011244345 A CN202011244345 A CN 202011244345A CN 114464678 A CN114464678 A CN 114464678A
Authority
CN
China
Prior art keywords
work function
function metal
gate
stepped
gate device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011244345.3A
Other languages
English (en)
Inventor
黄志文
黄士安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN202011244345.3A priority Critical patent/CN114464678A/zh
Priority to US17/128,168 priority patent/US11482605B2/en
Publication of CN114464678A publication Critical patent/CN114464678A/zh
Priority to US17/945,122 priority patent/US20230014945A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28105Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开一种功函数金属栅极装置,包含一栅极、一漂移区、一源极、一漏极以及一第一绝缘结构。栅极设置于一基底上,其中栅极包含一中突的阶梯状功函数金属堆叠结构或者一中凹的阶梯状功函数金属堆叠结构。漂移区设置于栅极的一部分下方的基底中。源极位于基底中,以及漏极位于栅极侧边的漂移区中。第一绝缘结构设置于栅极以及漏极之间的漂移区中。

Description

功函数金属栅极装置
技术领域
本发明涉及一种功函数金属栅极装置,且特别是涉及一种具有阶梯状功函数金属的功函数金属栅极装置。
背景技术
在现有半导体产业中,多晶硅系广泛地应用于半导体元件如金属氧化物半导体(metal-oxide-semiconductor,MOS)晶体管中,作为标准的栅极填充材料选择。然而,随着MOS晶体管尺寸持续地微缩,传统多晶硅栅极因硼穿透(boron penetration)效应导致元件效能降低,及其难以避免的空乏效应(depletion effect)等问题,使得等效的栅极介电层厚度增加、栅极电容值下降,进而导致元件驱动能力的衰退等困境。因此,半导体业界更尝试以新的栅极填充材料,例如利用功函数(work function)金属来取代传统的多晶硅栅极,用以作为匹配高介电常数(High-K)栅极介电层的控制电极。
发明内容
本发明提出一种功函数金属栅极装置,此装置的栅极包含阶梯状功函数金属堆叠结构,以调变通道电荷密度并降低阻值。
本发明提供一种功函数金属栅极装置,包含一栅极、一漂移区、一源极、一漏极以及一第一绝缘结构。栅极设置于一基底上,其中栅极包含一中突的阶梯状功函数金属堆叠结构。漂移区设置于栅极的一部分下方的基底中。源极位于基底中,以及漏极位于栅极侧边的漂移区中。第一绝缘结构设置于栅极以及漏极之间的漂移区中。
本发明提供一种功函数金属栅极装置,包含一栅极、一漂移区、一源极、一漏极以及一第一绝缘结构。栅极设置于一基底上,其中栅极包含一中凹的阶梯状功函数金属堆叠结构。漂移区设置于栅极的一部分下方的基底中。源极位于基底中,以及漏极位于栅极侧边的漂移区中。第一绝缘结构设置于栅极以及漏极之间的漂移区中。
本发明提出一种功函数金属栅极装置,其设置一栅极于一基底上,此栅极可包含一中突的阶梯状功函数金属堆叠结构或一中凹的阶梯状功函数金属堆叠结构,以调变通道电荷密度,并降低源极与漏极之间基底的阻值。
附图说明
图1为本发明一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图;
图2为本发明一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图;
图3为本发明一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图;
图4为本发明一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图;
图5为本发明一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图;
图6为本发明另一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图;
图7为本发明另一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图;
图8为本发明另一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图;
图9为本发明另一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图;
图10为本发明另一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图。
主要元件符号说明
12:绝缘结构
14:第一绝缘结构
16:第二绝缘结构
20:栅极氧化层
100:功函数金属栅极装置
110:基底
112:漂移区
114:第一漂移区
120:层间介电层
122:间隙壁
132:U形高介电常数介电层
134:U形阻障层
140a:第一阶梯状功函数金属堆叠结构
142、142a:第一层功函数金属层
144、144a:第二层功函数金属层
150:第二阶梯状功函数金属堆叠结构
160:低电阻率材料
B1:底层功函数金属层
B2:顶层功函数金属层
C1:中突的阶梯状功函数金属堆叠结构
D:漏极
E1、E2:端
M1:栅极
P1、P2:光致抗蚀剂
R1:凹槽
S:源极
T1、T2:侧壁
g1、g2:空隙
具体实施方式
图1~图5为本发明一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图。如图1所示,提供一基底110。基底110例如是一硅基底、一含硅基底、一三五族覆硅基底(例如GaN-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)或一硅覆绝缘(silicon-on-insulator,SOI)基底等半导体基底。在本实施例中,例如以掺杂制作工艺形成一漂移区112以及一第一漂移区114于基底110中。接着,可形成绝缘结构12于基底110中,以电性绝缘各晶体管,以及一第一绝缘结构14以及一第二绝缘结构16于基底110中,以作为电性绝缘高电压晶体管的栅极、漏极及源极之用。绝缘结构12、第一绝缘结构14以及第二绝缘结构16例如为浅沟隔离(shallow trench isolation,STI)结构,其例如以浅沟隔离制作工艺形成,详细形成方法为本领域所熟知故不再赘述,但本发明不以此为限。在本实施例中,绝缘结构12以及第一绝缘结构14位于漂移区112中,而绝缘结构12以及第二绝缘结构16位于第一漂移区114中,但本发明不以此为限。
可选择性先形成一栅极氧化层20于第一绝缘结构14以及第二绝缘结构16之间的基底110中。然后,形成一金属栅极于栅极氧化层20、第一绝缘结构14以及第二绝缘结构16上。
详细而言,可先沉积一层间介电层120覆盖基底110,其中层间介电层120具有一凹槽R1。形成层间介电层120的方法可包含下述步骤。先形成一牺牲栅极(未绘示)于栅极氧化层20、第一绝缘结构14以及第二绝缘结构16上,再形成一漏极D于绝缘结构12以及第一绝缘结构14之间的漂移区112中,以及一源极S于绝缘结构12以及第二绝缘结构16之间的第一漂移区114中。全面沉积一层间介电层(未绘示)于牺牲栅极侧边的基底110上,再移除牺牲栅极以于层间介电层120中形成凹槽R1。另外,再沉积一层间介电层之前,可先选择性形成间隙壁122于牺牲栅极的侧边,如此一来,在移除牺牲栅极之后,可形成间隙壁122围绕凹槽R1。
之后,形成一U形高介电常数介电层132、一U形阻障层134以及一第一层功函数金属层142顺应覆盖凹槽R1。在一实施例中,可先依序沉积一高介电常数介电层(未绘示)、一阻障层(未绘示)以及一功函数金属层(未绘示)顺应覆盖凹槽R1、间隙壁122以及层间介电层120,再移除超出凹槽R1的高介电常数介电层(未绘示)、阻障层(未绘示)以及功函数金属层(未绘示),以形成U形高介电常数介电层132、U形阻障层134以及第一层功函数金属层142于凹槽R1中。U形高介电常数介电层132可选自氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium siliconoxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconiumoxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconiumsilicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconate titanate,PbZrxTi1-xO3,PZT)与钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)所组成的群组;U形阻障层134例如为氮化钽(tantalum nitride,TaN)、氮化钛(titanium nitride,TiN)等单层结构或复合层结构,但本发明不以此为限。
然后,形成一光致抗蚀剂P1于第一层功函数金属层142上,以图案化第一层功函数金属层142。
如图2所示,以光致抗蚀剂P1图案化第一层功函数金属层142,而形成一第一层功函数金属层142a。随即,移除光致抗蚀剂P1。
如图3~图4所示,形成一第二层功函数金属层144a覆盖第一层功函数金属层142a。如图3所示,可先沉积一第二层功函数金属层144顺应覆盖凹槽R1。接着,如图4所示,形成一光致抗蚀剂P2覆盖凹槽R1中的部分的第二层功函数金属层144,以图案化第二层功函数金属层144,而形成第二层功函数金属层144a覆盖第一层功函数金属层142a。随即,移除光致抗蚀剂P2。
如此一来,本实施例可形成一第一阶梯状功函数金属堆叠结构140a,其中第一阶梯状功函数金属堆叠结构140a可包含一底层功函数金属层B1以及一顶层功函数金属层B2,其中底层功函数金属层B1的两端E1/E2突出顶层功函数金属层B2。在本实施例中,是以分别沉积第一层功函数金属层142a以及第二层功函数金属层144a而形成第一阶梯状功函数金属堆叠结构140a,但在其他实施例中,也可分别沉积底层功函数金属层B1以及顶层功函数金属层B2而形成第一阶梯状功函数金属堆叠结构140a,视实际情况而定。
如图5所示,沉积一第二阶梯状功函数金属堆叠结构150,顺应覆盖第一阶梯状功函数金属堆叠结构140a以及基底110。第一阶梯状功函数金属堆叠结构140a以及第二阶梯状功函数金属堆叠结构150为一满足晶体管所需功函数要求的金属,其可为单层结构或复合层结构,例如氮化钛(titanium nitride,TiN)、碳化钛(titanium carbide,TiC)、氮化钽(tantalum nitride,TaN)、碳化钽(tantalum carbide,TaC)、碳化钨(tungsten carbide,WC)、铝钛(titanium aluminide,TiAl)或氮化铝钛(aluminum titanium nitride,TiAlN)等。如此,形成一中突的阶梯状功函数金属堆叠结构C1,且在优选的实施例中,中突的阶梯状功函数金属堆叠结构C1具有一金字塔型阶梯状剖面结构,但本发明不限于此。
本实施例中,第一阶梯状功函数金属堆叠结构140a与第二阶梯状功函数金属堆叠结构150具有不同电性。在一实施例中,第一阶梯状功函数金属堆叠结构140a具有P型功函数金属(功函数约介于4.8eV与5.2eV之间,例如氮化钛),而第二阶梯状功函数金属堆叠结构150具有N型功函数金属(功函数约介于3.9eV与4.3eV之间,例如铝钛),但本发明不以此为限。
而后,形成一低电阻率材料160填充凹槽R1,即可形成一(金属)栅极M1,其中低电阻率材料160可由铝、钨、钛铝合金(TiAl)或钴钨磷化物(cobalt tungsten phosphide,CoWP)等低电阻材料所构成。
承上,本实施例形成一功函数金属栅极装置100,其中此功函数金属栅极装置100包含栅极M1设置于基底110上,且栅极M1包含中突的阶梯状功函数金属堆叠结构C1。中突的阶梯状功函数金属堆叠结构C1可包含底层功函数金属层B1以及顶层功函数金属层B2。
漂移区112设置于栅极M1的部分下方的基底110中,且第一绝缘结构14设置于栅极M1以及漏极D之间的漂移区112中。第一漂移区114设置于栅极M1的部分下方的基底110中,且第二绝缘结构16设置于栅极M1以及源极S之间的第一漂移区114中。是以,本发明可调变通道电荷密度(特别是接近漏极D的通道电荷密度),并降低漂移区112的阻值。在一优选的实施例中,第一阶梯状功函数金属堆叠结构140a垂直重叠第一绝缘结构14的一部分,或者第一阶梯状功函数金属堆叠结构140a的一侧壁T1与第一绝缘结构14的一侧壁T2切齐。在一更佳的实施例中,底层功函数金属层B1垂直覆盖第一绝缘结构14以及第二绝缘结构16之间的一空隙g1,且顶层功函数金属层B2垂直重叠漂移区112以及第一漂移区114之间的一空隙g2。
以上提出本发明具有中突的阶梯状功函数金属堆叠结构的功函数金属栅极装置。以下再提出本发明另一实施例,其具有中凹的阶梯状功函数金属堆叠结构的功函数金属栅极装置。
图6~图10为本发明另一实施例的形成功函数金属栅极装置的制作工艺的剖面示意图。如图6所示,提供一基底110。基底110例如是一硅基底、一含硅基底、一三五族覆硅基底(例如GaN-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)或一硅覆绝缘(silicon-on-insulator,SOI)基底等半导体基底。在本实施例中,例如以掺杂制作工艺形成一漂移区112以及一第一漂移区114于基底110中。接着,可形成绝缘结构12于基底110中,以电性绝缘各晶体管,以及一第一绝缘结构14以及一第二绝缘结构16于基底110中,以作为电性绝缘高电压晶体管的栅极、漏极及源极之用。绝缘结构12、第一绝缘结构14以及第二绝缘结构16例如为浅沟隔离(shallow trench isolation,STI)结构,其例如以浅沟隔离制作工艺形成,详细形成方法为本领域所熟知故不再赘述,但本发明不以此为限。在本实施例中,绝缘结构12以及第一绝缘结构14位于漂移区112中,而绝缘结构12以及第二绝缘结构16位于第一漂移区114中,但本发明不以此为限。
可先形成一栅极氧化层20于第一绝缘结构14以及第二绝缘结构16之间的基底110中。然后,形成一金属栅极于栅极氧化层20、第一绝缘结构14以及第二绝缘结构16上。详细而言,可先沉积一层间介电层120覆盖基底110,其中层间介电层120具有一凹槽R2。形成层间介电层120的方法可包含下述步骤。先形成一牺牲栅极(未绘示)于栅极氧化层20、第一绝缘结构14以及第二绝缘结构16上,再形成一漏极D于绝缘结构12以及第一绝缘结构14之间的漂移区112中,以及一源极S于绝缘结构12以及第二绝缘结构16之间的第一漂移区114中。全面沉积一层间介电层(未绘示)于牺牲栅极侧边的基底110上,再移除牺牲栅极以于层间介电层120中形成凹槽R2。另外,再沉积一层间介电层之前,可先选择性形成间隙壁122于牺牲栅极的侧边,如此一来,在移除牺牲栅极之后,可形成间隙壁122围绕凹槽R2。
之后,形成一U形高介电常数介电层132、一U形阻障层134以及一第一层功函数金属层142顺应覆盖凹槽R2。在一实施例中,可先依序沉积一高介电常数介电层(未绘示)、一阻障层(未绘示)以及一功函数金属层(未绘示)顺应覆盖凹槽R2、间隙壁122以及层间介电层120,再移除超出凹槽R2的高介电常数介电层(未绘示)、阻障层(未绘示)以及功函数金属层(未绘示),以形成U形高介电常数介电层132、U形阻障层134以及第一层功函数金属层142于凹槽R2中。U形高介电常数介电层132可选自氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium siliconoxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconiumoxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconiumsilicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconate titanate,PbZrxTi1-xO3,PZT)与钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)所组成的群组;U形阻障层134例如为氮化钽(tantalum nitride,TaN)、氮化钛(titanium nitride,TiN)等单层结构或复合层结构,但本发明不以此为限。
然后,形成一光致抗蚀剂P3于第一层功函数金属层142上,以图案化第一层功函数金属层142。
如图7所示,以光致抗蚀剂P3图案化第一层功函数金属层142,而形成一第一层功函数金属层142b,并暴露出部分的阻障层134。随即,移除光致抗蚀剂P3。
如图8~图9所示,形成一第二层功函数金属层244a覆盖第一层功函数金属层142b。如图8所示,可先沉积一第二层功函数金属层244顺应覆盖凹槽R2。接着,如图9所示,形成一光致抗蚀剂P4覆盖凹槽R2中的部分的第二层功函数金属层244,以图案化第二层功函数金属层244,而形成第二层功函数金属层244a覆盖第一层功函数金属层142b。随即,移除光致抗蚀剂P4。
如此一来,本实施例可形成一第一阶梯状功函数金属堆叠结构240,其中第一阶梯状功函数金属堆叠结构240可包含一底层功函数金属层B11以及一顶层功函数金属层B22。底层功函数金属层B11具有一第一凹槽r1以及顶层功函数金属层B22具有一第二凹槽r2,其中第二凹槽r2垂直重叠第一凹槽r1。在一优选的实施例中,第一凹槽r1与第二凹槽r2共用一中线,以形成对称的功函数金属结构。
在本实施例中,是以分别沉积第一层功函数金属层142b以及第二层功函数金属层244a而形成第一阶梯状功函数金属堆叠结构240,但在其他实施例中,也可分别沉积底层功函数金属层B11以及顶层功函数金属层B22而形成第一阶梯状功函数金属堆叠结构240,视实际情况而定。
如图10所示,沉积一第二阶梯状功函数金属堆叠结构250,顺应覆盖第一阶梯状功函数金属堆叠结构240以及基底110。第一阶梯状功函数金属堆叠结构240以及第二阶梯状功函数金属堆叠结构250为一满足晶体管所需功函数要求的金属,其可为单层结构或复合层结构,例如氮化钛(titanium nitride,TiN)、碳化钛(titanium carbide,TiC)、氮化钽(tantalum nitride,TaN)、碳化钽(tantalum carbide,TaC)、碳化钨(tungsten carbide,WC)、铝钛(titanium aluminide,TiAl)或氮化铝钛(aluminum titanium nitride,TiAlN)等。如此,形成一中凹的阶梯状功函数金属堆叠结构C2,且在优选的实施例中,中凹的阶梯状功函数金属堆叠结构C2具有一盘型阶梯状剖面结构,但本发明不限于此。
本实施例中,第一阶梯状功函数金属堆叠结构240与第二阶梯状功函数金属堆叠结构250具有不同电性。在一实施例中,第一阶梯状功函数金属堆叠结构240具有P型功函数金属(功函数约介于4.8eV与5.2eV之间,例如氮化钛),而第二阶梯状功函数金属堆叠结构250具有N型功函数金属(功函数约介于3.9eV与4.3eV之间,例如铝钛)。
而后,形成一低电阻率材料260填充凹槽R2,即可形成一(金属)栅极M2,其中低电阻率材料160可由铝、钨、钛铝合金(TiAl)或钴钨磷化物(cobalt tungsten phosphide,CoWP)等低电阻材料所构成。
承上,本实施例形成一功函数金属栅极装置200,其中此功函数金属栅极装置200包含栅极M2设置于基底110上,且栅极M2包含中凹的阶梯状功函数金属堆叠结构C2。中凹的阶梯状功函数金属堆叠结构C2可包含底层功函数金属层B11以及顶层功函数金属层B22。
漂移区112设置于栅极M2的部分下方的基底110中,且第一绝缘结构14设置于栅极M1以及漏极D之间的漂移区112中。第一漂移区114设置于栅极M1的部分下方的基底110中,且第二绝缘结构16设置于栅极M1以及源极S之间的第一漂移区114中。是以,本发明可调变源极S至漏极D之间,且特别是接近漏极D的通道电荷密度,并降低漂移区112的阻值。在一优选的实施例中,顶层功函数金属层B22的第二凹槽r2垂直覆盖第一绝缘结构14以及第二绝缘结构16之间的一空隙g3。在一更佳的实施例中,底层功函数金属层B11的第一凹槽r1垂直重叠漂移区112以及第一漂移区114之间的一空隙g4。
综上所述,本发明提出一种功函数金属栅极装置,其设置一栅极于基底上,此栅极可包含一中突的阶梯状功函数金属堆叠结构或一中凹的阶梯状功函数金属堆叠结构,以调变通道电荷密度,并降低源极与漏极之间基底的阻值。中突的阶梯状功函数金属堆叠结构较佳具有一金字塔型阶梯状剖面结构。中凹的阶梯状功函数金属堆叠结构较佳具有一盘型阶梯状剖面结构。
再者,一漏极位于栅极侧边的漂移区中,且一源极位于栅极侧边的一第一漂移区中。一第一绝缘结构设置于栅极以及漏极之间的漂移区中,且一第二绝缘结构设置于栅极以及源极之间的第一漂移区中。可通过调整阶梯状功函数金属堆叠结构中各层金属层垂直对应漂移区以及绝缘结构的位置,以局部调变通道的电荷密度,进而改变局部基底或漂移区的阻值。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。

Claims (20)

1.一种功函数金属栅极装置,其特征在于,包含:
栅极,设置于基底上,其中该栅极包含中突的阶梯状功函数金属堆叠结构;
漂移区,设置于该栅极的一部分下方的该基底中;
源极,位于该基底中,以及漏极位于该栅极侧边的该漂移区中;以及
第一绝缘结构,设置于该栅极以及该漏极之间的该漂移区中。
2.如权利要求1所述的功函数金属栅极装置,其中该中突的阶梯状功函数金属堆叠结构具有金字塔型阶梯状剖面结构。
3.如权利要求2所述的功函数金属栅极装置,其中该中突的阶梯状功函数金属堆叠结构包含第一阶梯状功函数金属堆叠结构以及第二阶梯状功函数金属堆叠结构,其中该第二阶梯状功函数金属堆叠结构顺应覆盖该第一阶梯状功函数金属堆叠结构以及该基底。
4.如权利要求3所述的功函数金属栅极装置,其中该第一阶梯状功函数金属堆叠结构与该第二阶梯状功函数金属堆叠结构具有不同电性。
5.如权利要求3所述的功函数金属栅极装置,其中该第一阶梯状功函数金属堆叠结构包含底层功函数金属层以及顶层功函数金属层,其中该底层功函数金属层的两端突出该顶层功函数金属层。
6.如权利要求5所述的功函数金属栅极装置,还包含:
第二绝缘结构,设置于该栅极以及该源极之间的该基底中;以及
栅极氧化层,位于该第一绝缘结构以及该第二绝缘结构之间的该基底中。
7.如权利要求6所述的功函数金属栅极装置,其中该底层功函数金属层垂直覆盖该第一绝缘结构以及该第二绝缘结构之间的空隙。
8.如权利要求6所述的功函数金属栅极装置,还包含:
第一漂移区,设置于该栅极的一部分下方的该基底中,且该漏极以及该第二绝缘结构位于该第一漂移区中,其中该顶层功函数金属层垂直重叠该第一漂移区以及该漂移区之间的空隙。
9.如权利要求3所述的功函数金属栅极装置,其中该第一阶梯状功函数金属堆叠结构垂直重叠该第一绝缘结构的一部分。
10.如权利要求3所述的功函数金属栅极装置,其中该第一阶梯状功函数金属堆叠结构的侧壁与该第一绝缘结构的侧壁切齐。
11.一种功函数金属栅极装置,包含:
栅极,设置于基底上,其中该栅极包含中凹的阶梯状功函数金属堆叠结构;
漂移区,设置于该栅极的一部分下方的该基底中;
源极,位于该基底中,以及漏极位于该栅极侧边的该漂移区中;以及
第一绝缘结构,设置于该栅极以及该漏极之间的该漂移区中。
12.如权利要求11所述的功函数金属栅极装置,其中该中凹的阶梯状功函数金属堆叠结构具有盘型阶梯状剖面结构。
13.如权利要求12所述的功函数金属栅极装置,其中该中凹的阶梯状功函数金属堆叠结构包含第一阶梯状功函数金属堆叠结构以及第二阶梯状功函数金属堆叠结构,其中该第二阶梯状功函数金属堆叠结构顺应覆盖该第一阶梯状功函数金属堆叠结构。
14.如权利要求13所述的功函数金属栅极装置,其中该第一阶梯状功函数金属堆叠结构与该第二阶梯状功函数金属堆叠结构具有不同电性。
15.如权利要求13所述的功函数金属栅极装置,其中该第一阶梯状功函数金属堆叠结构包含底层功函数金属层具有第一凹槽以及顶层功函数金属层具有第二凹槽。
16.如权利要求15所述的功函数金属栅极装置,其中该第二凹槽垂直重叠该第一凹槽。
17.如权利要求16所述的功函数金属栅极装置,其中该第一凹槽与该第二凹槽共用中线。
18.如权利要求17所述的功函数金属栅极装置,还包含:
第二绝缘结构,设置于该栅极以及该源极之间的该基底中;以及
栅极氧化层,位于该第一绝缘结构以及该第二绝缘结构之间的该基底中。
19.如权利要求18所述的功函数金属栅极装置,其中该顶层功函数金属层的该第二凹槽垂直覆盖该第一绝缘结构以及该第二绝缘结构之间的空隙。
20.如权利要求18所述的功函数金属栅极装置,还包含:
第一漂移区,设置于该栅极的一部分下方的该基底中,且该源极以及该第二绝缘结构位于该第一漂移区中,其中该底层功函数金属层的该第一凹槽垂直重叠该第一漂移区以及该漂移区之间的空隙。
CN202011244345.3A 2020-11-10 2020-11-10 功函数金属栅极装置 Pending CN114464678A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202011244345.3A CN114464678A (zh) 2020-11-10 2020-11-10 功函数金属栅极装置
US17/128,168 US11482605B2 (en) 2020-11-10 2020-12-20 Work function metal gate device
US17/945,122 US20230014945A1 (en) 2020-11-10 2022-09-15 Work function metal gate device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011244345.3A CN114464678A (zh) 2020-11-10 2020-11-10 功函数金属栅极装置

Publications (1)

Publication Number Publication Date
CN114464678A true CN114464678A (zh) 2022-05-10

Family

ID=81404557

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011244345.3A Pending CN114464678A (zh) 2020-11-10 2020-11-10 功函数金属栅极装置

Country Status (2)

Country Link
US (2) US11482605B2 (zh)
CN (1) CN114464678A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220228257A1 (en) * 2021-01-21 2022-07-21 Taiwan Semiconductor Manufacturing Company Limited Tungsten deposition on a cobalt surface

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200723407A (en) 2005-12-13 2007-06-16 St Microelectronics Crolles 2 MOS transistor with better short channel effect control and corresponding manufacturing method
US8105931B2 (en) * 2008-08-27 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating dual high-k metal gates for MOS devices
KR101783952B1 (ko) * 2011-01-12 2017-10-10 삼성전자주식회사 반도체 장치
US9583362B2 (en) 2014-01-17 2017-02-28 Taiwan Semiconductor Manufacturing Company Ltd. Metal gate structure and manufacturing method thereof
CN106663694B (zh) 2014-08-19 2021-05-25 英特尔公司 具有横向渐变功函数的晶体管栅极金属

Also Published As

Publication number Publication date
US20230014945A1 (en) 2023-01-19
US20220149171A1 (en) 2022-05-12
US11482605B2 (en) 2022-10-25

Similar Documents

Publication Publication Date Title
CN106803484B (zh) 半导体元件及其制作方法
US10068797B2 (en) Semiconductor process for forming plug
CN106683990B (zh) 半导体元件及其制作方法
CN102842491B (zh) 金属栅极的制作方法
US11139384B2 (en) Method for fabricating semiconductor device
CN105826174B (zh) 半导体装置及其制作方法
CN103515421B (zh) 半导体结构及其制作工艺
CN106409889B (zh) 半导体元件
CN110473784B (zh) 半导体元件及其制作方法
CN104425575A (zh) 金属栅极结构及其制作方法
US20230014945A1 (en) Work function metal gate device
CN102856256B (zh) 半导体元件及其制作方法
CN112736079A (zh) 具有连接pmos区域栅极结构的接触插塞的半导体元件
US10283412B2 (en) Semiconductor device and fabrication method thereof
CN110021559B (zh) 半导体元件及其制作方法
TW201714277A (zh) 半導體結構及其製造方法
TWI515830B (zh) 一種製作半導體元件的方法
TWI569333B (zh) 一種製作半導體元件的方法
US20230378167A1 (en) Semiconductor device and method of fabricating the same
US20210050441A1 (en) Semiconductor process
CN109545747B (zh) 半导体元件及其制作方法
TW201318041A (zh) 具有金屬閘極之半導體元件及其製作方法
TWI575745B (zh) Mos電晶體及其製程
CN114792682A (zh) 纳米线晶体管及其制作方法
TW202135227A (zh) 半導體元件及其製作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination