CN114449774A - Manufacturing process of conducting circuit - Google Patents
Manufacturing process of conducting circuit Download PDFInfo
- Publication number
- CN114449774A CN114449774A CN202210213231.5A CN202210213231A CN114449774A CN 114449774 A CN114449774 A CN 114449774A CN 202210213231 A CN202210213231 A CN 202210213231A CN 114449774 A CN114449774 A CN 114449774A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- conductive
- area
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000002699 waste material Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 238000005520 cutting process Methods 0.000 claims abstract description 15
- 238000010030 laminating Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 15
- 239000007822 coupling agent Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 239000011259 mixed solution Substances 0.000 claims description 6
- 239000003960 organic solvent Substances 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 4
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 claims description 3
- 239000012964 benzotriazole Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 58
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 5
- 229920000139 polyethylene terephthalate Polymers 0.000 description 5
- 239000005020 polyethylene terephthalate Substances 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 239000003921 oil Substances 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 150000004841 phenylimidazoles Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 239000003223 protective agent Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention provides a manufacturing process of a conducting circuit, which comprises the following steps: a1, providing a substrate, and planning a wiring area and a waste discharge area on the surface of the substrate; a2, covering an isolation layer on the surface of the waste discharge area of the substrate; a3, laminating the conductive layer on the surface of the substrate; a4, cutting out the circuit on the surface of the wiring area and the waste material on the surface of the waste discharge area by die cutting; and A5, removing the waste material to obtain the conductive circuit in the wiring area. Cover an isolation layer at the district surface of wasting discharge for the cohesion of conducting layer in the wasting discharge district will be less than at the cohesion of wiring district, cuts off after the cross cutting, and because of the difference of cohesion, modes such as accessible negative pressure is absorbed and is got rid of the waste material in unison, and the wasting discharge is easy, efficient, and can not influence the circuit that is located wiring district surface, and the precision obtains fine guarantee.
Description
Technical Field
The invention relates to a manufacturing process of a conducting circuit.
Background
An integrated circuit (integrated circuit) is a type of microelectronic device or component. The transistor, resistor, capacitor and inductor elements and wiring required in a circuit are interconnected together by a certain process, and are manufactured on a small semiconductor wafer or a plurality of small semiconductor wafers or medium substrates to form a micro structure with the required circuit function, such as a circuit board, an RFID tag and the like. Before assembling the electronic components, the conductive circuits need to be laid out. In the prior art, the manufacturing process of the conductive circuit comprises wet etching, printing, electroplating, vacuum plating, die cutting and the like. In the die-cutting preparation process, a circuit pattern is die-cut on the whole conductive layer (such as a copper foil layer), and then waste materials are discharged in a waste discharge mode, but the defects of difficult waste discharge, poor precision and the like generally exist.
Disclosure of Invention
Therefore, the invention provides a manufacturing process of a conducting circuit based on a die cutting process, and can well solve the problems of difficult waste discharge and poor precision.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a manufacturing process of a conducting circuit comprises the following steps:
a1, providing a substrate, and planning a wiring area and a waste discharge area on the surface of the substrate;
a2, covering an isolation layer on the surface of the waste discharge area of the substrate;
a3, laminating the conductive layer on the surface of the substrate;
a4, cutting out the circuit on the surface of the wiring area and the waste material on the surface of the waste discharge area by die cutting;
and A5, removing the waste material to obtain the conductive circuit in the wiring area.
Further, in step a2, the surface of the wiring area of the substrate is exposed, and in step A3, the conductive layer is directly bonded to the surface of the wiring area of the substrate and the surface of the isolation layer in the waste discharge area.
Further, in step a2, the method further includes covering the wiring region of the substrate with a coupling agent layer, and in step A3, the conductive layer is laminated on the surface of the coupling agent layer of the wiring region and the surface of the isolation layer located in the waste discharge region.
Further, the isolation layer is an OSP layer, specifically, the OSP is an abbreviation of Organic solder resist Preservatives, and is also called a copper-protecting agent.
Furthermore, the OSP layer is made of benzotriazole.
Further, in step a2, dissolving the OSP material in an organic solvent to obtain a mixed solution, covering the mixed solution on the surface of the waste discharge area by printing or spraying, and volatilizing and drying the organic solvent to obtain the isolation layer.
Further, in the step a3, the conductive layer is a conductive film layer made of copper foil, aluminum foil or other conductive film material, and an enhancement layer is added to the bottom of the conductive film layer.
Further, in step a5, the waste material is removed by negative pressure suction.
Further, step a5 is followed by step a6 of covering a passivation layer on the conductive lines in the wiring area.
Through the technical scheme provided by the invention, the method has the following beneficial effects:
cover an isolation layer at the district surface of wasting discharge for the cohesion of conducting layer in the wasting discharge district will be less than at the cohesion of wiring district, cuts off after the cross cutting, and because of the difference of cohesion, modes such as accessible negative pressure is absorbed and is got rid of the waste material in unison, and the wasting discharge is easy, efficient, and can not influence the circuit that is located wiring district surface, and the precision obtains fine guarantee.
Drawings
FIG. 1 is a block diagram illustrating a process for forming conductive traces according to a first embodiment;
FIG. 2 is a schematic external view of a substrate according to an embodiment;
FIG. 3 is a partial cross-sectional structural view of the product obtained in step A2 according to the first embodiment;
FIG. 4 is a partial cross-sectional view of the structure of the product obtained in step A3 according to the first embodiment;
FIG. 5 is a partial cross-sectional structural view of the product obtained in step A4 according to the first embodiment;
FIG. 6 is a partial structural sectional view of a product obtained in the step A5 according to the first embodiment.
Detailed Description
To further illustrate the various embodiments, the invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. Those skilled in the art will appreciate still other possible embodiments and advantages of the present invention with reference to these figures. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.
The invention will now be further described with reference to the accompanying drawings and detailed description.
Example one
Referring to fig. 1, the present embodiment provides a manufacturing process of a conductive circuit, including the following steps:
a1, as shown in fig. 2, providing a substrate 10, and planning a wiring area 101 and a waste area 102 on the surface of the substrate 10; in the figure, the ring position is set as a wiring area 101, and the rest positions are waste discharge areas 102.
A2, covering a separation layer 20 on the surface of the waste discharge area 102 of the substrate 10, as shown in fig. 3;
specifically, in the present embodiment, the surface of the wiring region 101 of the substrate 10 is exposed, so as to form an exposed surface;
a3, as shown in fig. 4, pressing the conductive layer 30 (specifically, the copper foil layer in this embodiment) on the surface of the substrate 10;
specifically, the conductive layer 30 is directly laminated on the surface of the wiring region 101 of the substrate 10 and the surface of the isolation layer 20 located in the waste discharge region 102.
A4, cutting the conductive layer 30 into the circuit 31 on the surface of the wiring area 101 and the waste material 32 on the surface of the waste discharge area 102 by die cutting as shown in fig. 5; specifically, the die cutting can be selected from laser cutting, knife die cutting and the like in the prior art.
Thus, since the surface of the waste discharge region 102 is covered with the isolation layer 20, the bonding force of the conductive layer 30 in the waste discharge region 102 is smaller than that in the wiring region 101.
A5, as shown in fig. 6, the waste material 32 is discharged to obtain the conductive circuit located in the wiring area 101, and the wiring 31 is the conductive circuit.
Due to the difference of the binding force, the waste 32 is easier to discharge, the circuit 31 on the surface of the wiring area 101 is not affected, and the precision is well guaranteed. Specifically, in step a5, the waste 32 is uniformly removed by negative pressure suction, which is more efficient. Of course, other means of disposal may be used.
Specifically, in the present embodiment, the substrate 10 is a structure capable of forming an adhesion with the conductive layer 30 during the lamination process, such as a PET substrate. Of course, if the substrate 10 is difficult to be directly bonded to the conductive layer 30, such as a ceramic substrate, in order to achieve bonding to the conductive layer 30, an adhesive layer may be added on the surface of the substrate 10 or at the bottom of the conductive layer 30 to facilitate pressing and bonding.
Further, in the step a3, if the conductive layer is a conductive film layer, such as a copper foil, an aluminum foil or other conductive film material with a thickness of 18 microns, the strength of the conductive layer is obviously insufficient, and the conductive layer is basically broken by pulling with hands; therefore, in this case, a reinforcing layer, such as a PET layer with a thickness of 10 μm, may be added to the bottom of the conductive film layer, i.e., the aluminum foil (or copper foil) and the PET are processed by a composite process to increase the strength.
Specifically, the isolation layer 20 is an OSP layer, specifically, in step a2, the OSP material is dissolved in an organic solvent to obtain a mixed solution, the mixed solution is covered on the surface of the waste discharge area by a printing or spraying manner, and the isolation layer is obtained after the organic solvent is volatilized and dried. The OSP layer can be formed to be nano-scale in thickness, generally 0.2-0.5 micron, and the solvent is solid after volatilization, and can not be diffused any more, and the formed circuit is clearer.
Meanwhile, after the conductive circuit is formed, the residual OSP layer can be volatilized or sublimed to be removed through the subsequent normal baking or reflow soldering heating process without adding an additional removing step; after the removal, the isolation effect is not played any more, and a resin layer can be added on the line 31 for secondary lamination or glue is applied for protection and reinforcement. More preferably, the OSP layer is made of benzotriazole which can be sublimated at 98-100 ℃, is easier to remove and has a lower removal temperature, particularly a long-term use temperature lower than that of a common material PET (polyethylene terephthalate, the long-term use temperature is below 120 ℃) of the RFID label. Of course, in other embodiments, other organic semiconductors such as alkyl imidazoles or phenyl imidazoles may be used for the OSP layer. Besides the OSP layer, other silicon oil layers made of silicon oil and the like can be adopted, and isolation can be realized; however, the effect is poor, i.e. after the step a5, an additional step of removing the isolation layer is required to remove it.
Further, step a5 is followed by step a6 of covering a passivation layer on the conductive lines in the wiring area. In this way, the line 31 can be effectively protected. Of course, in other embodiments, this is not limiting.
Example two
The manufacturing process of the conductive circuit provided in this embodiment is substantially the same as the manufacturing process provided in the first embodiment, except that: in this embodiment, step a2 further includes covering the wiring region of the substrate with a coupling agent layer, and in step A3, the conductive layer is laminated on the surface of the coupling agent layer of the wiring region and the surface of the isolation layer in the waste region. In this embodiment, a coupling agent layer is added in the wiring region, and the coupling agent can further promote the bonding between the conductive layer and the surface of the wiring region, so that the bonding is firmer.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A manufacturing process of a conducting circuit is characterized by comprising the following steps:
a1, providing a substrate, and planning a wiring area and a waste discharge area on the surface of the substrate;
a2, covering an isolation layer on the surface of the waste discharge area of the substrate;
a3, laminating the conductive layer on the surface of the substrate;
a4, cutting out the circuit on the surface of the wiring area and the waste material on the surface of the waste discharge area by die cutting;
and A5, removing the waste material to obtain the conductive circuit in the wiring area.
2. The process for forming a conductive circuit according to claim 1, wherein: in step a2, the surface of the wiring area of the substrate is exposed, and in step A3, the conductive layer is directly bonded to the surface of the wiring area of the substrate and the surface of the isolation layer in the waste discharge area.
3. The process for forming a conductive circuit according to claim 1, wherein: in step a2, the method further includes covering the wiring region of the substrate with a coupling agent layer, and in step A3, the conductive layer is laminated on the surface of the coupling agent layer of the wiring region and the surface of the isolation layer of the waste region.
4. The process for forming a conductive circuit according to claim 1, wherein: the isolation layer is an OSP layer.
5. The process for forming a conductive circuit according to claim 4, wherein: the OSP layer is made of benzotriazole.
6. The process for forming a conductive circuit according to claim 4, wherein: in the step A2, dissolving the OSP material into an organic solvent to obtain a mixed solution, covering the mixed solution on the surface of the waste discharge area in a printing or spraying mode, and volatilizing and drying the organic solvent to obtain the isolation layer.
7. The process for forming a conductive circuit according to claim 1, wherein: in step A5, the waste material is removed by suction under negative pressure.
8. The process for forming a conductive circuit according to claim 1, wherein: step a5 is followed by step a6 of covering a passivation layer over the conductive lines in the wire area.
9. The process for forming a conductive circuit according to claim 1, wherein: in the step A3, the conductive layer is a conductive film layer, and an enhancement layer is added at the bottom of the conductive film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210213231.5A CN114449774A (en) | 2022-02-28 | 2022-02-28 | Manufacturing process of conducting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210213231.5A CN114449774A (en) | 2022-02-28 | 2022-02-28 | Manufacturing process of conducting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114449774A true CN114449774A (en) | 2022-05-06 |
Family
ID=81360190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210213231.5A Pending CN114449774A (en) | 2022-02-28 | 2022-02-28 | Manufacturing process of conducting circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114449774A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004335907A (en) * | 2003-05-12 | 2004-11-25 | Fuchigami Micro:Kk | Flexible embedding circuit board and manufacturing method thereof |
| CN101794186A (en) * | 2010-03-22 | 2010-08-04 | 牧东光电（苏州）有限公司 | Processing method for induction layers of capacitive touch panel |
| KR101125356B1 (en) * | 2011-03-25 | 2012-04-02 | 엘지이노텍 주식회사 | The printed circuit board and the method for manufacturing the same |
| US20130247373A1 (en) * | 2012-03-09 | 2013-09-26 | Mitsui Mining & Smelting Co., Ltd. | Method of producing printed wiring board and copper foil for laser processing |
| CN103687344A (en) * | 2012-09-26 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board manufacturing method |
| JP2016120610A (en) * | 2014-12-24 | 2016-07-07 | サトーホールディングス株式会社 | Manufacturing device and manufacturing method of hole opening label continuous body |
| CN107911949A (en) * | 2017-11-06 | 2018-04-13 | 王国清 | A kind of wiring thin film board manufacturing method |
| CN111647362A (en) * | 2020-07-10 | 2020-09-11 | 东莞捷邦实业有限公司 | Conductive double-sided adhesive tape assembly for electronic circuit board and production process thereof |
| CN112188745A (en) * | 2020-09-30 | 2021-01-05 | 深圳光韵达激光应用技术有限公司 | Die-cutting conductor circuit manufacturing process |
| JP2021111744A (en) * | 2020-01-15 | 2021-08-02 | 日本特殊陶業株式会社 | Manufacturing method for conductive layer, manufacturing method for wiring board and manufacturing method for heater device |
| CN113199556A (en) * | 2021-04-19 | 2021-08-03 | 麦格磁电科技（珠海）有限公司 | Multilayer material die cutting processing method |
-
2022
- 2022-02-28 CN CN202210213231.5A patent/CN114449774A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004335907A (en) * | 2003-05-12 | 2004-11-25 | Fuchigami Micro:Kk | Flexible embedding circuit board and manufacturing method thereof |
| CN101794186A (en) * | 2010-03-22 | 2010-08-04 | 牧东光电（苏州）有限公司 | Processing method for induction layers of capacitive touch panel |
| KR101125356B1 (en) * | 2011-03-25 | 2012-04-02 | 엘지이노텍 주식회사 | The printed circuit board and the method for manufacturing the same |
| US20130247373A1 (en) * | 2012-03-09 | 2013-09-26 | Mitsui Mining & Smelting Co., Ltd. | Method of producing printed wiring board and copper foil for laser processing |
| CN103687344A (en) * | 2012-09-26 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board manufacturing method |
| JP2016120610A (en) * | 2014-12-24 | 2016-07-07 | サトーホールディングス株式会社 | Manufacturing device and manufacturing method of hole opening label continuous body |
| CN107911949A (en) * | 2017-11-06 | 2018-04-13 | 王国清 | A kind of wiring thin film board manufacturing method |
| JP2021111744A (en) * | 2020-01-15 | 2021-08-02 | 日本特殊陶業株式会社 | Manufacturing method for conductive layer, manufacturing method for wiring board and manufacturing method for heater device |
| CN111647362A (en) * | 2020-07-10 | 2020-09-11 | 东莞捷邦实业有限公司 | Conductive double-sided adhesive tape assembly for electronic circuit board and production process thereof |
| CN112188745A (en) * | 2020-09-30 | 2021-01-05 | 深圳光韵达激光应用技术有限公司 | Die-cutting conductor circuit manufacturing process |
| CN113199556A (en) * | 2021-04-19 | 2021-08-03 | 麦格磁电科技（珠海）有限公司 | Multilayer material die cutting processing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7639473B2 (en) | Circuit board structure with embedded electronic components | |
| KR101348748B1 (en) | Method for manufacturing a semiconductor package using a pad redistribution substrate | |
| US20090084494A1 (en) | Substrate manufacturing method | |
| JP2011199077A (en) | Method of manufacturing multilayer wiring board | |
| US8841763B2 (en) | Three-dimensional system-in-a-package | |
| CN106550554B (en) | Protective structure for manufacturing a component carrier with a dummy core and two sheets of different materials thereon | |
| KR101055495B1 (en) | Carrier member for substrate manufacturing and substrate manufacturing method using same | |
| US9661759B2 (en) | Printed circuit board and method of manufacturing the same | |
| CN114449774A (en) | Manufacturing process of conducting circuit | |
| CN108172561B (en) | Bearing substrate, packaging structure thereof and manufacturing method of semiconductor packaging element | |
| JP2006005097A (en) | Process for fabricating circuit module | |
| EP3443584B1 (en) | Batch manufacturing of component carriers and their related semi-finished product | |
| JP5302927B2 (en) | Manufacturing method of multilayer wiring board | |
| KR100730763B1 (en) | Substrate with multi-layer interconnection structure and method of manufacturing the same | |
| KR101441466B1 (en) | Ultra-thin package board and manufacturing method thereof | |
| KR20180004421A (en) | Method of manufacturing a circuit board having a cavity | |
| KR101119380B1 (en) | A carrier member for manufacturing a substrate and a method of manufacturing a substrate using the same | |
| JP2006019425A (en) | Circuit module and its manufacturing method | |
| CN110545636B (en) | Circuit board and manufacturing method thereof | |
| CN112492777B (en) | Circuit board and manufacturing method thereof | |
| JP7443689B2 (en) | Manufacturing method of electronic component built-in board | |
| KR101044123B1 (en) | A carrier member for manufacturing a substrate and a method of manufacturing a substrate using the same | |
| JP2005109068A (en) | Semiconductor device and manufacturing method thereof | |
| KR101898479B1 (en) | Method of manufacturing printed circuit board using multi carrier substrates | |
| EP3001783A1 (en) | Component-embedded substrate and manufacturing method for same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20240618 Address after: Room 105, block a, Jianye Building, No.96, Xiangxing Road, industrial zone, Xiamen Torch hi tech Zone (Xiang'an), Xiamen City, Fujian Province, 361000 Applicant after: Xiamen craftsman welding new material technology Co.,Ltd. Country or region after: China Address before: 361022 301, No. 3, Xilin Xili, Siming District, Xiamen City, Fujian Province Applicant before: Xiamen Jiangyan New Material Technology Co.,Ltd. Country or region before: China |