CN114421438B - Predictive fault protection device and method for direct current solid state circuit breaker - Google Patents
Predictive fault protection device and method for direct current solid state circuit breaker Download PDFInfo
- Publication number
- CN114421438B CN114421438B CN202210029037.1A CN202210029037A CN114421438B CN 114421438 B CN114421438 B CN 114421438B CN 202210029037 A CN202210029037 A CN 202210029037A CN 114421438 B CN114421438 B CN 114421438B
- Authority
- CN
- China
- Prior art keywords
- circuit
- resistor
- current
- source
- short
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000007787 solid Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000005070 sampling Methods 0.000 claims abstract description 81
- 230000003071 parasitic effect Effects 0.000 claims abstract description 52
- 238000012545 processing Methods 0.000 claims abstract description 46
- 208000033707 Early-onset X-linked optic atrophy Diseases 0.000 claims description 17
- 208000025019 optic atrophy 2 Diseases 0.000 claims description 17
- 230000008859 change Effects 0.000 claims description 15
- 101150110971 CIN7 gene Proteins 0.000 claims description 12
- 101150110298 INV1 gene Proteins 0.000 claims description 12
- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 claims description 12
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 claims description 12
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 12
- TVEXGJYMHHTVKP-UHFFFAOYSA-N 6-oxabicyclo[3.2.1]oct-3-en-7-one Chemical compound C1C2C(=O)OC1C=CC2 TVEXGJYMHHTVKP-UHFFFAOYSA-N 0.000 claims description 3
- 101100172279 Paenibacillus polymyxa endR gene Proteins 0.000 claims 2
- 241000208340 Araliaceae Species 0.000 claims 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims 1
- 235000003140 Panax quinquefolius Nutrition 0.000 claims 1
- 101150012763 endA gene Proteins 0.000 claims 1
- 235000008434 ginseng Nutrition 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/22—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for distribution gear, e.g. bus-bar systems; for switching devices
- H02H7/222—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for distribution gear, e.g. bus-bar systems; for switching devices for switches
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/05—Details with means for increasing reliability, e.g. redundancy arrangements
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/087—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current for dc applications
Landscapes
- Protection Of Static Devices (AREA)
Abstract
A predictive fault protection device and protection method for a direct current solid state circuit breaker includes: the device comprises a source parasitic inductance sampling circuit, a load capacitance sampling circuit and a logic processing circuit, wherein the source parasitic inductance sampling circuit and the load capacitance sampling circuit are connected with the logic processing circuit; the source parasitic inductance sampling circuit, the logic processing circuit and the load capacitance sampling circuit are also connected with a main power circuit where the direct current solid state circuit breaker is located; the source parasitic inductance sampling circuit is used for sampling voltage and current on a source parasitic inductance of an MOS tube of the direct current solid state circuit breaker in the main power loop; by combining with other structures and methods, the defects that the short-circuit time of the SiC device often exceeds the short-circuit bearing time and the current overshoot caused by capacitive load and the SiC device is not suitable for the direct-current solid-state circuit breaker due to the fact that the corresponding fault speed of the short-circuit protection method for the direct-current solid-state circuit breaker in the prior art is too long are effectively avoided.
Description
Technical Field
The invention relates to the technical field of power electronics and electrician, in particular to a short-circuit fault protection circuit suitable for a direct-current solid-state circuit breaker, and particularly relates to a predictive fault protection device and a protection method for the direct-current solid-state circuit breaker, and in particular relates to a protection circuit and a protection method for improving the safety reliability of the direct-current solid-state circuit breaker and preventing misjudgment of the direct-current solid-state circuit breaker.
Background
As the power electronics technology continues to advance, the dc solid state circuit breaker also gradually rises, and the basic topology is shown in fig. 1. Dc solid state circuit breakers employing thyristor turn-off have emerged in the 70 s of the 20 th century; in the 80 s, with the advent of fully controlled devices such as gate turn-off thyristors (GTO), insulated Gate Bipolar Transistors (IGBT) and the like, new choices are made for devices used by the direct current solid state circuit breaker. That is, the direct current solid state circuit breaker will adopt a SiC device, which has wider forbidden bandwidth, higher thermal conductivity, higher critical field strength and faster electron migration rate than a Si device, and has obvious advantages in high temperature and pressure resistance, high frequency application and the like, and is suitable for high-speed and high-power application occasions.
However, in practical application, on one hand, a power device such as a dc solid state circuit breaker employing a SiC device inevitably works in an abnormal working state such as overload and short circuit, and a certain delay exists in the detection of the action of the protection circuit, which requires that the power device such as the dc solid state circuit breaker employing the SiC device has certain overload and short circuit capabilities, i.e. can bear certain fault time. Meanwhile, the corresponding protection circuit must clear the fault within the fault time that the power device such as the direct current solid state circuit breaker adopting the SiC device can bear, so as to avoid the damage of the power device such as the direct current solid state circuit breaker adopting the SiC device. On the other hand, due to the structure of the device, the thickness of the oxide layer of the grid electrode of the SiC MOSFET is thinner than that of the Si MOSFET, and the stability of the interface of the oxide layer is lower when a short circuit fault occurs, so that the SiC MOSFET is not beneficial to long-term reliable operation. In addition, the SiC MOSFET has small die area and large current density, has weaker short-circuit capability and shorter short-circuit bearing time, and brings great challenges to the design of the short-circuit protection of the SiC MOSFET. When the load of the power converter is a capacitive load, current overshoot often occurs, which causes the current to exceed a threshold set by the short-circuit protection circuit, but the circuit is not in a short-circuit condition at this time, which may cause the short-circuit protection circuit to malfunction.
The traditional short-circuit protection method aiming at the direct-current solid-state circuit breaker comprises the methods of current Hall detection, sampling resistance detection, parasitic inductance detection and the like, but the short-circuit time of the SiC device possibly exceeds the short-circuit bearing time due to the overlong corresponding speed of faults; current overshoot due to capacitive loading is a factor that many protection circuits do not consider at present, so the traditional short-circuit protection method for the direct current solid state circuit breaker is not suitable for the SiC device of the direct current solid state circuit breaker.
Disclosure of Invention
In order to solve the problems, the invention provides a predictive fault protection device and a predictive fault protection method for a direct current solid state circuit breaker, which effectively avoid the defects that the short circuit time of a SiC device often exceeds the short circuit bearing time of the SiC device and the current overshoot is caused by capacitive load and the SiC device is not suitable for the direct current solid state circuit breaker because of the overlong fault corresponding speed of the short circuit protection method for the direct current solid state circuit breaker in the prior art. The safety and reliability of the direct-current solid-state circuit breaker are improved, and meanwhile, the protection circuit for preventing misjudgment of the direct-current solid-state circuit breaker is realized.
To overcome the defects in the prior art, the invention provides a solution of a predictive fault protection device and method for a direct current solid state circuit breaker, which comprises the following specific steps:
a predictive fault protection device for a dc solid state circuit breaker, comprising:
a source parasitic inductance sampling circuit, a load capacitance sampling circuit and a logic processing circuit,
the source parasitic inductance sampling circuit and the load capacitance sampling circuit are both connected with the logic processing circuit;
the source parasitic inductance sampling circuit, the logic processing circuit and the load capacitance sampling circuit are also connected with a main power circuit where the direct current solid state circuit breaker is located;
the source parasitic inductance sampling circuit is used for sampling the voltage and the current on the source parasitic inductance of the MOS tube of the direct current solid-state circuit breaker in the main power loop and judging whether the circuit has a short circuit state or not;
the capacitive load sampling circuit is used for sampling the voltage on the capacitive load and judging whether a short circuit condition occurs or the capacitive turn-on current is overlarge when the main power loop is turned on;
the logic processing circuit is used for processing signals transmitted by the source parasitic inductance sampling circuit, the capacitive load sampling circuit and the control signal source PWM, judging whether a main power loop where the direct current solid state circuit breaker is located is short-circuited or not, and transmitting driving signals to MOS tubes of the direct current solid state circuit breaker.
Further, the source parasitic inductance sampling circuitComprising the following steps: first operational amplifier U OPA1 Second operational amplifier U OPA2 First comparator U COMP1 A first resistor R 1 A second resistor R 2 Third resistor R 3 Fourth resistor R 4 Fifth resistor R 5 Sixth resistor R 6 Seventh resistor R 7 And a first reference voltage source U ref1 ；
First operational amplifier U OPA1 Is a non-inverting input terminal of (1), a first resistor R 1 And a second resistor R 2 Is connected with one end of a first resistor R 1 The other end of the transistor is connected with a parasitic inductance L of the source electrode of the MOS transistor S Is a member of the group; first operational amplifier U OPA1 Is connected with a third resistor R 3 One end of (3) a third resistor R 3 The other end of the first part is connected with a reference ground; first operational amplifier U OPA1 Output terminal of (2), second resistor R 2 And a fifth resistor R 5 Is connected with one end of the connecting rod; second operational amplifier U OPA2 A non-inverting input terminal of (a), a fourth resistor R 4 And the other end, the fifth resistor R 5 And a seventh resistor R 7 One end of the fourth resistor R is connected to 4 The other end of the transistor is connected with a parasitic inductance L of the source electrode of the MOS transistor S Is a member of the group; second operational amplifier U OPA2 The inverting input terminal of (a) is connected with a sixth resistor R 6 A sixth resistor R 6 The other end of which is connected with a reference ground; second operational amplifier U OPA2 Output terminal of (d), seventh resistor R 7 And the other end of the first comparator U COMP1 Is connected with the positive input end of the power supply; first comparator U COMP1 Is connected with a first reference voltage source U ref1 A first reference voltage source U ref1 Is connected to a reference ground; first comparator U COMP1 Output terminal of (2) 1 First OR gate U connected with logic processing circuit OR1 Is provided.
Further, the capacitive load sampling circuit includes: third operational amplifier U OPA3 Second comparator U COMP2 Eighth resistor R 8 Ninth resistor R 9 Tenth resistor R 10 And (d)Two reference voltage sources U ref2 ；
Third operational amplifier U OPA3 In-phase input terminal of (2), eighth resistor R 8 And a tenth resistor R 10 One end of the eighth resistor R is connected to 8 The other end of (2) is connected with a load resistor R L Is a member of the group; third operational amplifier U OPA3 The inverting input terminal of (a) is connected with a ninth resistor R 9 A ninth resistor R 9 The other end of the first part is connected with a reference ground; third operational amplifier U OPA3 Output terminal of (2), tenth resistor R 10 And a second comparator U COMP2 Is connected with the non-inverting input end of the power supply; second comparator U COMP2 Is connected with a second reference voltage source U ref2 The positive electrode of the second reference voltage source U ref2 Is connected to a reference ground; second comparator U COMP2 The output end of (a) is connected with a first inverter U of a logic processing circuit INV1 Is provided.
The logic processing circuit includes: first inverter U INV1 First OR gate U OR1 First AND gate U AND1 And a control signal source PWM;
first inverter U INV1 The output end of (a) is connected with a first OR gate U OR1 Is connected to the second input terminal of the first circuit; first OR gate U OR1 The output end of (a) is connected with a first AND gate U AND1 Is connected to the first input terminal of the first circuit; first AND gate U AND1 The second input end of the control signal source PWM is connected with the control signal source PWM; output terminal U of first AND gate AND1 Is connected with the grid electrode of the MOS tube.
A protection method for a predictive fault protection device for a direct current solid state circuit breaker, comprising:
when the main power loop is detected, the source parasitic inductance sampling circuit samples the source parasitic inductance L of the MOS tube S Current i and voltage drop U over L Sampling, pressure drop U L After the signal is input into the source parasitic inductance sampling circuit, the signal is amplified by the first operational amplifier U OPA1 A first resistor R 1 A second resistor R 2 And a third resistor R 3 A level shift circuit for converting the voltage drop signal U L Converting into a current change rate di/dt; electric currentThe signal i and the current change rate signal di/dt are passed through a second operational amplifier U OPA2 Fourth resistor R 4 Fifth resistor R 5 Sixth resistor R 6 And a seventh resistor R 7 The combined summing circuit is combined into a predicted current value signal; then the predicted current value signal passes through the first comparator U COMP1 And a first reference voltage source U ref1 First short circuit judgment circuit and first reference voltage source U ref1 Representing the self-set short-circuit current value I ref Predicted current value and short-circuit current value I ref Comparing, if the current predicted value exceeds the set short-circuit current value I ref Judging that the first voltage source U is short-circuited ref1 Output of (2) a high level, otherwise the first reference voltage source U ref1 The output end of the (a) outputs a low level;
the load capacitance sampling circuit samples the current I on the capacitive load by CO Sampling the current signal I CO The input is provided with a third operational amplifier U OPA2 Eighth resistor R 8 Ninth resistor R 9 And a tenth resistor R 10 Level shifter circuit for converting current signal I CO Converting into a voltage change rate signal du/dt; the voltage change rate signal du/dt is input to the second comparator U COMP2 And a second reference voltage source U ref2 And if the circuit is short-circuited, the voltage change rate signal du/dt is smaller than 0, the second short-circuit fault judging circuit outputs a low level, and if the current peak value caused by the capacitive load is larger than 0, the second short-circuit fault judging circuit outputs a high level.
Further, an output signal of the source parasitic inductance sampling circuit is connected to a first OR gate U in the logic processing circuit OR1 The output signal of the capacitive load sampling circuit passes through the first inverter U of the logic processing circuit INV1 Then, access the first OR gate U OR1 Is connected to the second input terminal of the first circuit; the source parasitic inductance sampling circuit and the capacitive load sampling circuit both output high level, the logic processing circuit judges that no short circuit fault occurs, and the grid electrode of the MOS tube receives the high level;first OR gate U OR1 The first input end of the MOS transistor is changed into a low level, the logic processing circuit judges that the capacitive current overshoot condition occurs but no short circuit fault occurs, and the grid electrode of the MOS transistor receives a high level; first OR gate U OR1 The first input end and the second input end of the MOS transistor are changed into low level, the logic processing circuit judges that the circuit has short circuit fault, and the grid electrode of the MOS transistor receives the low level and is turned off.
The beneficial effects of the invention are as follows:
(1) Based on a current prediction method, damage of the direct current solid state circuit breaker caused by overlarge short-circuit current is prevented;
(2) Based on the voltage prediction method, misjudgment of the direct-current solid-state circuit breaker caused by capacitive load opening current is prevented.
The defects that the short circuit time of the SiC device often exceeds the short circuit bearing time and the current overshoot caused by capacitive load and the SiC device is not suitable for the direct current solid state circuit breaker due to the overlong fault corresponding speed of the short circuit protection method for the direct current solid state circuit breaker in the prior art are effectively avoided.
Drawings
FIG. 1 is a topology of a main power loop and fault protection device of the present invention;
FIG. 2 is a waveform diagram of MOS transistor current during normal on and short circuit fault in the present invention;
FIG. 3 is a graph of capacitive load voltage waveforms at normal on and short circuit failure in the present invention;
FIG. 4 is a signal diagram of a logic processing circuit in normal on state in the present invention;
FIG. 5 is a signal diagram of a logic processing circuit during capacitive current overshoot in accordance with the present invention;
fig. 6 is a signal diagram of a logic processing circuit in the case of a short-circuit fault in the present invention.
Detailed Description
The invention will be further described with reference to the drawings and examples.
As shown in fig. 1 to 6, a predictive fault protection device for a direct current solid state circuit breaker includes:
a source parasitic inductance sampling circuit, a load capacitance sampling circuit and a logic processing circuit,
the source parasitic inductance sampling circuit and the load capacitance sampling circuit are both connected with the logic processing circuit;
the source parasitic inductance sampling circuit, the logic processing circuit and the load capacitance sampling circuit are also connected with a main power circuit where the direct current solid state circuit breaker is located;
the source parasitic inductance sampling circuit is used for sampling the voltage and the current on the source parasitic inductance of the MOS tube of the direct current solid-state circuit breaker in the main power loop and judging whether the circuit has a short circuit state or not; the MOS tube of the direct current solid state breaker is the SiC MOSFET of the direct current solid state breaker. The main power loop generally comprises MOS tubes of direct current solid state circuit breakers, parasitic inductance of source electrodes of the MOS tubes and a direct current voltage source U which are connected in series dc And capacitive load, the parasitic inductance of the MOS tube source electrode is the parasitic inductance L connected in series with the MOS tube source electrode S Capacitive loads generally include a load resistor R L And is connected in parallel with the load resistor R L Load capacitance C on L The method comprises the steps of carrying out a first treatment on the surface of the DC voltage source U dc Is connected with the drain electrode of the MOS tube.
The capacitive load sampling circuit is used for sampling the voltage on the capacitive load and judging whether a short circuit condition occurs or the capacitive turn-on current is overlarge when the main power loop is turned on;
the logic processing circuit is used for processing signals transmitted by the source parasitic inductance sampling circuit, the capacitive load sampling circuit and the control signal source PWM, judging whether a main power loop where the direct current solid state circuit breaker is located is short-circuited or not, and transmitting driving signals to MOS tubes of the direct current solid state circuit breaker. The control signal source PWM may continuously output a high level.
The source parasitic inductance sampling circuit comprises a first operational amplifier, a second operational amplifier, a first comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a first reference voltage source; the load capacitance sampling circuit comprises a third operational amplifier, a second comparator, an eighth resistor, a ninth resistor, a tenth resistor and a second reference voltage source; the logic processing circuit comprises a first inverter, a first OR gate, a first AND gate and a control signal source; the main power loop comprises a direct-current voltage source, an MOS tube source parasitic inductance, a load resistor and a load capacitor. The following description is made:
the source parasitic inductance sampling circuit includes: first operational amplifier U OPA1 Second operational amplifier U OPA2 First comparator U COMP1 A first resistor R 1 A second resistor R 2 Third resistor R 3 Fourth resistor R 4 Fifth resistor R 5 Sixth resistor R 6 Seventh resistor R 7 And a first reference voltage source U ref1 ；
Wherein, the first operational amplifier U OPA1 Is a non-inverting input terminal of (1), a first resistor R 1 And a second resistor R 2 Is connected with one end of a first resistor R 1 The other end of the transistor is connected with a parasitic inductance L of the source electrode of the MOS transistor S Is a member of the group; first operational amplifier U OPA1 Is connected with a third resistor R 3 One end of (3) a third resistor R 3 The other end of the first part is connected with a reference ground; first operational amplifier U OPA1 Output terminal of (2), second resistor R 2 And a fifth resistor R 5 Is connected with one end of the connecting rod; second operational amplifier U OPA2 A non-inverting input terminal of (a), a fourth resistor R 4 And the other end, the fifth resistor R 5 And a seventh resistor R 7 One end of the fourth resistor R is connected to 4 The other end of the transistor is connected with a parasitic inductance L of the source electrode of the MOS transistor S Is a member of the group; second operational amplifier U OPA2 The inverting input terminal of (a) is connected with a sixth resistor R 6 A sixth resistor R 6 The other end of which is connected with a reference ground; second operational amplifier U OPA2 Output terminal of (d), seventh resistor R 7 And the other end of the first comparator U COMP1 Is connected with the positive input end of the power supply; first comparator U COMP1 Is connected with a first reference voltage source U ref1 A first reference voltage source U ref1 Is connected to a reference ground; first comparator U COMP1 Output terminal of (2) 1 First OR gate U connected with logic processing circuit OR1 Is connected to the first input terminal of (a)。
The capacitive load sampling circuit includes: third operational amplifier U OPA3 Second comparator U COMP2 Eighth resistor R 8 Ninth resistor R 9 Tenth resistor R 10 And a second reference voltage source U ref2 ；
Third operational amplifier U OPA3 In-phase input terminal of (2), eighth resistor R 8 And a tenth resistor R 10 One end of the eighth resistor R is connected to 8 The other end of (2) is connected with a load resistor R L Is a member of the group; third operational amplifier U OPA3 The inverting input terminal of (a) is connected with a ninth resistor R 9 A ninth resistor R 9 The other end of the first part is connected with a reference ground; third operational amplifier U OPA3 Output terminal of (2), tenth resistor R 10 And a second comparator U COMP2 Is connected with the non-inverting input end of the power supply; second comparator U COMP2 Is connected with a second reference voltage source U ref2 The positive electrode of the second reference voltage source U ref2 Is connected to a reference ground; second comparator U COMP2 The output end of (a) is connected with a first inverter U of a logic processing circuit INV1 Is provided.
The logic processing circuit includes: first inverter U INV1 First OR gate U OR1 First AND gate U AND1 And a control signal source PWM;
first inverter U INV1 The output end of (a) is connected with a first OR gate U OR1 Is connected to the second input terminal of the first circuit; first OR gate U OR1 The output end of (a) is connected with a first AND gate U AND1 Is connected to the first input terminal of the first circuit; first AND gate U AND1 The second input end of the control signal source PWM is connected with the control signal source PWM; output terminal U of first AND gate AND1 Is connected with the grid electrode of the MOS tube.
A protection method for a predictive fault protection device for a dc solid state circuit breaker, the method being analyzed in particular in connection with fig. 2, 3, 4, 5, 6, comprising:
when the main power loop is detected, the source parasitic inductance sampling circuit samples the source parasitic inductance L of the MOS tube S Current i and voltage drop U over L Sampling, pressure drop U L After the signal is input into the source parasitic inductance sampling circuit, the signal is amplified by the first operational amplifier U OPA1 A first resistor R 1 A second resistor R 2 And a third resistor R 3 A level shift circuit for converting the voltage drop signal U L Converting into a current change rate di/dt; the current signal i and the current change rate signal di/dt are passed through a second operational amplifier U OPA2 Fourth resistor R 4 Fifth resistor R 5 Sixth resistor R 6 And a seventh resistor R 7 The combined summing circuit is combined into a predicted current value signal; then the predicted current value signal passes through the first comparator U COMP1 And a first reference voltage source U ref1 First short circuit judgment circuit and first reference voltage source U ref1 Representing the self-set short-circuit current value I ref Predicted current value and short-circuit current value I ref Comparing, if the current predicted value exceeds the set short-circuit current value I ref Judging that the first voltage source U is short-circuited ref1 Output of (2) a high level, otherwise the first reference voltage source U ref1 The output end of the circuit breaker outputs low level, so that the situation that the short circuit current of the main power circuit where the direct current solid-state circuit breaker is overlarge is avoided;
the load capacitance sampling circuit samples the current I on the capacitive load by CO Sampling the current signal I CO The input is provided with a third operational amplifier U OPA2 Eighth resistor R 8 Ninth resistor R 9 And a tenth resistor R 10 Level shifter circuit for converting current signal I CO Converting into a voltage change rate signal du/dt; the voltage change rate signal du/dt is input to the second comparator U COMP2 And a second reference voltage source U ref2 And if the circuit is short-circuited, the voltage change rate signal du/dt is smaller than 0, the second short-circuit fault judging circuit outputs a low level, if the current peak value caused by capacitive load is larger than 0, the second short-circuit fault judging circuit outputs a high level, and the misjudgment of the direct-current solid-state circuit breaker caused by capacitive load current overshoot is avoided. Second short-circuit faultThe judging circuit outputs a low level and the second short-circuit fault judging circuit outputs a high level, namely, the output end of the second comparator outputs a low level and the output end of the second comparator outputs a high level respectively. The second short-circuit fault judging circuit outputs a low level or the second short-circuit fault judging circuit outputs a high level, that is, an output signal of the capacitive load sampling circuit.
The output signal of the source parasitic inductance sampling circuit, i.e. the first reference voltage source U ref1 The signal output by the output end of (a) is connected into a first OR gate U in a logic processing circuit OR1 The output signal of the capacitive load sampling circuit passes through the first inverter U of the logic processing circuit INV1 Then, access the first OR gate U OR1 Is connected to the second input terminal of the first circuit; under normal conditions, as shown in fig. 4, the source parasitic inductance sampling circuit and the capacitive load sampling circuit both output high level, the logic processing circuit judges that no short-circuit fault occurs, and the grid electrode of the MOS tube receives the high level; as shown in fig. 5, the first or gate U OR1 The first input end of the MOS transistor is changed into a low level, the logic processing circuit judges that the capacitive current overshoot condition occurs but no short circuit fault occurs, and the grid electrode of the MOS transistor receives a high level; when a short-circuit fault occurs, as shown in FIG. 6, a first OR gate U OR1 The first input end and the second input end of the MOS transistor are changed into low level, the logic processing circuit judges that the circuit has short circuit fault, and the grid electrode of the MOS transistor receives the low level and is turned off.
The invention aims to provide a current and voltage prediction type protection circuit suitable for a direct-current solid-state circuit breaker, and particularly provides a protection circuit and a protection method for preventing misjudgment of the direct-current solid-state circuit breaker while improving the safety and reliability of the direct-current solid-state circuit breaker.
The present invention has been described above by way of illustration of the embodiments, and it will be apparent to those skilled in the art that the present disclosure is not limited to the embodiments described above, but is capable of various modifications, alterations and substitutions without departing from the scope of the present invention.
Claims (5)
1. A predictive fault protection device for a dc solid state circuit breaker, comprising:
a source parasitic inductance sampling circuit, a load capacitance sampling circuit and a logic processing circuit,
the source parasitic inductance sampling circuit and the load capacitance sampling circuit are both connected with the logic processing circuit;
the source parasitic inductance sampling circuit, the logic processing circuit and the load capacitance sampling circuit are also connected with a main power circuit where the direct current solid state circuit breaker is located;
the source parasitic inductance sampling circuit is used for sampling the voltage and the current on the source parasitic inductance of the MOS tube of the direct current solid-state circuit breaker in the main power loop and judging whether the circuit has a short circuit state or not;
the load capacitance sampling circuit is used for sampling the voltage on the capacitive load and judging whether the short circuit condition occurs or the capacitive opening current is overlarge when the main power loop is opened;
the logic processing circuit is used for processing signals transmitted by the source parasitic inductance sampling circuit, the capacitive load sampling circuit and the control signal source PWM, judging whether a main power loop where the direct current solid state circuit breaker is positioned is short-circuited or not, and transmitting a driving signal to an MOS tube of the direct current solid state circuit breaker;
the source parasitic inductance sampling circuit includes: first operational amplifier U OPA1 Second operational amplifier U OPA2 First comparator U COMP1 First resistorR 1 A second resistorR 2 Third resistorR 3 Fourth resistorR 4 Fifth resistorR 5 Sixth resistorR 6 Seventh resistorR 7 And a first reference voltage sourceU ref1 ；
First operational amplifier U OPA1 Is a non-inverting input terminal, a first resistorR 1 And a second resistorR 2 Is connected with one end of a first resistorR 1 The other end of the transistor is connected with a parasitic inductance of the source electrode of the MOS tubeL S Is a member of the group; first operational amplifier U OPA1 Is connected with a third resistorR 3 One end of (2)Third resistorR 3 The other end of the first part is connected with a reference ground; first operational amplifier U OPA1 Output terminal of (2), second resistorR 2 And a fifth resistor at the other endR 5 Is connected with one end of the connecting rod; second operational amplifier U OPA2 A non-inverting input terminal of (a) a fourth resistorR 4 And the other end, the fifth resistorR 5 And a seventh resistor at the other endR 7 One end of the fourth resistor is connected toR 4 The other end of the transistor is connected with a parasitic inductance of the source electrode of the MOS tubeL S Is a member of the group; second operational amplifier U OPA2 The inverting input terminal of (2) is connected with a sixth resistorR 6 A sixth resistorR 6 The other end of which is connected with a reference ground; second operational amplifier U OPA2 Output terminal of (c), seventh resistorR 7 And the other end of the first comparator U COMP1 Is connected with the positive input end of the power supply; first comparator U COMP1 Is connected with a first reference voltage sourceU ref1 A positive electrode of a first reference voltage sourceU ref1 Is connected to a reference ground; first comparator U COMP1 The output end of (a) is connected with a first OR gate U of a logic processing circuit OR1 Is provided.
2. The predictive failure protection apparatus for a dc solid state circuit breaker of claim 1, wherein the capacitive load sampling circuit comprises: third operational amplifier U OPA3 Second comparator U COMP2 Eighth resistorR 8 Ninth resistorR 9 Tenth resistorR 10 And a second reference voltage sourceU ref2 ；
Third operational amplifier U OPA3 Is the same as the input end of the first resistorR 8 And a tenth resistorR 10 Is connected with one end of an eighth resistorR 8 The other end of (2) is connected with a load resistor R L Is a member of the group; third operational amplifier U OPA3 The inverting input terminal of (2) is connected with the ninth resistorR 9 A ninth resistorR 9 Is connected with the ginseng at the other endA test field; third operational amplifier U OPA3 Output terminal of (c), tenth resistorR 10 And a second comparator U COMP2 Is connected with the non-inverting input end of the power supply; second comparator U COMP2 Is connected with a second reference voltage sourceU ref2 Is a positive electrode of a second reference voltage sourceU ref2 Is connected to a reference ground; second comparator U COMP2 The output end of (a) is connected with a first inverter U of a logic processing circuit INV1 Is provided.
3. The predictive failure protection apparatus for a dc solid state circuit breaker of claim 1, wherein the logic processing circuit comprises: first inverter U INV1 First OR gate U OR1 First AND gate U AND1 And a control signal source PWM;
first inverter U INV1 The output end of (a) is connected with a first OR gate U OR1 Is connected to the second input terminal of the first circuit; first OR gate U OR1 The output end of (a) is connected with a first AND gate U AND1 Is connected to the first input terminal of the first circuit; first AND gate U AND1 The second input end of the control signal source PWM is connected with the control signal source PWM; output terminal U of first AND gate AND1 Is connected with the grid electrode of the MOS tube.
4. A protection method for a predictive fault protection device for a direct current solid state circuit breaker, comprising:
when the main power loop is detected, the source parasitic inductance sampling circuit samples the source parasitic inductance of the MOS tubeL S Current oniAnd pressure dropU L Sampling, pressure dropU L After the signal is input into the source parasitic inductance sampling circuit, the signal is amplified by the first operational amplifier U OPA1 First resistorR 1 A second resistorR 2 And a third resistorR 3 Level shifting circuit for shifting voltage drop signalU L Converting into a current change rate di/dt; current signaliAnd the current change rate signal di/dt is passed through the second operational amplifier U OPA2 Fourth resistorR 4 Fifth electricityResistance resistorR 5 Sixth resistorR 6 And a seventh resistorR 7 The combined summing circuit is combined into a predicted current value signal; then the predicted current value signal passes through the first comparator U COMP1 And a first reference voltage sourceU ref1 First short circuit judging circuit and first reference voltage sourceU ref1 Representing the value of the self-set short-circuit currentI ref Predicting current value and short-circuit current valueI ref Comparing, if the current predicted value exceeds the set short-circuit current valueI ref Judging that the first voltage source is short-circuitedU ref1 Output of high level, otherwise the first reference voltage sourceU ref1 The output end of the (a) outputs a low level;
load capacitance sampling circuit through the current on capacitive loadI CO Sampling the current signalI CO The input is provided with a third operational amplifier U OPA3 Eighth resistorR 8 Ninth resistorR 9 And a tenth resistorR 10 Level shifter circuit for converting current signalI CO Converting into a voltage change rate signal du/dt; the voltage change rate signal du/dt is input to the second comparator U COMP2 And a second reference voltage sourceU ref2 And if the circuit is short-circuited, the voltage change rate signal du/dt is smaller than 0, the second short-circuit fault judging circuit outputs a low level, and if the current peak value caused by the capacitive load is larger than 0, the second short-circuit fault judging circuit outputs a high level.
5. The protection method of predictive failure protection apparatus for a DC solid state circuit breaker as recited in claim 4, wherein an output signal of the source parasitic inductance sampling circuit is coupled to a first OR gate U in the logic processing circuit OR1 The output signal of the capacitive load sampling circuit passes through the first inverter U of the logic processing circuit INV1 Then, access the first OR gate U OR1 Is connected to the second input terminal of the first circuit; source electrode mailerThe inductance generating sampling circuit and the capacitive load sampling circuit both output high level, the logic processing circuit judges that no short circuit fault occurs, and the grid electrode of the MOS tube receives the high level; first OR gate U OR1 The first input end of the MOS transistor is changed into a low level, the logic processing circuit judges that the capacitive current overshoot condition occurs but no short circuit fault occurs, and the grid electrode of the MOS transistor receives a high level; first OR gate U OR1 The first input end and the second input end of the MOS transistor are changed into low level, the logic processing circuit judges that the circuit has short circuit fault, and the grid electrode of the MOS transistor receives the low level and is turned off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210029037.1A CN114421438B (en) | 2022-01-11 | 2022-01-11 | Predictive fault protection device and method for direct current solid state circuit breaker |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210029037.1A CN114421438B (en) | 2022-01-11 | 2022-01-11 | Predictive fault protection device and method for direct current solid state circuit breaker |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114421438A CN114421438A (en) | 2022-04-29 |
| CN114421438B true CN114421438B (en) | 2023-12-01 |
Family
ID=81273940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210029037.1A Active CN114421438B (en) | 2022-01-11 | 2022-01-11 | Predictive fault protection device and method for direct current solid state circuit breaker |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114421438B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117394270B (en) * | 2023-12-12 | 2024-04-16 | 杭州飞仕得科技股份有限公司 | Overcurrent protection circuit and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027011A (en) * | 2016-05-23 | 2016-10-12 | 南京航空航天大学 | Current detection method based on parasitic inductance and application of current detection method |
| CN111435834A (en) * | 2019-01-12 | 2020-07-21 | 上海航空电器有限公司 | Capacitive load and load short circuit identification system and method for direct current solid-state power controller |
| CN111585553A (en) * | 2020-04-29 | 2020-08-25 | 连云港灌源科技有限公司 | Short-circuit protection structure and protection method for wide bandgap semiconductor SiC MOSFET |
-
2022
- 2022-01-11 CN CN202210029037.1A patent/CN114421438B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027011A (en) * | 2016-05-23 | 2016-10-12 | 南京航空航天大学 | Current detection method based on parasitic inductance and application of current detection method |
| CN111435834A (en) * | 2019-01-12 | 2020-07-21 | 上海航空电器有限公司 | Capacitive load and load short circuit identification system and method for direct current solid-state power controller |
| CN111585553A (en) * | 2020-04-29 | 2020-08-25 | 连云港灌源科技有限公司 | Short-circuit protection structure and protection method for wide bandgap semiconductor SiC MOSFET |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114421438A (en) | 2022-04-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN211930609U (en) | SiC MOSFET short-circuit protection circuit based on short-circuit current suppression | |
| CN106556791B (en) | High-power IGBT dynamic test circuit and control method thereof | |
| CN111244883B (en) | SiC MOSFET short-circuit protection circuit and protection method for comprehensively comparing grid charge and voltage | |
| CN109375087B (en) | Protection circuit and method for detecting IGBT short-circuit fault at high speed | |
| CN109698611B (en) | Multi-stage grid voltage reduction type SiC-MOSFET drive circuit | |
| Cui et al. | Monolithic GaN half-bridge stages with integrated gate drivers for high temperature DC-DC buck converters | |
| Luo et al. | Modern IGBT gate driving methods for enhancing reliability of high-power converters—An overview | |
| CN114421438B (en) | Predictive fault protection device and method for direct current solid state circuit breaker | |
| CN111656686B (en) | Protection of field effect transistors operating in switching mode against overload currents | |
| CN110572011B (en) | IGBT drive circuit soft switching device with short-circuit protection | |
| CN112946517A (en) | Rapid high-power SiC MOSFET short-circuit fault detection circuit and detection method | |
| CN112865767B (en) | Circuit for improving response speed of short circuit fault of SiC MOSFET device | |
| CN212085806U (en) | Overcurrent protection device for current converter | |
| CN110535335B (en) | Method and system for controlling switching device in energy discharge circuit | |
| CN112953174B (en) | Clamping active driving circuit for inhibiting SiC MOSFET crosstalk based on dv/dt detection | |
| CN111628482B (en) | Current converter overcurrent protection device and method | |
| CN112290920B (en) | Driving system and method for dynamically adjusting gate voltage | |
| CN107979073A (en) | For the low-power consumption short-circuit protection circuit of DC/DC converters and guard method | |
| CN113938118A (en) | Desaturation short-circuit protection circuit, power device short-circuit protection circuit and test circuit | |
| Li et al. | Short-circuit Protection Circuit of SiC MOSFET Based on Drain-source Voltage Integral | |
| CN220525956U (en) | Solid state circuit breaker fault detection device and solid state circuit breaker comprising same | |
| CN116990655B (en) | Transistor short circuit detection circuit and method based on drain-source voltage change rate | |
| CN112230119B (en) | Power device conduction voltage non-stop measuring circuit | |
| Hu et al. | A Gate Current Detection for Short-Circuit Protection of SiC MOSFET | |
| Bhatnagar et al. | Improvements in SOA ruggedness of 6.5 kV IGBTs |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |