CN114400236B - Silicon optical integrated chip integrating silicon optical modulator and germanium-silicon detector and preparation method - Google Patents
Silicon optical integrated chip integrating silicon optical modulator and germanium-silicon detector and preparation method Download PDFInfo
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- CN114400236B CN114400236B CN202210045715.3A CN202210045715A CN114400236B CN 114400236 B CN114400236 B CN 114400236B CN 202210045715 A CN202210045715 A CN 202210045715A CN 114400236 B CN114400236 B CN 114400236B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 105
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 105
- 239000010703 silicon Substances 0.000 title claims abstract description 105
- 230000003287 optical effect Effects 0.000 title claims abstract description 64
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 65
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims abstract description 38
- 230000008569 process Effects 0.000 claims abstract description 24
- 238000005498 polishing Methods 0.000 claims abstract description 11
- 239000000126 substance Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 28
- 239000011229 interlayer Substances 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052732 germanium Inorganic materials 0.000 claims description 18
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 abstract description 8
- 238000010168 coupling process Methods 0.000 abstract description 8
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- 238000010521 absorption reaction Methods 0.000 description 2
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- 230000002411 adverse Effects 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
Abstract
The invention provides a silicon light integrated chip integrating a silicon light modulator and a germanium-silicon detector and a preparation method thereof, wherein the position and the size of a silicon nitride waveguide are defined by utilizing a groove formed by an etching process, and then redundant silicon nitride is removed by chemical mechanical polishing, and the silicon nitride in the groove forms the optical waveguide; with the silicon waveguide at the bottom layer and the silicon nitride waveguide at the upper layer, various passive devices with better performance, such as a coupler with lower coupling loss, a waveguide with lower transmission loss, and the like, can be designed in a combined manner.
Description
Technical Field
The invention belongs to the technical field of optical communication and integrated optics, and particularly relates to a silicon optical integrated chip integrating a silicon optical modulator and a silicon germanium detector and a preparation method thereof.
Background
Silicon-based photonic integration has been seen in recent years as one of the ideal solutions for large bandwidth, low power consumption and low cost optical interconnects. The silicon-based photoelectric integrated chip based on the silicon photon technology can integrate devices such as a multipath high-speed modulator, a detector, a beam splitting/combining device, a wavelength division multiplexing/demultiplexing device and the like, and can meet the requirements of high-capacity communication, high-speed optical interconnection and the like. However, silicon-based optoelectronic integrated chips have certain limitations in performance, such as: the silicon material is affected by two-photon absorption and free carrier absorption effects, and is difficult to bear larger optical power, so that the input optical power of the integrated chip is limited; the transmission loss of the silicon optical waveguide is slightly high, so that the on-chip loss is larger, and especially the loss of an integrated chip with longer waveguide and larger area is larger; the thermal-optical coefficient of the silicon material is large, so that the performance of devices such as silicon fundamental wave multiplexing/demultiplexing devices is easily affected by temperature.
To solve the above technical problem, those skilled in the art propose to use silicon nitride materials to make passive devices, which have higher high optical power tolerance than silicon, lower waveguide transmission loss, and a thermo-optical coefficient of only about one fifth that of silicon materials. The passive optical waveguide device made of the silicon nitride material has higher optical power tolerance, lower optical waveguide transmission loss and temperature insensitivity. However, silicon nitride materials are difficult to fabricate high-speed active devices such as modulators and detectors, resulting in limited use of silicon nitride-based integrated chips.
At present, there are two general modes for manufacturing a silicon nitride waveguide on a silicon-based platform, the first mode is a low-pressure chemical vapor deposition method (LPCVD, lowPressure Chemical Vapor Deposition), the LPCVD method needs a higher temperature, and is generally easy to integrate with a silicon-based passive device at 600-800 ℃, but has larger process realization difficulty when the LPCVD method is integrated with a silicon-based high-speed active device, for example, the LPCVD method can bring obvious adverse effects to the manufacture of a silicon-based modulator and a germanium-silicon detector; another approach is the plasma enhanced chemical Vapor Deposition (PECVD, plasma Enhanced Chemical Vapor Deposition), which requires lower temperatures, typically 200-400 ℃, at which no significant impact on silicon-based modulator and silicon-germanium detector fabrication, while PECVD belongs to a later process, resulting in a minimum distance between the silicon nitride waveguide and the silicon waveguide that is too large, e.g., above 500nm, which is detrimental to the optical field to achieve low-loss switching between the silicon waveguide and the silicon nitride waveguide, thereby degrading the performance of the integrated chip.
Disclosure of Invention
In order to solve the technical problems, the invention provides a silicon optical integrated chip integrating a silicon optical modulator and a germanium-silicon detector and a preparation method thereof. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
The invention adopts the following technical scheme:
The invention provides a silicon optical integrated chip integrating a silicon optical modulator and a germanium-silicon detector, which comprises the following components: the SOI wafer and the interlayer dielectric deposited on the SOI wafer, wherein a groove is etched on the interlayer dielectric, and a silicon nitride waveguide is deposited in the groove.
Furthermore, the SOI wafer is also provided with a PN junction and a silicon waveguide of the silicon optical modulator and a germanium layer of the germanium-silicon detector, and the interlayer medium covers the PN junction and the silicon waveguide of the silicon optical modulator and the germanium layer of the germanium-silicon detector.
Further, the groove is positioned above the silicon waveguide of the silicon light modulator.
The invention also provides a preparation method of the silicon optical integrated chip integrating the silicon optical modulator and the germanium-silicon detector, which comprises the following steps: etching the interlayer dielectric to form a groove; depositing a silicon nitride material on the interlayer medium to cover the groove with silicon nitride; and grinding and removing the silicon nitride material outside the grooves, so that the silicon nitride in the grooves forms a silicon nitride waveguide.
Wherein, the method also comprises the following steps: manufacturing PN junctions and silicon waveguides of a silicon optical modulator on an SOI wafer, and finishing the growth of germanium layers of a germanium-silicon detector; and depositing the interlayer medium and performing chemical mechanical polishing.
Wherein the recess is etched over the silicon waveguide of the silicon optical modulator.
Wherein after the silicon nitride waveguide is formed, further comprising: and depositing silicon dioxide with a certain thickness, and covering the PN junction of the silicon light modulator, the silicon waveguide, the germanium layer of the germanium-silicon detector and the silicon nitride waveguide by the deposited silicon dioxide layer.
The PN junction and the silicon waveguide of the silicon light modulator are manufactured on the SOI wafer by using a CMOS process, and the germanium layer growth of the germanium-silicon detector is completed; a silicon nitride material is deposited on the interlayer dielectric using a plasma enhanced chemical vapor deposition process.
The invention has the beneficial effects that: the position and the size of the silicon nitride waveguide are defined by utilizing the groove formed by the etching process, then the redundant silicon nitride is removed by chemical mechanical polishing, and the silicon nitride in the groove forms the optical waveguide, so that the preparation of the silicon nitride waveguide can be compatible with the manufacturing process of the silicon optical integrated chip comprising the silicon optical modulator and the germanium-silicon detector, the distance between the silicon nitride waveguide and the silicon waveguide can be flexibly controlled, and the controllable coupling strength and the coupling loss between the silicon waveguide and the silicon nitride waveguide are realized; with the silicon waveguide at the bottom layer and the silicon nitride waveguide at the upper layer, various passive devices with better performance, such as a coupler with lower coupling loss, a waveguide with lower transmission loss, and the like, can be designed in a combined manner.
Drawings
FIG. 1 is a schematic diagram of a silicon optical integrated chip according to the present invention;
FIG. 2 is a schematic cross-sectional view of a silicon optical integrated chip after the completion of step two according to the method of the present invention;
FIG. 3 is a schematic cross-sectional view of a silicon optical integrated chip after completion of step three according to the method of the present invention;
FIG. 4 is a schematic cross-sectional view of a silicon optical integrated chip after the completion of step four according to the method of the present invention;
FIG. 5 is a schematic cross-sectional view of a silicon optical integrated chip after the completion of step five according to the method of the present invention;
fig. 6 is a schematic cross-sectional view of a silicon optical integrated chip after completing step six according to the method for manufacturing a silicon optical integrated chip of the present invention.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others.
In some illustrative embodiments, as shown in FIG. 1, the present invention provides a silicon optical integrated chip integrating a silicon optical modulator and a silicon germanium detector, comprising: an SOI wafer 1.
The SOI wafer 1 is provided with a PN junction 201 and a silicon waveguide 202 of a silicon optical modulator 2 manufactured by a CMOS process and a germanium layer 301 of a germanium-silicon detector 3. After the preparation of the PN junction 201, the silicon waveguide 202 and the germanium layer 301 is completed, an interlayer dielectric 4 is deposited on the SOI wafer 1, that is, the interlayer dielectric 4 is deposited on the SOI wafer 1, and the interlayer dielectric 4 covers the PN junction 201, the silicon waveguide 202 and the germanium layer 301.
The interlayer dielectric 4 is an electrically insulating layer and serves as a separation film between two layers of conductive metal or adjacent metal lines, and typically a silicon dioxide material having a dielectric constant of 3.9 to 4.0 is used.
The interlayer dielectric 4 is etched with a groove. After the etching is completed, a silicon nitride material is deposited on the interlayer dielectric 4 by using a vapor deposition method of plasma enhanced chemistry, so that the silicon nitride is deposited in the grooves, and thus the silicon nitride deposited in the grooves forms the silicon nitride waveguide 5. The invention utilizes the grooves formed by the etching process to define the position and the size of the silicon nitride waveguide 5, and the grooves are etched above the silicon waveguide 202 of the silicon optical modulator, so that the distance between the silicon nitride waveguide 5 and the silicon waveguide 202 can be flexibly controlled, and the controllable coupling strength and the controllable coupling loss between the silicon waveguide 202 and the silicon nitride waveguide 5 are realized. With the silicon waveguide 202 on the bottom layer and the silicon nitride waveguide 5 on the upper layer, various passive devices with better performance, such as a coupler with lower coupling loss, a waveguide with lower transmission loss, and the like, can be designed in combination.
The silicon nitride material is a CMOS process compatible material and has the characteristics of mature process and low cost. The invention transfers the excellent characteristics of the silicon nitride waveguide to the silicon optical integrated chip for advantage complementation, not only can play the advantages of high integration level, low cost and mass production of the silicon optical integrated chip, but also can improve the performance of passive devices in the integrated chip through the introduction of silicon nitride, so that the silicon optical integrated chip integrated with the silicon nitride waveguide has better performance and stronger market competitiveness, and is applicable to wider scenes.
In some illustrative embodiments, as shown in fig. 1-6, the present invention further provides a method for manufacturing a silicon optical integrated chip for integrating a silicon optical modulator and a silicon germanium detector, comprising the steps of:
Step one: the PN junction 201 and the silicon waveguide 202 of the silicon optical modulator 2 are fabricated on the SOI wafer 1 by using a CMOS process, and the germanium layer 301 of the germanium-silicon detector 3 is grown on the SOI wafer 1. The CMOS process is a prior art, and the preparation of the PN junction 201, the silicon waveguide 202, and the germanium layer 301 is a prior art, which is not described herein.
Step two: after the fabrication of the PN junction 201, the silicon waveguide 202, the germanium layer 301, and the pins of the sige probe 3, an interlayer dielectric 4 is deposited and subjected to chemical mechanical polishing (CMP, chip multiprocessors), and the cross-sectional view of the resulting structure is shown in fig. 2.
The interlayer dielectric 4 is an electrically insulating layer, and is typically a silicon dioxide material having a dielectric constant of 3.9 to 4.0.
CMP is a critical process for achieving planarization of a wafer surface during integrated circuit fabrication. Unlike conventional pure mechanical or pure chemical polishing methods, the CMP process is to remove micro/nano-scale different materials on the wafer surface by combining surface chemical action and mechanical polishing technology, so as to achieve nano-scale planarization on the wafer surface, and enable the next photolithography process to be performed. The main working principle of CMP is that under a certain pressure and in the presence of polishing liquid, the polished wafer makes relative motion to the polishing pad, and the polished wafer surface meets the requirements of high planarization, low surface roughness and low defects by means of the high organic combination between the mechanical grinding action of the nano abrasive and the chemical action of various chemical reagents.
Step three: as shown in fig. 3, the interlayer dielectric 4 is etched to form a recess 6, i.e. the recess 6 is etched in silicon dioxide, the recess 6 will subsequently be filled with a silicon nitride material. The cross-sectional dimensions of the grooves 6 will determine the cross-sectional dimensions of the silicon nitride waveguide 5.
Step four: a silicon nitride material 7 is deposited on the interlayer dielectric 4 using a PECVD process, as shown in fig. 4, with silicon nitride covering the recess 6.
Step five: as shown in fig. 5, the silicon nitride material outside the recess 6 and part of the silicon dioxide are removed by polishing using a CMP process, i.e. only the silicon nitride in the recess 6 remains, so that the silicon nitride in the recess 6 forms the silicon nitride waveguide 5.
Step six: as shown in fig. 6, after the silicon nitride waveguide 5 is formed, a certain thickness of silicon dioxide is deposited for subsequent via processing and electrode fabrication, and the deposited silicon dioxide layer may cover the PN junction 201 and the silicon waveguide 202 of the silicon optical modulator, the germanium layer 301 of the germanium-silicon detector, and the silicon nitride waveguide 5. The subsequent steps are mainly to open a through hole and manufacture an electrode, and to lead out standard CMOS processes such as pad, which will not be described here again.
The recess 6 herein is etched over the silicon waveguide 202 of the silicon optical modulator.
The silicon nitride deposition process is manufactured by adopting a PECVD (plasma enhanced chemical vapor deposition) mode, belongs to a subsequent CMOS (complementary metal oxide semiconductor) process, and is realized in the subsequent process after the PN junction of the silicon light modulator and the germanium region of the germanium-silicon detector grow. The grooves 6 are formed by etching to define the position and cross-sectional dimensions of the silicon nitride waveguides 5, after which the excess silicon nitride is removed by chemical mechanical polishing, the silicon nitride in the grooves 6 forming the optical waveguides. The manufacturing method of the silicon nitride waveguide 5 can be well compatible with the technological process of a silicon light modulator and a germanium-silicon detector, the distance between the silicon nitride waveguide 5 and the silicon waveguide 202 can be designed to be very close, the distance can be easily realized to be smaller than 200nm, the extremely low coupling loss between the silicon waveguide 202 and the silicon nitride waveguide 5 is realized, and the passive device with better performance can be designed by utilizing the combination of the two layers of optical waveguides.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
Claims (4)
1. A silicon optical integrated chip integrating a silicon optical modulator and a silicon germanium detector, comprising: the device comprises an SOI wafer and an interlayer medium deposited on the SOI wafer, wherein a groove is etched on the interlayer medium, and a silicon nitride waveguide is deposited in the groove;
The SOI wafer is also provided with a PN junction and a silicon waveguide of a silicon light modulator and a germanium layer of a germanium-silicon detector, and the interlayer medium covers the PN junction and the silicon waveguide of the silicon light modulator and the germanium layer of the germanium-silicon detector;
the recess is located above a silicon waveguide of the silicon optical modulator.
2. A method for fabricating a silicon optical integrated chip integrating a silicon optical modulator and a silicon germanium detector, comprising:
manufacturing PN junctions and silicon waveguides of a silicon optical modulator on an SOI wafer, and finishing the growth of germanium layers of a germanium-silicon detector; depositing an interlayer medium and performing chemical mechanical polishing;
Etching the interlayer dielectric to form a groove;
Depositing a silicon nitride material on the interlayer medium to cover the groove with silicon nitride;
Grinding and removing silicon nitride materials outside the grooves so that silicon nitride in the grooves forms a silicon nitride waveguide;
the recess is etched over a silicon waveguide of the silicon optical modulator.
3. The method of fabricating a silicon optical integrated chip for integrating a silicon optical modulator and a silicon germanium detector as defined in claim 2, further comprising, after the silicon nitride waveguide is formed: and depositing silicon dioxide with a certain thickness, and covering the PN junction of the silicon light modulator, the silicon waveguide, the germanium layer of the germanium-silicon detector and the silicon nitride waveguide by the deposited silicon dioxide layer.
4. A method of fabricating a silicon optical integrated chip for integrating a silicon optical modulator and a silicon germanium detector as defined in claim 3, wherein a CMOS process is used to fabricate a PN junction and a silicon waveguide of the silicon optical modulator on the SOI wafer and to complete the growth of a germanium layer of the silicon germanium detector; a silicon nitride material is deposited on the interlayer dielectric using a plasma enhanced chemical vapor deposition process.
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| CN112285826A (en) * | 2020-11-10 | 2021-01-29 | 中国科学院上海微系统与信息技术研究所 | Silicon-based multimode light receiving device and preparation method thereof |
| CN112680715A (en) * | 2020-11-12 | 2021-04-20 | 中国科学院微电子研究所 | Growth method of silicon nitride film and preparation method of thick film silicon nitride waveguide device |
| CN113540063A (en) * | 2021-07-14 | 2021-10-22 | Nano科技(北京)有限公司 | Silicon optical integrated chip compatible with germanium-silicon detector and thin-film lithium niobate modulator |
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