CN114400236A - Silicon optical integrated chip integrating silicon optical modulator and germanium-silicon detector and preparation method thereof - Google Patents
Silicon optical integrated chip integrating silicon optical modulator and germanium-silicon detector and preparation method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 104
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 104
- 239000010703 silicon Substances 0.000 title claims abstract description 104
- 230000003287 optical effect Effects 0.000 title claims abstract description 75
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 66
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 38
- 230000008569 process Effects 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 238000005498 polishing Methods 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 28
- 239000011229 interlayer Substances 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052732 germanium Inorganic materials 0.000 claims description 18
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
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- 230000009471 action Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
Abstract
The invention provides a silicon optical integrated chip integrating a silicon optical modulator and a germanium-silicon detector and a preparation method thereof, wherein the position and the size of a silicon nitride waveguide are defined by utilizing a groove formed by an etching process, then redundant silicon nitride is removed by chemical mechanical polishing, and the silicon nitride in the groove forms an optical waveguide, so that the preparation of the silicon nitride waveguide can be compatible with the manufacturing process of the silicon optical integrated chip comprising the silicon optical modulator and the germanium-silicon detector, and the distance between the silicon nitride waveguide and the silicon waveguide can be flexibly controlled, thereby realizing controllable coupling strength and coupling loss between the silicon waveguide and the silicon nitride waveguide; by utilizing the silicon waveguide at the bottom layer and the silicon nitride waveguide at the upper layer, a plurality of passive devices with better performance can be combined and designed, such as couplers with lower coupling loss, waveguides with lower transmission loss and the like.
Description
Technical Field
The invention belongs to the technical field of optical communication and integrated optics, and particularly relates to a silicon optical integrated chip integrating a silicon optical modulator and a germanium-silicon detector and a preparation method thereof.
Background
In recent years, silicon-based photonic integration has been viewed as one of the ideal solutions for large bandwidth, low power consumption, and low cost optical interconnects. The silicon-based photoelectric integrated chip based on the silicon photon technology can integrate devices such as a multi-path high-speed modulator, a detector, a beam splitter/combiner, a wavelength division multiplexing/demultiplexing device and the like, and can meet the requirements of high-capacity communication, high-speed optical interconnection and the like. However, the silicon-based optoelectronic integrated chip also has certain limitations in performance, such as: the silicon material is influenced by two-photon absorption and free carrier absorption effects, so that the silicon material is difficult to bear larger optical power, and the input optical power of the integrated chip is limited; the transmission loss of the silicon optical waveguide is slightly higher, so that the on-chip loss is larger, and especially the loss of an integrated chip with longer waveguide and larger area is larger; the silicon material has a large thermo-optic coefficient, so that the performance of devices such as silicon-based wavelength division multiplexing/demultiplexing and the like is easily influenced by temperature.
In order to solve the above technical problems, those skilled in the art propose to use a silicon nitride material to fabricate a passive device, which has a higher property of withstanding large optical power than silicon, a lower waveguide transmission loss, and a thermo-optic coefficient of only about one fifth of that of the silicon material. The passive optical waveguide device made of the silicon nitride material has the characteristics of higher optical power tolerance, lower optical waveguide transmission loss and temperature insensitivity. However, silicon nitride materials are difficult to manufacture high-speed active devices such as modulators and detectors, and the use scenes of silicon nitride-based integrated chips are limited.
At present, two methods are generally used for manufacturing a silicon nitride waveguide on a silicon-based platform, the first method is a Low Pressure Chemical Vapor Deposition (LPCVD) method, the LPCVD method requires a high temperature, generally 600-; another method is a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, which requires a low temperature, generally 200-.
Disclosure of Invention
In order to solve the technical problems, the invention provides a silicon optical integrated chip integrating a silicon optical modulator and a germanium-silicon detector and a preparation method thereof. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
The invention adopts the following technical scheme:
the invention provides a silicon optical integrated chip for integrating a silicon optical modulator and a germanium-silicon detector, which comprises: the SOI wafer comprises an SOI wafer and an interlayer medium deposited on the SOI wafer, wherein a groove is etched in the interlayer medium, and a silicon nitride waveguide is deposited in the groove.
Further, a PN junction of the silicon optical modulator, a silicon waveguide and a germanium layer of the germanium-silicon detector are further arranged on the SOI wafer, and the interlayer medium covers the PN junction of the silicon optical modulator, the silicon waveguide and the germanium layer of the germanium-silicon detector.
Further, the groove is positioned above the silicon waveguide of the silicon optical modulator.
The invention also provides a preparation method of the silicon optical integrated chip integrating the silicon optical modulator and the germanium-silicon detector, which comprises the following steps: etching the interlayer dielectric to form a groove; depositing a silicon nitride material on the interlayer medium to enable the silicon nitride to cover the groove; and grinding and removing the silicon nitride material outside the groove so that the silicon nitride positioned in the groove forms a silicon nitride waveguide.
Wherein, the method also comprises the following steps: manufacturing a PN junction and a silicon waveguide of the silicon optical modulator on the SOI wafer, and finishing the growth of a germanium layer of the germanium-silicon detector; and depositing the interlayer medium and performing chemical mechanical polishing.
Wherein the groove is etched above the silicon waveguide of the silicon optical modulator.
Wherein after the formation of the silicon nitride waveguide, further comprising: and depositing silicon dioxide with a certain thickness, wherein the deposited silicon dioxide layer covers the PN junction and the silicon waveguide of the silicon optical modulator, the germanium layer of the germanium-silicon detector and the silicon nitride waveguide.
Manufacturing a PN junction and a silicon waveguide of the silicon optical modulator on the SOI wafer by utilizing a CMOS process, and finishing the growth of a germanium layer of the germanium-silicon detector; depositing a silicon nitride material on the interlayer dielectric using a vapor deposition process of plasma enhanced chemistry.
The invention has the following beneficial effects: the position and the size of the silicon nitride waveguide are defined by utilizing the groove formed by the etching process, then the redundant silicon nitride is removed through chemical mechanical polishing, and the silicon nitride in the groove forms the optical waveguide, so that the preparation of the silicon nitride waveguide is compatible with the manufacturing process of a silicon optical integrated chip containing a silicon optical modulator and a germanium-silicon detector, and the distance between the silicon nitride waveguide and the silicon waveguide can be flexibly controlled, thereby realizing the controllable coupling strength and coupling loss between the silicon waveguide and the silicon nitride waveguide; by utilizing the silicon waveguide at the bottom layer and the silicon nitride waveguide at the upper layer, a plurality of passive devices with better performance can be combined and designed, such as couplers with lower coupling loss, waveguides with lower transmission loss and the like.
Drawings
FIG. 1 is a schematic structural diagram of a silicon optical integrated chip according to the present invention;
FIG. 2 is a schematic cross-sectional view of the silicon optical integrated chip after step two of the manufacturing method of the invention is completed;
FIG. 3 is a schematic cross-sectional view of a silicon optical integrated chip after step three of the manufacturing method of the invention;
FIG. 4 is a schematic cross-sectional view of the silicon optical integrated chip after step four of the manufacturing method of the invention;
FIG. 5 is a schematic cross-sectional view of the silicon optical integrated chip after step five of the manufacturing method of the invention;
fig. 6 is a schematic cross-sectional view of the silicon optical integrated chip after step six of the method for manufacturing a silicon optical integrated chip of the present invention is completed.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others.
In some illustrative embodiments, as shown in fig. 1, the present invention provides a silicon optical integrated chip for integrating a silicon optical modulator and a silicon germanium detector, comprising: an SOI wafer 1.
The SOI wafer 1 is provided with a PN junction 201 and a silicon waveguide 202 of a silicon optical modulator 2 and a germanium layer 301 of a silicon germanium detector 3, which are manufactured by a CMOS process. After the preparation of the PN junction 201, the silicon waveguide 202 and the germanium layer 301 is completed, the SOI wafer 1 is deposited with the interlayer dielectric 4, that is, the interlayer dielectric 4 is deposited on the SOI wafer 1, and the interlayer dielectric 4 covers the PN junction 201, the silicon waveguide 202 and the germanium layer 301.
The interlayer dielectric 4 is an electrical insulation layer, serves as an isolation film between two layers of conductive metal or adjacent metal lines, and is usually made of a silicon dioxide material with a dielectric constant of 3.9-4.0.
Grooves are etched in the interlayer dielectric 4. After the etching is completed, a silicon nitride material is deposited on the interlayer dielectric 4 by using a plasma enhanced chemical vapor deposition method, so that the silicon nitride is deposited in the groove, and thus the silicon nitride deposited in the groove forms a silicon nitride waveguide 5. The invention utilizes the groove formed by the etching process to define the position and the size of the silicon nitride waveguide 5, and the groove is etched above the silicon waveguide 202 of the silicon optical modulator, so that the distance between the silicon nitride waveguide 5 and the silicon waveguide 202 can be flexibly controlled, and the controllable coupling strength and the coupling loss between the silicon waveguide 202 and the silicon nitride waveguide 5 are realized. By using the silicon waveguide 202 on the bottom layer and the silicon nitride waveguide 5 on the upper layer, a variety of passive devices with better performance, such as couplers with lower coupling loss, waveguides with lower transmission loss, and the like, can be designed in combination.
The silicon nitride material is a material compatible with a CMOS process, and has the characteristics of mature process and low cost. The invention transfers the excellent characteristics of the silicon nitride waveguide to the silicon optical integrated chip for advantage complementation, thereby not only playing the advantages of high integration level, low cost and mass production of the silicon optical integrated chip, but also improving the performance of passive devices in the integrated chip by introducing the silicon nitride, so that the silicon optical integrated chip integrated with the silicon nitride waveguide has better performance and stronger market competitiveness, and the application scene of the silicon optical integrated chip is necessarily wider.
In some illustrative embodiments, as shown in fig. 1 to 6, the present invention further provides a method for manufacturing a silicon optical integrated chip integrating a silicon optical modulator and a germanium-silicon detector, including the following steps:
the method comprises the following steps: the PN junction 201 and the silicon waveguide 202 of the silicon optical modulator 2 are fabricated on the SOI wafer 1 by using a CMOS process, and the growth of the germanium layer 301 of the silicon germanium detector 3 is completed on the SOI wafer 1. The CMOS process is prior art, and the preparation of the PN junction 201, the silicon waveguide 202, and the germanium layer 301 is prior art, and will not be described herein.
Step two: after the PN junction 201, the silicon waveguide 202, the germanium layer 301 and the leads of the sige detector 3 are fabricated, the interlayer dielectric 4 is deposited and Chemical Mechanical Polishing (CMP) is performed, and the cross-sectional view of the structure is shown in fig. 2.
The interlayer dielectric 4 is an electrically insulating layer, and is usually made of a silicon dioxide material having a dielectric constant of 3.9 to 4.0.
CMP is a critical process for achieving wafer surface planarization in integrated circuit manufacturing. Different from the traditional pure mechanical or pure chemical polishing method, the CMP process realizes the removal of micron/nanometer-scale different materials on the surface of the wafer by combining the surface chemical action and the mechanical grinding technology, thereby achieving the nanometer-scale planarization of the surface of the wafer and leading the next photoetching process to be carried out. The main working principle of CMP is that under a certain pressure and in the presence of polishing liquid, a polished wafer makes relative motion to a polishing pad, and the mechanical grinding action of nano-abrasive and the chemical action of various chemical reagents are highly organically combined, so that the surface of the polished wafer meets the requirements of high planarization, low surface roughness and low defect.
Step three: as shown in fig. 3, the interlayer dielectric 4 is etched to form a recess 6, i.e. the recess 6 is etched in the silicon dioxide, and the recess 6 is subsequently filled with a silicon nitride material. The cross-sectional dimensions of the groove 6 will determine the cross-sectional dimensions of the silicon nitride waveguide 5.
Step four: a silicon nitride material 7 is deposited on the interlayer dielectric 4 by PECVD, as shown in fig. 4, the silicon nitride covering the recess 6.
Step five: as shown in fig. 5, the silicon nitride material outside the groove 6 and a part of the silicon dioxide are removed by polishing using a CMP process, i.e. only the silicon nitride in the groove 6 remains, so that the silicon nitride in the groove 6 forms the silicon nitride waveguide 5.
Step six: as shown in fig. 6, after the silicon nitride waveguide 5 is formed, a certain thickness of silicon dioxide is deposited for the subsequent via process and electrode fabrication, and the thickness of the deposited silicon dioxide layer may cover the PN junction 201 and the silicon waveguide 202 of the silicon optical modulator, the germanium layer 301 of the silicon germanium detector, and the silicon nitride waveguide 5. The subsequent steps mainly include opening through holes, manufacturing electrodes, leading out pads and other standard CMOS processes, and are not described herein again.
The groove 6 herein is etched over the silicon waveguide 202 of the silicon light modulator.
The silicon nitride deposition process of the invention is manufactured by a PECVD mode, belongs to a subsequent CMOS process, and is realized in the subsequent process after PN junction of a silicon optical modulator and germanium region of a germanium-silicon detector grow. The silicon nitride waveguide 5 is defined in terms of its position and cross-sectional dimensions by etching to form a groove 6, after which excess silicon nitride is removed by chemical mechanical polishing, the silicon nitride in the groove 6 forming the optical waveguide. The manufacturing method of the silicon nitride waveguide 5 can be well compatible with the technological process of a silicon optical modulator and a germanium-silicon detector, the silicon nitride waveguide 5 and the silicon waveguide 202 can be designed to be very close to each other, the distance smaller than 200nm can be easily realized, so that the extremely low coupling loss between the silicon waveguide 202 and the silicon nitride waveguide 5 is realized, and a passive device with better performance can be designed by combining the two layers of optical waveguides.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
Claims (8)
1. A silicon optical integrated chip for integrating a silicon optical modulator and a germanium-silicon detector is characterized by comprising: the SOI wafer comprises an SOI wafer and an interlayer medium deposited on the SOI wafer, wherein a groove is etched in the interlayer medium, and a silicon nitride waveguide is deposited in the groove.
2. The integrated silicon optical modulator and germanium-silicon detector chip of claim 1, wherein a PN junction and a silicon waveguide of the silicon optical modulator and a germanium layer of the germanium-silicon detector are further disposed on the SOI wafer, and the interlayer dielectric covers the PN junction and the silicon waveguide of the silicon optical modulator and the germanium layer of the germanium-silicon detector.
3. The integrated silicon optical modulator and silicon germanium detector chip as claimed in claim 2, wherein said trench is located above a silicon waveguide of said silicon optical modulator.
4. A method for preparing a silicon optical integrated chip integrating a silicon optical modulator and a germanium-silicon detector is characterized by comprising the following steps:
etching the interlayer dielectric to form a groove;
depositing a silicon nitride material on the interlayer medium to enable the silicon nitride to cover the groove;
and grinding and removing the silicon nitride material outside the groove so that the silicon nitride positioned in the groove forms a silicon nitride waveguide.
5. The method for manufacturing the silicon optical integrated chip integrating the silicon optical modulator and the germanium-silicon detector according to claim 4, wherein the method further comprises the following steps: manufacturing a PN junction and a silicon waveguide of the silicon optical modulator on the SOI wafer, and finishing the growth of a germanium layer of the germanium-silicon detector; and depositing the interlayer medium and performing chemical mechanical polishing.
6. The method according to claim 5, wherein the groove is etched above the silicon waveguide of the silicon optical modulator.
7. The method of claim 6, further comprising, after the formation of the silicon nitride waveguide: and depositing silicon dioxide with a certain thickness, wherein the deposited silicon dioxide layer covers the PN junction and the silicon waveguide of the silicon optical modulator, the germanium layer of the germanium-silicon detector and the silicon nitride waveguide.
8. The method according to claim 7, wherein a PN junction and a silicon waveguide of the silicon optical modulator are fabricated on the SOI wafer by a CMOS process, and germanium layer growth of the germanium-silicon detector is completed; depositing a silicon nitride material on the interlayer dielectric using a vapor deposition process of plasma enhanced chemistry.
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| CN115166898A (en) * | 2022-07-21 | 2022-10-11 | 西安电子科技大学 | Electro-optical modulation integrated waveguide structure |
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| CN114899265A (en) * | 2022-07-14 | 2022-08-12 | 之江实验室 | Germanium-silicon detector with point-like metal contact structure |
| CN115166898A (en) * | 2022-07-21 | 2022-10-11 | 西安电子科技大学 | Electro-optical modulation integrated waveguide structure |
| CN115166898B (en) * | 2022-07-21 | 2024-02-06 | 西安电子科技大学 | Electro-optical modulation integrated waveguide structure |
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