CN108321119B - Three-dimensional photoelectric integrated filter realized based on CMOS (complementary Metal oxide semiconductor) post process and preparation method thereof - Google Patents
Three-dimensional photoelectric integrated filter realized based on CMOS (complementary Metal oxide semiconductor) post process and preparation method thereof Download PDFInfo
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Abstract
A three-dimensional photoelectric integrated filter and a preparation method thereof comprise the following steps: the CMOS monitoring device comprises an isolation layer, a first photoelectric device layer, a monitoring layer, a buffer layer, a second photoelectric device layer and a protective layer which are sequentially deposited on a CMOS integrated circuit from bottom to top, wherein a plurality of through holes penetrate through the isolation layer, the first photoelectric device layer, the monitoring layer, the buffer layer, the second photoelectric device layer and the protective layer; the first photoelectric device layer is used for preparing a lower filter interacting with the CMOS integrated circuit; the second optoelectronic device layer is used to fabricate an upper filter that is optically interconnected with the first optoelectronic device layer. The invention can solve the loss and crosstalk of photoelectron integrated optical interconnection in a single plane, realize multi-dimensional photoelectron integration in a plurality of planes and improve the density of photoelectron integration and the complexity of an optical interconnection system; the micro-loop filter can also solve the dependence on the environment temperature, and the purpose of wide working temperature range is realized through the automatic thermal tuning of the bottom temperature control circuit to the top filter.
Description
Technical Field
The invention relates to the technical field of photoelectric integration, in particular to a three-dimensional photoelectric integrated filter realized based on a CMOS (complementary metal oxide semiconductor) post process and a preparation method thereof.
Background
With the continuous development of integrated circuit technology towards high speed and high integration, moore's law is facing the ultimate challenge of chip integration, and the problems of high delay, high power consumption, severe signal crosstalk and the like inevitably occur in the conventional electrical interconnection. People are thus looking to move to a new generation of interconnect technology, optical interconnects. The optical interconnection has the advantages of wide bandwidth, electromagnetic interference resistance, strong confidentiality, low loss, small power consumption and the like, and the silicon-based optical interconnection can give play to the advantages of wide bandwidth, low crosstalk, low loss and compatibility with a CMOS (complementary metal oxide semiconductor) process in optical communication.
However, current optoelectronic integrated optical interconnection schemes are limited to a single plane, i.e. different optoelectronic devices are in the same plane, and the crossing of optical waveguides in the same plane causes loss and crosstalk. On the other hand, the area of a single plane is limited, and optoelectronic devices cannot be integrated on a large scale, thereby limiting the density of optoelectronic integration and the complexity of optical interconnection systems. Therefore, it is necessary to provide a multi-dimensional optoelectronic integrated optical interconnection scheme, that is, different optoelectronic devices are in different planes, and optical signals in optical waveguides can be coupled between different planar waveguides by means of directional couplers, so that the crossing of optical waveguides in a single plane is eliminated, and loss and crosstalk caused by the crossing of the same planar waveguide are avoided. In addition, as different optoelectronic devices can be distributed on different planes, the density of optoelectronic integration and the complexity of an optical interconnection system can be greatly improved.
By adopting a Wavelength Division Multiplexing (WDM) technology, the utilization rate of the spectrum in the optoelectronic integrated optical interconnection system can be effectively improved, so that an optical interconnection link obtains higher bandwidth. The optical add/drop multiplexer formed by the micro-ring filter is a key device in a WDM system. The micro-ring filter can be more flexibly applied to the optical interconnection system because the micro-ring filter has a more compact size, good wavelength selection characteristics, and has upload/download capability. Silicon-based micro-ring filters are generally used as multiplexing and demultiplexing devices in silicon-based optoelectronic integrated optical interconnection systems at present. The multiplexer and demultiplexer based on the micro-ring filter has the advantages of small volume, easiness in on-chip integration and extremely high sensitivity to temperature change and strict requirements on working temperature, and the central wavelength can be shifted due to small temperature drift.
Disclosure of Invention
The invention aims to provide a three-dimensional photoelectric integrated filter realized based on a CMOS (complementary metal oxide semiconductor) post process and a preparation method thereof.
In order to achieve the above object, in one aspect, the present invention provides a three-dimensional optoelectronic integrated filter, which includes an isolation layer, a first optoelectronic device layer, a monitoring layer, a buffer layer, a second optoelectronic device layer, and a protection layer deposited on a CMOS integrated circuit in sequence from bottom to top, wherein a plurality of through holes penetrate through the above layers, the through holes are filled with metal and are in contact with electrodes of the CMOS integrated circuit, and interconnection electrodes are disposed above the through holes;
wherein: the first photoelectric device layer is used for preparing a lower filter interacting with the CMOS integrated circuit; the second optoelectronic device layer is used to fabricate an upper filter that is optically interconnected with the first optoelectronic device layer.
Preferably, the isolation layer has a thickness of 3 μm to 4 μm, the buffer layer has a thickness of 0.5 μm to 1.5 μm, the protection layer has a thickness of 4 μm to 5 μm, and the isolation layer, the buffer layer, and the protection layer are each independently selected from silicon oxide, aluminum oxide, and silicon oxynitride.
Preferably, the thickness of the first photoelectric device layer and the second photoelectric device layer is 220-500nm, and the materials are respectively and independently selected from Si and Si3N4Or AlN.
Preferably, the thickness of the monitoring layer is 100-300nm, and the material is selected from Ti/Au alloy or Cr/Au alloy.
Preferably, the lower filter is a through-end waveguide of a micro-ring filter, and the upper filter is a micro-ring and a down-end waveguide of the micro-ring filter.
In order to achieve the above object, in another aspect, the present invention further provides a method for manufacturing a three-dimensional optoelectronic integrated filter based on a CMOS post-process, including the following steps:
depositing an isolation layer above the CMOS integrated circuit and carrying out surface planarization treatment;
depositing a first optoelectronic device layer on the isolation layer and fabricating a lower filter on the first optoelectronic device layer;
depositing a monitoring layer on the first photoelectric device layer, and etching a specific area on the monitoring layer;
depositing a buffer layer on the monitoring layer, etching a monitoring step, and carrying out surface planarization treatment;
depositing a second optoelectronic device layer on the buffer layer, fabricating an upper filter on the second optoelectronic device layer, and completing an optical interconnection with the lower filter;
depositing a protective layer over said second photovoltaic device layer;
etching a plurality of through holes downwards at specific positions on the surface of the protective layer, filling metal in the through holes, and contacting with electrodes on the CMOS integrated circuit to complete electrical interconnection with the CMOS integrated circuit;
an interconnect electrode is formed over the via.
Preferably, the isolation layer, the first photoelectric device layer, the buffer layer, the second photoelectric device layer and the protection layer are formed by deposition through a PECVD process, and the monitoring layer is formed by deposition through a vacuum evaporation process.
Preferably, the surface planarization treatment is performed using a chemical mechanical polishing process.
Preferably, the lower filter and the upper filter are manufactured by using electron beam lithography and inductively coupled plasma etching processes.
Preferably, the through hole is prepared by adopting an inductively coupled plasma etching process.
Preferably, the metal in the through hole and the interconnection electrode are prepared by a sputtering process.
Compared with the prior art, the invention has the following advantages:
1. the invention adopts a thin-film laminated stack structure, can realize optical coupling and three-dimensional optical interconnection between two layers of photoelectric devices, and improves the bandwidth of an optical interconnection link and the integration level of photoelectric integration;
2. the invention adopts a three-dimensional integration method to realize the monolithic integration of the photoelectric device and the CMOS integrated circuit;
3. according to the three-dimensional photoelectric integrated filter, the lower CMOS integrated circuit has a temperature control function, and the filter can work in a wide temperature range;
4. all process temperatures adopted by the invention are controlled below 400 ℃, so that the influence of high temperature on a lower-layer CMOS integrated circuit can be prevented;
5. the preparation process adopted by the invention is completely compatible with the CMOS process, and can directly deposit a film on the CMOS integrated circuit to prepare the optical layer;
6. the invention adopts the monitoring layer to monitor the chemical mechanical polishing process in real time, can accurately control the thickness between layers and can reach the nm precision;
7. the invention adopts a MultiPrep precision grinding and polishing system, and the surface roughness can reach 0.1 nm.
Drawings
FIG. 1 is a three-dimensional schematic diagram of a three-dimensional optoelectronic integrated filter according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a three-dimensional optoelectronic integrated filter according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a process flow for manufacturing a three-dimensional optoelectronic integrated filter according to an embodiment of the present invention;
FIGS. 4A and 4B are schematic diagrams illustrating the height difference of the surface of the silicon oxide film measured by AFM before and after chemical mechanical polishing according to an embodiment of the present invention;
FIGS. 4C and 4D are the surface roughness of the silicon oxide film measured by AFM before and after chemical mechanical polishing, respectively, in the examples of the present invention.
Description of reference numerals:
1-a CMOS integrated circuit; 2-a silicon oxide isolation layer; 3-a first silicon nitride optoelectronic device layer; 4-a titanium monitoring layer; 5-a silicon oxide buffer layer; 6-a second silicon nitride optoelectronic device layer; 7-a silicon oxide protective layer; 8-an interconnect electrode; 9-through hole.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
The invention provides a three-dimensional photoelectric integrated filter realized based on CMOS post-process, all process temperatures are controlled below 400 ℃, the influence on a CMOS integrated circuit is avoided, the monolithic integration of a photoelectric device and the CMOS integrated circuit is realized, the three-dimensional optical interconnection is realized, and the bottleneck problem of electric interconnection is solved.
Referring to fig. 1 and 2, the three-dimensional photoelectric integrated filter implemented based on CMOS post-process of the present invention includes a silicon oxide isolation layer 2, a first silicon nitride photoelectric device layer 3, a titanium monitoring layer 4, a silicon oxide buffer layer 5, a second silicon nitride photoelectric device layer 6, and a silicon oxide protection layer 7 deposited on a CMOS integrated circuit 1 in sequence from bottom to top; a plurality of vias 9 pass through the above layers, wherein metal is filled and contacts the electrodes of the CMOS integrated circuit 1, and an interconnection electrode 8 is provided above the vias 9. The first silicon nitride optoelectronic device layer 3 is used for preparing a lower filter interacting with the CMOS integrated circuit 1; the second silicon nitride optoelectronic device layer 6 is used to fabricate an upper filter that is optically interconnected with the first silicon nitride optoelectronic device layer 3.
The thickness of the silicon oxide isolation layer 2 is 3-4 μm, the thickness of the first silicon nitride optoelectronic device layer 3 is 400nm, the thickness of the titanium monitoring layer 4 is 200nm, the thickness of the silicon oxide buffer layer 5 is 1 μm, the thickness of the second silicon nitride optoelectronic device layer 6 is 400nm, and the thickness of the silicon oxide protective layer 7 is 4-5 μm.
In the three-dimensional photoelectric integrated filter in this embodiment, light is coupled from the lower layer waveguide to the upper layer micro ring filter or from the upper layer waveguide to the lower layer micro ring filter by interlayer coupling.
As shown in fig. 3, the method for manufacturing the three-dimensional optoelectronic integrated filter shown in fig. 1 of the present invention includes the following steps:
step 1: and cleaning the CMOS integrated circuit substrate. Sequentially placing into acetone and ethanol, respectively, ultrasonically oscillating at 85% power for 5min, washing with deionized water, and repeating the above process for 3 times.
Growing SiH gas by PECVD method4And N2And under the condition of O, depositing silicon oxide with the thickness of 3-4 microns on the substrate as a silicon oxide isolation layer, wherein the refractive index of the material is 1.45 (at the wavelength of 1.55 microns).
The surface of the silicon oxide isolation layer is flattened by adopting a chemical mechanical polishing method, a MultiPrep precision grinding and polishing system is selected, the rotating speed of a grinding disc is 100rpm, the rotating speed of a grinding head is 1-time, the load of a sample is 0 grade, 50nm alkaline silica gel is selected as polishing liquid, and the polishing time is 60min, so that the surface of the chip reaches the flatness of nm grade.
Step 2: using plasmaPECVD using bulk enhanced chemical vapor deposition (PECVD) to grow SiH4 and NH3With a material refractive index of 2 (at a wavelength of 1.55 μm) as a first silicon nitride optoelectronic device layer, silicon nitride was deposited on the planar silicon oxide spacer layer to a thickness of 400 nm.
And preparing a straight-through end waveguide of the micro-ring filter on the first silicon nitride optoelectronic device layer by adopting an Electron Beam Lithography (EBL) method and an inductively coupled plasma etching (ICP) method, wherein the sectional dimension of the waveguide is 400nm multiplied by 1 mu m.
And 3, step 3: depositing an Au alloy with the thickness of 200nmTi on the silicon nitride photoelectric device layer by adopting a vacuum evaporation method to serve as a titanium monitoring layer, and etching a specific area by adopting an ultraviolet photoetching and wet etching method.
And 4, step 4: growing SiH gas by PECVD method4And N2And under the condition of O, silicon oxide with the thickness of 1 μm is deposited on the titanium monitoring layer to be used as a silicon oxide buffer layer, and the refractive index of the material is 1.45 (at the wavelength of 1.55 μm).
Selecting buffer solution (HF: NH) of hydrofluoric acid and ammonium fluoride by adopting ultraviolet lithography and wet etching method4F：H2O is 1: 2: 3) and corroding the silicon oxide buffer layer in the specific area to obtain a monitoring step.
The surface of the deposited chip is flattened by adopting a chemical mechanical polishing method, a MultiPrep precision grinding and polishing system is selected, the rotating speed of a grinding disc is selected to be 100rpm, the rotating speed of a grinding head is 1-time, the load of a sample is 0 grade, 20nm alkaline silica gel is selected as polishing liquid, the polishing time is 90min, the height of a step is measured by a step instrument every 10min, the surface reaches the flatness of nm grade, and the final thickness of a silicon oxide buffer layer is 400 nm.
And 5, step 5: growing SiH gas by PECVD method4And NH3Under the conditions of (1), silicon nitride with a thickness of 400nm is deposited on the surface of the flat silicon oxide buffer layer to serve as a second silicon nitride optoelectronic device layer, and the refractive index of the material is 2 (at the wavelength of 1.55 microns).
And preparing a micro-ring and a download end waveguide of the micro-ring filter on the second silicon nitride optoelectronic device layer by adopting an Electron Beam Lithography (EBL) method and an inductively coupled plasma etching (ICP) method. The section size of the micro-ring is 400nm multiplied by 1 mu m, the radius is 30 mu m, the horizontal displacement of the micro-ring and the bottom layer straight-through end waveguide is 300nm, and the vertical displacement is 800 nm; the cross-sectional dimension of the down-loading end waveguide is 400nm multiplied by 1 μm, and the horizontal distance between the down-loading end waveguide and the micro-ring is 300 nm. The second silicon nitride optoelectronic device layer microring and the first silicon nitride optoelectronic device layer through-end waveguide need to be strictly aligned, namely, aligned. The alignment precision is 20 nm.
And 6, step 6: growing SiH gas by PECVD method4And N2And depositing silicon oxide with the thickness of 4-5 microns on the second silicon nitride photoelectric device layer as a silicon oxide protective layer under the condition of O, wherein the refractive index of the material is 1.45 (at the wavelength of 1.55 microns).
And 7, step 7: and downwards etching a plurality of through holes at specific positions on the surface of the silicon oxide protective layer by an inductive coupling plasma etching process, filling metal in the through holes by a sputtering process, and contacting with electrodes on the CMOS integrated circuit to complete electrical interconnection with the CMOS integrated circuit.
And 8, step 8: and depositing aluminum-copper alloy on the surface of the silicon oxide protective layer above the through hole by a sputtering method to be used as an interconnection electrode, thereby completing the preparation.
As can be seen from fig. 4A, 4B, 4C and 4D: before chemical mechanical polishing, the difference in height of the surface of the silicon oxide film is 1.326 μm as shown in FIG. 4A, and the surface roughness is 489.07nm as shown in FIG. 4C; after chemical mechanical polishing using the MultiPrep precision polishing system, the surface height difference of the silicon oxide film is 0.0218 μm as shown in FIG. 4B, and the surface roughness is 0.081nm as shown in FIG. 4D. Before and after chemical mechanical polishing, the height difference of the surface of the silicon oxide film is reduced by two orders of magnitude, and the surface roughness is reduced by three orders of magnitude to reach a sub-nanometer order. The data fully show that the ultra-precision effects of nano-scale surface flatness and sub-nano-scale surface roughness can be achieved by adopting a MultiPrep precision grinding and polishing system to carry out a surface planarization process.
The three-dimensional photoelectric integrated filter realized based on the CMOS post process not only can solve the loss and crosstalk of photoelectron integrated optical interconnection in a single plane, realize multi-dimensional photoelectron integration in a plurality of planes and improve the density of photoelectron integration and the complexity of an optical interconnection system; the problem that the micro-loop filter depends on the environment temperature can be solved, and the purpose of working in a wide temperature range is achieved through automatic thermal tuning of the bottom-layer temperature control circuit to the top-layer filter.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in more detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit, concept and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A three-dimensional photoelectric integrated filter realized based on CMOS post-process comprises: the CMOS photoelectric device comprises an isolation layer, a first photoelectric device layer, a monitoring layer, a buffer layer, a second photoelectric device layer and a protective layer which are deposited on a CMOS integrated circuit from bottom to top in sequence, wherein a plurality of through holes penetrate through the isolation layer, the first photoelectric device layer, the monitoring layer, the buffer layer, the second photoelectric device layer and the protective layer;
wherein the first optoelectronic device layer is used to fabricate an underlying filter that interacts with a CMOS integrated circuit; the second photoelectric device layer is used for preparing an upper filter which is optically interconnected with the first photoelectric device layer, optical coupling and three-dimensional optical interconnection are achieved between the first photoelectric device layer and the second photoelectric device layer, and the CMOS integrated circuit has a temperature control function and is used for automatically and thermally tuning the lower filter and the upper filter.
2. The three-dimensional photoelectric integrated filter according to claim 1, wherein the spacer layer has a thickness of 3 μm to 4 μm, the buffer layer has a thickness of 0.5 μm to 1.5 μm, the protective layer has a thickness of 4 μm to 5 μm, and the spacer layer, the buffer layer, and the protective layer are each independently selected from silicon oxide, aluminum oxide, and silicon oxynitride.
3. The three-dimensional optoelectronic integrated filter according to claim 1, wherein the thickness of the first optoelectronic device layer and the second optoelectronic device layer is 220-500nm, and the material is independently selected from Si, Si3N4 or AlN.
4. The three-dimensional optoelectronic integrated filter as claimed in claim 1, wherein the thickness of the monitoring layer is 100-300nm, and the material is selected from Ti/Au alloy or Cr/Au alloy.
5. The three-dimensional optoelectronic integrated filter according to claim 1, wherein the lower filter is a through-side waveguide of a micro-ring filter, and the upper filter is a micro-ring and a down-side waveguide of the micro-ring filter.
6. A method for manufacturing a three-dimensional photoelectric integrated filter based on CMOS post-process comprises the following steps:
depositing an isolation layer above the CMOS integrated circuit and carrying out surface planarization treatment;
depositing a first optoelectronic device layer on the isolation layer and fabricating a lower filter on the first optoelectronic device layer;
depositing a monitoring layer on the first photoelectric device layer, and etching a specific area on the monitoring layer;
depositing a buffer layer on the monitoring layer, etching a monitoring step, and carrying out surface planarization treatment;
depositing a second optoelectronic device layer on the buffer layer, fabricating an upper filter on the second optoelectronic device layer, and completing an optical interconnection with the lower filter; the CMOS integrated circuit has a temperature control function and is used for carrying out automatic thermal tuning on the lower filter and the upper filter;
depositing a protective layer over said second photovoltaic device layer;
etching a plurality of through holes downwards at specific positions on the surface of the protective layer, filling metal in the through holes, and contacting with electrodes on the CMOS integrated circuit to complete electrical interconnection with the CMOS integrated circuit;
an interconnect electrode is formed over the via.
7. The method of claim 6, wherein the isolation layer, the first optoelectronic device layer, the buffer layer, the second optoelectronic device layer, and the protective layer are deposited using a PECVD process, and the monitoring layer is deposited using a vacuum evaporation process.
8. The method of claim 6, wherein the surface planarization process is performed using a chemical mechanical polishing process.
9. The method of claim 6, wherein the lower filter and the upper filter are fabricated using electron beam lithography and inductively coupled plasma etching processes.
10. The method of claim 6, wherein the via is formed using an inductively coupled plasma etching process, and wherein the metal and the interconnect electrode are formed using a sputtering process.
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