CN110068894B - Three-dimensional photoelectric integrated grating coupler realized based on CMOS (complementary metal oxide semiconductor) post-process and preparation method - Google Patents
Three-dimensional photoelectric integrated grating coupler realized based on CMOS (complementary metal oxide semiconductor) post-process and preparation method Download PDFInfo
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- G—PHYSICS
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/12002—Three-dimensional structures
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- G—PHYSICS
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
- G02B6/124—Geodesic lenses or integrated gratings
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12133—Functions
- G02B2006/12147—Coupler
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12166—Manufacturing methods
Abstract
A three-dimensional photoelectric integrated grating coupler and a preparation method thereof are provided, the three-dimensional photoelectric integrated grating coupler comprises an isolation layer, a first photoelectric device layer, a monitoring layer, a buffer layer, a second photoelectric device layer and a protective layer which are deposited on a CMOS integrated circuit from bottom to top, a plurality of through holes penetrate through the isolation layer, the first photoelectric device layer, the monitoring layer, the buffer layer, the second photoelectric device layer and the protective layer, metal is filled in the through holes and is in contact with electrodes of the CMOS integrated circuit, and interconnection electrodes are arranged above the through holes; the first photoelectric device layer is used for preparing a lower grating coupler interacting with the CMOS integrated circuit; the second optoelectronic device layer is used to fabricate an upper grating coupler that is optically interconnected with the first optoelectronic device layer. The invention can realize monolithic integration of the grating coupler and the CMOS integrated circuit, realize three-dimensional optical interconnection, reduce transmission loss of interlayer optical interconnection and maximize interlayer coupling efficiency. The invention is compatible with CMOS technology, is easy to prepare, can be used for three-dimensional photoelectric integration, and realizes the integration of high-density photoelectronic devices and microelectronic circuits.
Description
Technical Field
The invention relates to the technical field of photoelectric integration, in particular to a three-dimensional photoelectric integrated grating coupler realized based on a CMOS (complementary metal oxide semiconductor) post process and a preparation method thereof.
Background
With the continuous development of integrated circuit technology towards high speed and high integration, moore's law is facing the ultimate challenge of chip integration, and the problems of high delay, high power consumption, severe signal crosstalk and the like inevitably occur in the conventional electrical interconnection. People are thus looking to move to a new generation of interconnect technology, optical interconnects. The optical interconnection has the advantages of wide bandwidth, electromagnetic interference resistance, strong confidentiality, low loss, small power consumption and the like, and the silicon-based optical interconnection can give play to the advantages of wide bandwidth, low crosstalk, low loss and compatibility with a CMOS (complementary metal oxide semiconductor) process in optical communication.
However, current optoelectronic integrated optical interconnection schemes are limited to a single plane, i.e. different optoelectronic devices are in the same plane, and the crossing of optical waveguides in the same plane causes loss and crosstalk. On the other hand, the area of a single plane is limited, and optoelectronic devices cannot be integrated on a large scale, thereby limiting the density of optoelectronic integration and the complexity of optical interconnection systems. Therefore, it is necessary to provide a multi-dimensional optoelectronic integrated optical interconnection scheme, that is, different optoelectronic devices are in different planes, and optical signals in optical waveguides can be coupled between different planar waveguides by means of directional couplers, so that the crossing of optical waveguides in a single plane is eliminated, and loss and crosstalk caused by the crossing of the same planar waveguide are avoided. In addition, as different optoelectronic devices can be distributed on different planes, the density of optoelectronic integration and the complexity of an optical interconnection system can be greatly improved.
The three-dimensional photoelectron integrated optical interconnection scheme improves the integration level of a photoelectron integrated system to the maximum extent, optical signals of the photoelectron integrated system need to be coupled among different planes, and the requirement on the precision of the distance between different planar photoelectron device layers is high. If the spacing of the different planar optoelectronic device layers deviates from the desired value, the optical coupling loss between the layers will inevitably increase.
Disclosure of Invention
The invention aims to provide a three-dimensional photoelectric integrated grating coupler realized based on a CMOS (complementary metal oxide semiconductor) post process and a preparation method thereof, which can enhance the coupling efficiency between layers and reduce the coupling loss caused by light transmission between the layers.
In order to achieve the above object, in one aspect, the present invention provides a three-dimensional optoelectronic integrated grating coupler, including an isolation layer, a first optoelectronic device layer, a monitoring layer, a buffer layer, a second optoelectronic device layer and a protection layer deposited on a CMOS integrated circuit from bottom to top, wherein a plurality of through holes penetrate through the above layers, the through holes are filled with metal and are in contact with electrodes of the CMOS integrated circuit, and interconnection electrodes are disposed above the through holes;
the first photoelectric device layer is used for preparing a lower grating coupler which interacts with a CMOS integrated circuit; the second optoelectronic device layer is used to fabricate an upper grating coupler that is optically interconnected with the first optoelectronic device layer.
Preferably, the isolation layer has a thickness of 3 μm to 4 μm, the buffer layer has a thickness of 0.5 μm to 1.5 μm, the protection layer has a thickness of 4 μm to 5 μm, and the isolation layer, the buffer layer, and the protection layer are each independently selected from silicon oxide, aluminum oxide, and silicon oxynitride.
Preferably, the thickness of the first photoelectric device layer and the second photoelectric device layer is 220-500nm, and the materials are respectively and independently selected from Si and Si3N4Or AlN.
Preferably, the thickness of the monitoring layer is 100-300nm, and the material is selected from Ti/Au alloy or Cr/Au alloy.
In order to achieve the above object, in another aspect, the present invention further provides a method for manufacturing a three-dimensional optoelectronic integrated grating coupler based on a CMOS post-process, including the following steps:
depositing an isolation layer above the CMOS integrated circuit and carrying out surface planarization treatment;
depositing a first photoelectric device layer on the isolation layer, and preparing a lower grating coupler on the first photoelectric device layer;
depositing a monitoring layer on the first photoelectric device layer, and etching a specific area on the monitoring layer;
depositing a buffer layer on the monitoring layer, etching a monitoring step, and carrying out surface planarization treatment;
depositing a second photoelectric device layer on the buffer layer, preparing an upper grating coupler on the second photoelectric device layer, and completing optical interconnection with the lower grating coupler;
depositing a protective layer over said second photovoltaic device layer;
etching a plurality of through holes downwards at specific positions on the surface of the protective layer, filling metal in the through holes, and contacting with electrodes on the CMOS integrated circuit to complete electrical interconnection with the CMOS integrated circuit;
an interconnect electrode is formed over the via.
Preferably, the isolation layer, the first photoelectric device layer, the buffer layer, the second photoelectric device layer and the protection layer are formed by deposition through a PECVD process, and the monitoring layer is formed by deposition through a vacuum evaporation process.
Preferably, the surface planarization treatment is performed using a chemical mechanical polishing process.
Preferably, the lower grating coupler and the upper grating coupler are prepared by adopting electron beam lithography and inductively coupled plasma etching processes.
Preferably, the through hole is prepared by adopting an inductively coupled plasma etching process.
Preferably, the metal in the through hole and the interconnection electrode are prepared by a sputtering process.
Compared with the prior art, the invention has the following advantages:
1. the invention adopts a thin-film laminated stack structure, can realize optical coupling and three-dimensional optical interconnection between two layers of photoelectric devices, and improves the bandwidth of an optical interconnection link and the integration level of photoelectric integration;
2. the invention adopts a three-dimensional integration method to realize the monolithic integration of the photoelectric device and the CMOS integrated circuit;
3. according to the three-dimensional photoelectric integrated grating coupler, the lower CMOS integrated circuit has a temperature control function, and the grating coupler can work in a wide temperature range;
4. all process temperatures adopted by the invention are controlled below 400 ℃, so that the influence of high temperature on a lower-layer CMOS integrated circuit can be prevented;
5. the preparation process adopted by the invention is completely compatible with the CMOS process, and can directly deposit a film on the CMOS integrated circuit to prepare the optical layer;
6. the invention adopts the monitoring layer to monitor the chemical mechanical polishing process in real time, can accurately control the thickness between layers and can reach the nm precision;
7. the invention adopts a MultiPrep precision grinding and polishing system, and the surface roughness can reach 0.1 nm.
Drawings
FIG. 1 is a three-dimensional schematic diagram of a three-dimensional photoelectric integrated grating coupler according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a three-dimensional optoelectronic integrated grating coupler according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a process for manufacturing a three-dimensional photoelectric integrated grating coupler according to an embodiment of the present invention;
FIGS. 4A and 4B are the height difference of the surface of the silicon oxide film measured by AFM before and after chemical mechanical polishing, respectively;
FIG. 4C and FIG. 4D are the surface roughness of the silicon oxide film measured by AFM before and after chemical mechanical polishing, respectively.
Description of reference numerals:
1-a CMOS integrated circuit; 2-a silicon oxide isolation layer; 3-a first silicon nitride optoelectronic device layer; 4-a titanium monitoring layer; 5-a silicon oxide buffer layer; 6-a second silicon nitride optoelectronic device layer; 7-a silicon oxide protective layer; 8-an interconnect electrode; 9-through hole.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
The invention provides a three-dimensional photoelectric integrated grating coupler realized based on CMOS post-process, all process temperatures are controlled below 400 ℃, the influence on a CMOS integrated circuit is avoided, the monolithic integration of a photoelectric device and the CMOS integrated circuit is realized, the three-dimensional optical interconnection is realized, and the bottleneck problem of electric interconnection is solved.
Referring to fig. 1 and 2, the three-dimensional photoelectric integrated grating coupler implemented based on CMOS post-process of the present invention includes a silicon oxide isolation layer 2, a first silicon nitride photoelectric device layer 3, a titanium monitoring layer 4, a silicon oxide buffer layer 5, a second silicon nitride photoelectric device layer 6 and a silicon oxide protection layer 7 deposited on a CMOS integrated circuit 1 in sequence from bottom to top; a plurality of vias 9 pass through the above layers, are filled with metal and are in contact with the electrodes of the CMOS integrated circuit 1, and interconnect electrodes 8 are provided above the vias 9. The first silicon nitride optoelectronic device layer 3 is used for preparing a lower grating coupler interacting with the CMOS integrated circuit 1; the second silicon nitride optoelectronic device layer 6 is used to fabricate an upper grating coupler that is optically interconnected with the first silicon nitride optoelectronic device layer 3.
The thickness of the silicon oxide isolation layer 2 is 3-4 μm, the thickness of the first silicon nitride optoelectronic device layer 3 is 400nm, the thickness of the titanium monitoring layer 4 is 200nm, the thickness of the silicon oxide buffer layer 5 is 0.5-1.5 μm, the thickness of the second silicon nitride optoelectronic device layer 6 is 400nm, and the thickness of the silicon oxide protective layer 7 is 4-5 μm.
Referring to fig. 3, the method for manufacturing the three-dimensional photoelectric integrated grating coupler shown in fig. 1 of the present invention includes the following steps:
step 1: and cleaning the CMOS integrated circuit substrate. Sequentially placing into acetone and ethanol, respectively, ultrasonically oscillating at 85% power for 5min, washing with deionized water, and repeating the above process for 3 times.
Growing SiH gas by PECVD method4And N2And under the condition of O, depositing silicon oxide with the thickness of 3-4 microns on the substrate as a silicon oxide isolation layer, wherein the refractive index of the material is 1.45 (at the wavelength of 1.55 microns).
The surface of the silicon oxide isolation layer is flattened by adopting a chemical mechanical polishing method, a MultiPrep precision grinding and polishing system is selected, the rotating speed of a grinding disc is 100rpm, the rotating speed of a grinding head is 1-time, the load of a sample is 0 grade, 50nm alkaline silica gel is selected as polishing liquid, and the polishing time is 60min, so that the surface of the chip reaches the flatness of nm grade.
Step 2: growing SiH gas by PECVD method4And NH3With a material refractive index of 2 (at a wavelength of 1.55 μm) as a first silicon nitride optoelectronic device layer, silicon nitride was deposited on the planar silicon oxide spacer layer to a thickness of 400 nm.
And preparing a uniform lower grating coupler on the first silicon nitride optoelectronic device layer by adopting an Electron Beam Lithography (EBL) method and an inductively coupled plasma etching (ICP) method, wherein the period is 1.26 mu m, and the duty ratio is 0.5.
And 3, step 3: and depositing a Ti/Au alloy with the thickness of 200nm on the first silicon nitride photoelectric device layer by adopting a vacuum evaporation method to serve as a titanium monitoring layer, and then etching a specific area by adopting an ultraviolet photoetching and wet etching method.
And 4, step 4: adopting Plasma Enhanced Chemical Vapor Deposition (PECVD) to grow gasBulk SiH4 and N2And under the condition of O, silicon oxide with the thickness of 1 μm is deposited on the titanium monitoring layer to be used as a silicon oxide buffer layer, and the refractive index of the material is 1.45 (at the wavelength of 1.55 μm).
Selecting buffer solution (HF: NH) of hydrofluoric acid and ammonium fluoride by adopting ultraviolet lithography and wet etching method4F：H2O is 1: 2: 3) and corroding the silicon oxide buffer layer in the specific area to obtain a monitoring step.
The surface of the deposited chip is flattened by adopting a chemical mechanical polishing method, a MultiPrep precision grinding and polishing system is selected, the rotating speed of a grinding disc is selected to be 100rpm, the rotating speed of a grinding head is 1-time, the load of a sample is 0 grade, 20nm alkaline silica gel is selected as polishing liquid, the polishing time is 90min, the height of a step is measured by a step instrument every 10min, the surface reaches the flatness of nm grade, and the final thickness of a silicon oxide buffer layer is 400 nm.
And 5, step 5: growing SiH gas by PECVD method4And NH3With a thickness of 400nm as a second silicon nitride optoelectronic device layer deposited on a flat silicon oxide surface, the material having a refractive index of 2 (at a wavelength of 1.55 μm).
And preparing a uniform upper grating coupler on the second silicon nitride optoelectronic device layer by adopting an Electron Beam Lithography (EBL) method and an inductively coupled plasma etching (ICP) method, wherein the period is 1.26 mu m, and the duty ratio is 0.5. The horizontal displacement of the upper grating coupler and the lower grating coupler is 0, and the vertical displacement is 800 nm. The upper grating coupler and the lower grating coupler need to be strictly aligned, i.e. registered. The alignment precision is 20 nm.
And 6, step 6: growing SiH gas by PECVD method4And N2And under the condition of O, depositing silicon oxide with the thickness of 4-5 microns on the silicon nitride optoelectronic device layer to serve as a silicon oxide protective layer, wherein the refractive index of the material is 1.45 (at the wavelength of 1.55 microns).
And 7, step 7: and downwards etching a plurality of through holes at specific positions on the surface of the silicon oxide protective layer by an inductive coupling plasma etching process, filling metal in the through holes by a sputtering process, and contacting with electrodes on the CMOS integrated circuit to complete electrical interconnection with the CMOS integrated circuit.
And 8, step 8: and depositing aluminum-copper alloy on the surface of the silicon nitride photoelectric device layer above the through hole by a sputtering method to be used as a gold interconnection electrode, thereby completing the preparation.
As can be seen from fig. 4A, 4B, 4C and 4D: before chemical mechanical polishing, the difference in height of the surface of the silicon oxide film is 1.326 μm as shown in FIG. 4A, and the surface roughness is 489.07nm as shown in FIG. 4C; after chemical mechanical polishing using the MultiPrep precision polishing system, the surface height difference of the silicon oxide film is 0.0218 μm as shown in FIG. 4B, and the surface roughness is 0.081nm as shown in FIG. 4D. Before and after chemical mechanical polishing, the height difference of the surface of the silicon oxide film is reduced by two orders of magnitude, and the surface roughness is reduced by three orders of magnitude to reach a sub-nanometer order. The data fully show that the ultra-precision effects of nano-scale surface flatness and sub-nano-scale surface roughness can be achieved by adopting a MultiPrep precision grinding and polishing system to carry out a surface planarization process.
The invention adopts a mode compatible with CMOS post-process to deposit a plurality of silicon nitride optical device layers on an IC integrated circuit to prepare the three-dimensional space grating coupler, thereby realizing the high-efficiency coupling of light among different planes and increasing the tolerance of coupling space between layers. Meanwhile, the resonant wavelength and the coupling coefficient of the grating coupler can be modulated through the bottom temperature control circuit, and low-loss transmission and high-efficiency coupling of different wavelengths of light between layers are achieved.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in more detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit, concept and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A three-dimensional photoelectric integrated grating coupler realized based on a CMOS (complementary metal oxide semiconductor) post process comprises an isolation layer, a first photoelectric device layer, a monitoring layer, a buffer layer, a second photoelectric device layer and a protective layer which are deposited on a CMOS integrated circuit from bottom to top, wherein a plurality of through holes penetrate through the isolation layer, the first photoelectric device layer, the monitoring layer, the buffer layer, the second photoelectric device layer and the protective layer, metal is filled in the through holes and is in contact with electrodes of the CMOS integrated circuit, and interconnection electrodes are arranged above;
the first photoelectric device layer is used for preparing a lower grating coupler which interacts with a CMOS integrated circuit; the second optoelectronic device layer is used to fabricate an upper grating coupler that is optically interconnected with the first optoelectronic device layer.
2. The three-dimensional optoelectronic integrated grating coupler of claim 1, wherein the isolation layer has a thickness of 3 μm to 4 μm, the buffer layer has a thickness of 0.5 μm to 1.5 μm, the protection layer has a thickness of 4 μm to 5 μm, and the isolation layer, the buffer layer, and the protection layer are made of materials independently selected from silicon oxide, aluminum oxide, and silicon oxynitride.
3. The three-dimensional optoelectronic integrated grating coupler of claim 1 wherein the first optoelectronic device layer and the second optoelectronic device layer have a thickness of 220-500nm, and the materials are independently selected from Si and Si, respectively3N4Or AlN.
4. The three-dimensional optoelectronic integrated grating coupler as claimed in claim 1, wherein the thickness of the monitoring layer is 100 nm and 300nm, and the material is selected from Ti/Au alloy or Cr/Au alloy.
5. A preparation method of a three-dimensional photoelectric integrated grating coupler realized based on a CMOS post-process comprises the following steps:
depositing an isolation layer above the CMOS integrated circuit and carrying out surface planarization treatment;
depositing a first photoelectric device layer on the isolation layer, and preparing a lower grating coupler on the first photoelectric device layer;
depositing a monitoring layer on the first photoelectric device layer, and etching a specific area on the monitoring layer;
depositing a buffer layer on the monitoring layer, etching a monitoring step, and carrying out surface planarization treatment;
depositing a second photoelectric device layer on the buffer layer, preparing an upper grating coupler on the second photoelectric device layer, and completing optical interconnection with the lower grating coupler;
depositing a protective layer over said second photovoltaic device layer;
etching a plurality of through holes downwards at specific positions on the surface of the protective layer, filling metal in the through holes, and contacting with electrodes on the CMOS integrated circuit to complete electrical interconnection with the CMOS integrated circuit;
an interconnect electrode is formed over the via.
6. The method of claim 5, wherein the isolation layer, the first optoelectronic device layer, the buffer layer, the second optoelectronic device layer and the protection layer are deposited by a PECVD process, and the monitoring layer is deposited by a vacuum evaporation process.
7. The method for manufacturing a three-dimensional optoelectronic integrated grating coupler based on CMOS post-process as claimed in claim 5, wherein the surface planarization process is performed by a chemical mechanical polishing process.
8. The method for manufacturing a three-dimensional photoelectric integrated grating coupler based on the CMOS post-process as claimed in claim 5, wherein the lower grating coupler and the upper grating coupler are manufactured by using electron beam lithography and inductively coupled plasma etching processes.
9. The method for manufacturing a three-dimensional photoelectric integrated grating coupler based on the CMOS post-process as claimed in claim 5, wherein the through hole is manufactured by an inductively coupled plasma etching process.
10. The method for manufacturing a three-dimensional optoelectronic integrated grating coupler based on CMOS post-process as claimed in claim 5, wherein the metal and interconnection electrodes in the through-hole are manufactured by sputtering process.
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