CN108321119A - The three-dimensional light realized based on technique after CMOS is electrically integrated filter and preparation method thereof - Google Patents
The three-dimensional light realized based on technique after CMOS is electrically integrated filter and preparation method thereof Download PDFInfo
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- CN108321119A CN108321119A CN201810062157.5A CN201810062157A CN108321119A CN 108321119 A CN108321119 A CN 108321119A CN 201810062157 A CN201810062157 A CN 201810062157A CN 108321119 A CN108321119 A CN 108321119A
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
Abstract
A kind of three-dimensional light is electrically integrated filter and preparation method thereof, including：Separation layer, the first photoelectric device layer, monitor layer, buffer layer, the second photoelectric device layer and the protective layer being sequentially deposited at from bottom to top on CMOS integrated circuits; multiple through-holes pass through above layers; it is filled with metal in the through-hole and is contacted with the electrode of CMOS integrated circuits, interconnection electrode is provided with above through-hole；Wherein, the first photoelectric device layer is used to prepare the lower layer's filter to interact with CMOS integrated circuits；Second photoelectric device layer is used to prepare the upper layer filter that light network is carried out with the first photoelectric device layer.The present invention can both solve the loss and crosstalk of optoelectronic intagration light network in single plane, realize multidimensional optoelectronic intagration in multiple planes, improve the density of optoelectronic intagration and the complexity of optical interconnection system；Dependence of the micro-loop filter to environment temperature can be solved again, and the purpose of wide operating temperature range is realized in the automatic thermal tuning by bottom temperature control circuit to top layer filter.
Description
Technical field
The present invention relates to optoelectronic integrated technology fields, more particularly to the three-dimensional light realized based on technique after CMOS is electrically integrated filter
Wave device and preparation method thereof.
Background technology
As integrated circuit technique constantly develops to the direction of high speed and high integration, Moore's Law is faced with integrated chip
Ultimate challenge, inevitably there is the problems such as high latency, high power consumption and severe signal crosstalk in traditional electrical interconnection.Then
Sight has been turned to interconnection technique of new generation by people --- light network.Light network has wide bandwidth, electromagnetism interference, strong secrecy
The advantages such as property, low-loss and low power consumption, and silicon-based optical interconnection can play optic communication wide bandwidth, low crosstalk, low-loss, with CMOS
The advantages of process compatible.
However current optoelectronic intagration light network scheme is limited only in single plane, i.e., different opto-electronic devices exists
In approximately the same plane, intersection of the optical waveguide in approximately the same plane can cause loss and crosstalk.On the other hand, the face of single plane
Product it is limited, can not large-scale integrated opto-electronic device, to limit the density of optoelectronic intagration and the complexity of optical interconnection system
Degree.It is therefore desirable to propose the optoelectronic intagration light network scheme of multidimensional, i.e., different opto-electronic devices in different planes,
Optical signal in optical waveguide can realize the coupling between Different Plane waveguide by directional coupler, single flat to eliminate
The intersection of optical waveguide in face avoids loss and crosstalk caused by the intersection of same plane waveguide.In addition, due to different photoelectrons
Device can be distributed the complexity of density and optical interconnection system that optoelectronic intagration can be greatly improved on a different plane.
Using wavelength-division multiplex (WDM) technology, the utilization rate of spectrum in optoelectronic intagration optical interconnection system can be effectively improved, is made
It obtains optical interconnection link and obtains higher bandwidth.The optical add/drop multiplexer that micro-loop filter is constituted is the Primary Component in wdm system.
Since micro-loop filter has greater compactness of size, good wavelength selectivity, and itself just has upload/download energy
Power, therefore what micro-loop filter can be more flexible applies in optical interconnection system.Si-based OEIC optical interconnection system at present
In generally use silicon-based micro ring filter as multiplexing and demultiplexer.Multiplexing based on micro-loop filter and demultiplexer advantage
Small, to be easy on piece integrated, very strict to operating temperature requirements the disadvantage is that extremely sensitive to temperature change, very little
Temperature drift may result in the drift of centre wavelength.
Invention content
It is an object of the invention to propose that a kind of three-dimensional light realized based on technique after CMOS is electrically integrated filter and its system
Preparation Method can automatically adjust the operating temperature of top layer micro-loop filter by the temperature control circuit of bottom, can solve micro-loop filter
Dependence of the wave device to environment temperature, realizes the purpose of wide operating temperature range.
To achieve the above object, on the one hand, the present invention propose a kind of three-dimensional light be electrically integrated filter include from bottom to top according to
The secondary separation layer being deposited on CMOS integrated circuits, the first photoelectric device layer, monitor layer, buffer layer, the second photoelectric device layer and
Protective layer, multiple through-holes pass through above layers, and metal is filled in the through-hole and is contacted with the electrode of CMOS integrated circuits, institute
It states and is provided with interconnection electrode above through-hole；
Wherein：The first photoelectric device layer is used to prepare the lower layer's filter to interact with CMOS integrated circuits；Institute
It states the second photoelectric device layer and is used to prepare the upper layer filter for carrying out light network with the first photoelectric device layer.
Preferably, the thickness of the separation layer is 3 μm~4 μm, the thickness of the buffer layer is 0.5-1.5 μm, described
The thickness of protective layer is 4 μm~5 μm, and the material of the separation layer, the buffer layer and the protective layer is separately selected from
Silica, aluminium oxide or silicon oxynitride.
Preferably, the thickness of the first photoelectric device layer and the second photoelectric device layer is 220-500nm, material
Separately it is selected from Si, Si3N4Or AlN.
Preferably, the thickness of the monitor layer is 100-300nm, material is selected from Ti/Au alloys or Cr/Au alloys.
Preferably, lower layer's filter is the straight-through end waveguide of micro-loop filter, the upper layer filter is micro-loop
The micro-loop of filter and downloading end waveguide.
To achieve the above object, on the other hand, the present invention also proposes a kind of three-dimensional photoelectricity realized based on technique after CMOS
The production method of integrated filter, includes the following steps：
A separation layer is deposited above CMOS integrated circuits, and carries out surface planarisation processing；
The first photoelectric device layer is deposited on the separation layer, and lower layer's filtering is prepared on the first photoelectric device layer
Device；
A monitor layer is deposited on the first photoelectric device layer, and etches specific region on the monitor layer；
A buffer layer is deposited on the monitor layer, etches monitoring step, and carry out surface planarisation processing；
The second photoelectric device layer is deposited on the buffer layer, and upper layer filtering is prepared on the second photoelectric device layer
Device, and complete the light network with lower layer's filter；
A protective layer is deposited on the second photoelectric device layer；
Multiple through-holes are etched downwards in the protective layer specific position, and fill metal in the through-hole, with
Electrode contact on CMOS integrated circuits, is completed and CMOS integrated circuit electricity interlinkages；
Interconnection electrode is formed above the through-hole.
Preferably, the separation layer, the first photoelectric device layer, the buffer layer, the second photoelectric device layer
It deposits to be formed using pecvd process with the protective layer, the monitor layer deposits to be formed using vacuum evaporation technology.
Preferably, the surface planarisation processing is carried out using CMP process.
Preferably, lower layer's filter and the upper layer filter use electron beam lithography and inductive couple plasma
It is prepared by body etching technics.
Preferably, the through-hole is prepared using sense coupling technique.
Preferably, metal and interconnection electrode are prepared using sputtering technology in the through-hole.
The present invention has the following advantages that compared with prior art：
1, the present invention uses film stratiform stacked structure, it can be achieved that optical coupling and three-dimensional light between two layers of photoelectric device are mutual
Even, the bandwidth of optical interconnection link and the integrated level that photoelectricity is integrated are improved；
2, the present invention uses three-dimensionally integrated method, realizes the single-chip integration of photoelectric device and CMOS integrated circuits；
3, the three-dimensional light realized of the present invention is electrically integrated filter, lower layer's CMOS integrated circuits there is function of temperature control, it can be achieved that
The wide temperature range of filter works；
4, all technological temperatures that the present invention uses are controlled at 400 DEG C hereinafter, high temperature can be prevented integrated to lower layer CMOS
Circuit impacts；
5, the preparation process that uses of the present invention is completely compatible with CMOS technology, can directly on CMOS integrated circuits deposit thin
Film preparation optical layer；
6, the present invention monitors CMP process using monitor layer in real time, accurately controls layer thickness,
Up to nm precision；
7, the present invention uses MultiPrep precise finiss polishing systems, and surface roughness is up to 0.1nm.
Description of the drawings
Fig. 1 is the structure three-dimensional schematic diagram that three-dimensional light is electrically integrated filter in the embodiment of the present invention；
Fig. 2 is the structural profile illustration that three-dimensional light is electrically integrated filter in the embodiment of the present invention；
Fig. 3 is the preparation process flow schematic diagram that three-dimensional light is electrically integrated filter in the embodiment of the present invention；
Fig. 4 A and Fig. 4 B are respectively the silicon oxide film surface for chemically-mechanicapolish polishing front and back AFM in the embodiment of the present invention and measuring
Difference in height；
Fig. 4 C and Fig. 4 D are respectively the silicon oxide film surface for chemically-mechanicapolish polishing front and back AFM in the embodiment of the present invention and measuring
Roughness.
Reference sign：
1-CMOS integrated circuits；2- silica separation layers；3- first nitrogenizes silicon photoelectric device layer；4- titanium monitor layers；5-
Aoxidize silicon buffer layer；6- second nitrogenizes silicon photoelectric device layer；7- silicon oxide protective layers；8- interconnection electrodes；9- through-holes.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing is described in further detail the present invention.
The present invention proposes that a kind of three-dimensional light realized based on technique after CMOS is electrically integrated filter, and all technological temperatures are controlled
System hereinafter, avoid impacting CMOS integrated circuits, realizes photoelectric device and CMOS integrated circuit single-chip integrations at 400 DEG C,
It realizes three-dimensional light network simultaneously, solves the bottleneck problem of electrical interconnection.
Referring to Figures 1 and 2, the three-dimensional light realized the present invention is based on technique after CMOS is electrically integrated filter, including from lower and
On be sequentially deposited at silica separation layer 2, first on CMOS integrated circuits 1 nitrogenize silicon photoelectric device layer 3, titanium monitor layer 4,
It aoxidizes silicon buffer layer 5, second and nitrogenizes silicon photoelectric device layer 6 and silicon oxide protective layer 7；Multiple through-holes 9 pass through above layers, wherein
Filling metal is simultaneously contacted with the electrode of CMOS integrated circuits 1, and 9 top of through-hole is provided with interconnection electrode 8.First silicon nitride phototube
Part layer 3 is used to prepare the lower layer's filter to interact with CMOS integrated circuits 1；Second nitridation silicon photoelectric device layer 6 is for making
The standby upper layer filter that light network is carried out with the first nitridation silicon photoelectric device layer 3.
The thickness of silica separation layer 2 is 3 μm~4 μm, and the thickness of the first nitridation silicon photoelectric device layer 3 is 400nm, titanium
The thickness of monitor layer 4 is 200nm, and the thickness of oxidation silicon buffer layer 5 is 1 μm, and the thickness of the second nitridation silicon photoelectric device layer 6 is
The thickness of 400nm, silicon oxide protective layer 7 are 4 μm~5 μm.
Three-dimensional light in this embodiment is electrically integrated in filter, and light is coupled to upper layer by layer coupling from lower layer's waveguide
Micro-loop filter is coupled to from upper layer waveguide in lower layer's micro-loop filter.
As shown in figure 3, the preparation method that present invention three-dimensional light shown in FIG. 1 is electrically integrated filter includes the following steps：
1st step：Clean CMOS IC substrates.The power ultrasonic in acetone, ethyl alcohol respectively with 85% is sequentially placed into shake
5min is swung, is then rinsed with a large amount of deionized waters, the above process is repeated 3 times.
Using plasma enhances CVD method PECVD, growth gasses SiH4And N2Under conditions of O, on substrate
For the silica that deposition thickness is 3 μm~4 μm as silica separation layer, Refractive Index of Material is 1.45 (at 1.55 μm of wavelength).
Surface planarisation is carried out to silica separation layer using chemical mechanical polishing method, chooses MultiPrep precise finiss
Polishing system, selection lap speed are 100rpm, and abrasive power head rotating speed is 1 speed, and it is 0 grade that sample, which bears a heavy burden, and polishing fluid is chosen
50nm alkaline silica gels, polishing time 60min make chip surface reach the flatness of nm magnitudes.
2nd step：Using plasma enhances CVD method PECVD, growth gasses SiH4 and NH3Under conditions of,
The silicon nitride that deposition thickness is 400nm on flat silica separation layer is as the first nitridation silicon photoelectric device layer, material folding
It is 2 (at 1.55 μm of wavelength) to penetrate rate.
Using E-beam lithography EBL, sense coupling method ICP, silicon photoelectric device layer is nitrogenized first
The straight-through end waveguide of micro-loop filter is prepared, waveguide cross-sectional dimensions are 400nm × 1 μm.
3rd step：Using vacuum vapor deposition method, deposition thickness is 200nmTi/Au alloy conducts on nitridation silicon photoelectric device layer
Titanium monitor layer uses ultraviolet photolithographic and wet etching method to etch specific region later.
4th step：Using plasma enhances CVD method PECVD, growth gasses SiH4And N2Under conditions of O,
For the silica that deposition thickness is 1 μm on titanium monitor layer as oxidation silicon buffer layer, Refractive Index of Material is 1.45 (1.55 μm of wavelength
Place).
Using ultraviolet photolithographic and wet etching method, the buffer solution (HF of hydrofluoric acid and ammonium fluoride is chosen：NH4F：H2O=1：2：
3), in specific region corrosion oxidation silicon buffer layer, monitoring step is obtained.
Surface planarisation is carried out to the chip after deposit using chemical mechanical polishing method, chooses MultiPrep precise finiss
Polishing system, selection lap speed are 100rpm, and abrasive power head rotating speed is 1 speed, and it is 0 grade that sample, which bears a heavy burden, and polishing fluid is chosen
20nm alkaline silica gels, polishing time 90min are used in combination step instrument to measure step height per 10min, and surface is made to reach the flat of nm magnitudes
Smooth degree, and it is 400nm to aoxidize silicon buffer layer final thickness.
5th step：Using plasma enhances CVD method PECVD, growth gasses SiH4And NH3Under conditions of,
The silicon nitride that flat silica buffer-layer surface deposition thickness is 400nm is as the second nitridation silicon photoelectric device layer, material folding
It is 2 (at 1.55 μm of wavelength) to penetrate rate.
Using E-beam lithography EBL, sense coupling method ICP, silicon photoelectric device layer is nitrogenized second
Prepare micro-loop and the downloading end waveguide of micro-loop filter.Micro-loop sectional dimension is 400nm × 1 μm, and radius is 30 μm, micro-loop and bottom
The straight-through end waveguide horizontal displacement of layer is 300nm, vertical displacement 800nm；Downloading end waveguide cross-sectional dimensions are 400nm × 1 μm, with
The level interval of micro-loop is 300nm.Second nitridation silicon photoelectric device layer micro-loop and the first straight-through end wave of nitridation silicon photoelectric device layer
It leads and needs to carry out stringent alignment, i.e. alignment.Alignment precision is 20nm.
6th step：Using plasma enhances CVD method PECVD, growth gasses SiH4And N2Under conditions of O,
As silicon oxide protective layer, Refractive Index of Material is the silica that deposition thickness is 4 μm~5 μm on second nitridation silicon photoelectric device layer
1.45 (at 1.55 μm of wavelength).
7th step：On silicon oxide protective layer surface, specific position is downward, is etched by sense coupling technique
Multiple through-holes fill metal in through-holes by sputtering technology, are contacted with the electrode on CMOS integrated circuits, complete and CMOS collection
At circuit electricity interlinkage.
8th step：Above through-hole, silicon oxide protective layer surface deposits aluminium copper by sputtering method and is used as interconnection electrode,
It completes to prepare.
It can be seen that from Fig. 4 A, 4B, 4C and 4D：Before chemically mechanical polishing, silicon oxide film apparent height is shown in Fig. 4 A
Difference is 1.326 μm, and display surface roughness is 489.07nm in Fig. 4 C；Using the precise polished cycle chemistry machineries of MultiPrep
After polishing, show that silicon oxide film surface height difference is 0.0218 μm in Fig. 4 B, display surface roughness is in Fig. 4 D
0.081nm.Before and after chemically mechanical polishing, silicon oxide film surface height difference reduces two orders of magnitude, and surface roughness reduces three
A order of magnitude reaches sub-nanometer magnitude.Above-mentioned data are fully shown, table is carried out using MultiPrep precise finiss polishing systems
Face flatening process can reach the ultraprecise effect of nanometer scale surface flatness and sub-nanometer magnitude surface roughness.
The three-dimensional light proposed by the present invention realized based on technique after CMOS is electrically integrated filter, can both solve single plane
The loss and crosstalk of interior optoelectronic intagration light network realize multidimensional optoelectronic intagration in multiple planes, improve optoelectronic intagration
The complexity of density and optical interconnection system；Dependence of the micro-loop filter to environment temperature can be solved again, pass through bottom temperature control electricity
The purpose of wide temperature range work is realized in automatic thermal tuning of the road to top layer filter.
Particular embodiments described above to the purpose of the present invention, technical solution and advantageous effect relatively in detail have
The explanation of body is not limited to this hair it should be understood that above-described is only specific embodiments of the present invention
Bright, all in the spirit, thought and spirit of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of three-dimensional light realized based on technique after CMOS is electrically integrated filter, including：It is sequentially deposited at CMOS from bottom to top
Separation layer, the first photoelectric device layer, monitor layer, buffer layer, the second photoelectric device layer on integrated circuit and protective layer, Duo Getong
Hole passes through above layers, and metal is filled in the through-hole and is contacted with the electrode of CMOS integrated circuits, is set above the through-hole
It is equipped with interconnection electrode；
Wherein, the first photoelectric device layer is used to prepare the lower layer's filter to interact with CMOS integrated circuits；Described
Two photoelectric device layers are used to prepare the upper layer filter that light network is carried out with the first photoelectric device layer.
2. three-dimensional light as described in claim 1 is electrically integrated filter, which is characterized in that the thickness of the separation layer is 3 μm~4
μm, the thickness of the buffer layer is 0.5-1.5 μm, and the thickness of the protective layer is 4 μm~5 μm, the separation layer, the buffering
The material of layer and the protective layer is separately selected from silica, aluminium oxide or silicon oxynitride.
3. three-dimensional light as described in claim 1 is electrically integrated filter, which is characterized in that the first photoelectric device layer and described
The thickness of second photoelectric device layer is 220-500nm, and material is separately selected from Si, Si3N4Or AlN.
4. three-dimensional light as described in claim 1 is electrically integrated filter, which is characterized in that the thickness of the monitor layer is 100-
300nm, material are selected from Ti/Au alloys or Cr/Au alloys.
5. three-dimensional light as described in claim 1 is electrically integrated filter, which is characterized in that lower layer's filter filters for micro-loop
The straight-through end waveguide of device, the upper layer filter are micro-loop and the downloading end waveguide of micro-loop filter.
6. a kind of production method that the three-dimensional light realized based on technique after CMOS is electrically integrated filter, includes the following steps：
A separation layer is deposited above CMOS integrated circuits, and carries out surface planarisation processing；
The first photoelectric device layer is deposited on the separation layer, and lower layer's filter is prepared on the first photoelectric device layer；
A monitor layer is deposited on the first photoelectric device layer, and etches specific region on the monitor layer；
A buffer layer is deposited on the monitor layer, etches monitoring step, and carry out surface planarisation processing；
The second photoelectric device layer is deposited on the buffer layer, and upper layer filter is prepared on the second photoelectric device layer, and
Complete the light network with lower layer's filter；
A protective layer is deposited on the second photoelectric device layer；
Multiple through-holes are etched downwards in the protective layer specific position, and fill metal in the through-hole, with CMOS collection
At the electrode contact on circuit, complete and CMOS integrated circuit electricity interlinkages；
Interconnection electrode is formed above the through-hole.
7. production method as claimed in claim 6, which is characterized in that the separation layer, the first photoelectric device layer, described
Buffer layer, the second photoelectric device layer and the protective layer deposit to be formed using pecvd process, and the monitor layer uses vacuum
Evaporation technology deposits to be formed.
8. production method as claimed in claim 6, which is characterized in that the surface planarisation processing is using chemically mechanical polishing
Technique carries out.
9. production method as claimed in claim 6, which is characterized in that lower layer's filter and the upper layer filter use
It is prepared by electron beam lithography and sense coupling technique.
10. production method as claimed in claim 6, which is characterized in that the through-hole uses sense coupling
Prepared by technique, preferably, metal and interconnection electrode are prepared using sputtering technology in the through-hole.
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| CN109143465A (en) * | 2018-09-03 | 2019-01-04 | 中国科学院微电子研究所 | A kind of forming method of optical waveguide device |
| CN111007592A (en) * | 2019-11-22 | 2020-04-14 | 河南仕佳光子科技股份有限公司 | 3dB directional coupler capable of shortening coupling length and manufacturing method thereof |
| CN111367013A (en) * | 2020-03-12 | 2020-07-03 | 华东师范大学 | Lithium niobate micro-ring and waveguide integrated device and preparation method thereof |
| CN111367013B (en) * | 2020-03-12 | 2021-11-19 | 华东师范大学 | Lithium niobate micro-ring and waveguide integrated device and preparation method thereof |
| CN113777809A (en) * | 2021-09-13 | 2021-12-10 | 苏州微光电子融合技术研究院有限公司 | Three-dimensional integrated device and method based on electro-optical modulator and driving circuit |
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