CN114285385A - Offset circuit of operational amplifier input current - Google Patents
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Abstract
The invention discloses a cancellation circuit of operational amplifier input current, comprising: a differential input stage, an input current cancellation circuit and an output stage; the first end of the differential input stage and the first end of the input current counteracting circuit are connected and then connected with the positive and negative input ends, the second end of the differential input stage and the second end of the input current counteracting circuit are connected and then connected with the power supply, the third end of the differential input stage and the third end of the input current counteracting circuit are connected and then connected with the bias voltage, and the fourth end of the differential input stage and the fourth end of the input current counteracting circuit are connected and then grounded; the fifth end of the differential input stage is connected with the first end of the output stage, and the second end of the output stage is connected with the voltage output end. The invention greatly reduces the input current of the differential input stage and realizes that the input impedance of the operational amplifier approaches infinity.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a cancellation circuit of an input current of an operational amplifier.
Background
Operational amplifiers are widely used in various electronic circuits or integrated circuits, and the operational amplifiers play a very important role as basic core devices in different electronic products. Operational amplifiers are used in a variety of circuits, and different application scenarios "idealize" the common parameters of an operational amplifier, such as an infinite input resistance, a very small output resistance, and a zero input offset voltage.
However, these idealized parameters are difficult to achieve in practice for the reasons: the input stage of the operational amplifier is usually provided with a triode (bipolar) type differential input pair or a MOSFET type differential input pair. The triode differential input pair has the advantages of low noise and small offset voltage, which is usually less than 1mV, and the offset voltage of the MOSFET type differential input pair is usually more than 10mV without adding any correction circuit. Based on the above advantages, in many integrated circuits of BCD (Bipolar-CMOS-DMOS) process, the differential input pair of the operational amplifier employs a triode.
However, the following drawbacks still exist for the transistor as a differential input pair: the base current exists at the input of the triode, although the beta value of the triode is very large, so that the base current can be reduced to nA level. However, compared with the input current of the pA stage of the MOSFET transistor, the input impedance of the triode as a differential input is difficult to be close to "infinity", which limits the practical application of the triode as the input stage of the operational amplifier.
Disclosure of Invention
The invention aims to provide a cancellation circuit of an input current of an operational amplifier, which is used for solving the technical problem of poor application effect of an input stage of the operational amplifier in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a cancellation circuit of operational amplifier input current, comprising: a differential input stage, an input current cancellation circuit and an output stage;
the first end of the differential input stage and the first end of the input current counteracting circuit are connected and then connected to a positive input end and a negative input end, the second end of the differential input stage and the second end of the input current counteracting circuit are connected and then connected to a power supply, the third end of the differential input stage and the third end of the input current counteracting circuit are connected and then connected to a bias voltage, and the fourth end of the differential input stage and the fourth end of the input current counteracting circuit are connected and then grounded;
the fifth end of the differential input stage is connected with the first end of the output stage, and the second end of the output stage is connected with the voltage output end.
In one possible design, the differential input stage includes a first NPN transistor Q1, a second NPN transistor Q2, a first resistor R1, a second resistor R2, a third NPN transistor Q3, and a third resistor R3;
a base electrode of the first NPN type triode Q1 is connected to a positive input end VP, a collector electrode of the first NPN type triode Q1 is connected to a first end of the second resistor R2, an emitter electrode of the first NPN type triode Q1 is connected to a collector electrode of the third NPN type triode Q3, and a second end of the second resistor R2 is connected to a power supply VCC;
a base electrode of the second NPN triode Q2 is connected to a negative input terminal VN, a collector electrode of the second NPN triode Q2 is connected to a first end of the first resistor R1, an emitter electrode of the second NPN triode Q2 is connected to a collector electrode of the third NPN triode Q3, and a second end of the first resistor R1 is connected to a power supply VCC;
a base electrode of the third NPN transistor Q3 is connected to a bias voltage VBIAS, an emitter electrode of the third NPN transistor Q3 is connected to a first end of the third resistor R3, and a second end of the third resistor R3 is grounded.
In one possible design, the input current cancellation circuit includes a first PNP transistor Q6, a second PNP transistor Q7, a third PNP transistor Q8, a fourth PNP transistor Q9, a fourth NPN transistor Q4, a fifth NPN transistor Q5, and a fourth resistor R4;
an emitting electrode of the first PNP triode Q6 and an emitting electrode of the second PNP triode Q7 are both connected to a power supply, a base electrode of the first PNP triode Q6 and a base electrode of the second PNP triode Q7 are connected to a collector electrode of the first PNP triode Q6 and a base electrode of the fifth NPN triode Q5 respectively, and a collector electrode of the second PNP triode Q7 is connected to an emitting electrode of the third PNP triode Q8 and an emitting electrode of the fourth PNP triode Q9 respectively;
the base electrode of the third PNP triode Q8 and the base electrode of the fourth PNP triode Q9 are connected and then connected to the emitter electrode of the fifth NPN triode Q5, the collector electrode of the third PNP triode Q8 is connected to the negative input terminal VN, and the collector electrode of the fourth PNP triode Q9 is connected to the positive input terminal VP;
a base electrode of the fifth NPN transistor Q5 is connected to a collector electrode of the first PNP transistor Q6, a collector electrode of the fifth NPN transistor Q5 is connected to the power supply VCC, and an emitter electrode of the fifth NPN transistor Q5 is connected to a base electrode of the third PNP transistor Q8, a base electrode of the fourth PNP transistor Q9, and a collector electrode of the fourth NPN transistor Q4, respectively;
a base electrode of the fourth NPN transistor Q4 is connected to a bias voltage VBIAS, an emitter electrode of the fourth NPN transistor Q4 is connected to a first end of the fourth resistor R4, and a second end of the fourth resistor R4 is grounded.
In one possible design, the first terminal of the output stage is connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, respectively.
In one possible design, the third NPN transistor Q3 and the fourth NPN transistor Q4 are a set 1: 1 mirror current mirror.
In one possible design, the emitter areas of the fifth NPN transistor Q5, the first NPN transistor Q1, and the second NPN transistor Q2 are equal.
In one possible design, the first PNP transistor Q6 and the second PNP transistor Q7 are a set 1: 1 mirror current mirror.
In one possible design, the third PNP transistor Q8 and the fourth PNP transistor Q9 are in a set 1: 1 mirror current mirror.
In one possible design, the input current of the operational amplifier
The calculation formula is as follows:
Has the advantages that:
the input stage of the operational amplifier is provided with the triode as the differential pair transistor, and one side of the differential pair transistor is provided with the current offset circuit for offsetting the base current of the differential pair transistor, so that the input current of the differential input stage is greatly reduced, and the input impedance of the operational amplifier approaches infinity on the premise of keeping the advantages of low noise and small offset voltage of the triode differential input pair.
Drawings
Fig. 1 is a schematic structural diagram of a cancellation circuit of an operational amplifier input current in the present embodiment;
fig. 2 is a schematic diagram illustrating the current flow of the cancellation circuit for the input current of the operational amplifier in this embodiment.
1-a differential input stage; 2-an input current cancellation circuit; 3-output stage.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments in the present description, belong to the protection scope of the present invention.
Examples
In order to solve the technical problems that input impedance of a triode as differential input is difficult to approach to infinity and application of the triode as an input stage of an operational amplifier in practice is limited in the prior art, the embodiment of the application provides a cancellation circuit of input current of the operational amplifier.
As shown in fig. 1 and fig. 2, in a first aspect, the present invention provides a cancellation circuit for an input current of an operational amplifier, including: a differential input stage 1, an input current cancellation circuit 2 and an output stage 3;
the first end of the differential input stage 1 and the first end of the input current counteracting circuit 2 are connected and then connected to a positive input end and a negative input end, the second end of the differential input stage 1 and the second end of the input current counteracting circuit 2 are connected and then connected to a power supply, the third end of the differential input stage 1 and the third end of the input current counteracting circuit 2 are connected and then connected to a bias voltage, and the fourth end of the differential input stage 1 and the fourth end of the input current counteracting circuit 2 are connected and then grounded; the fifth terminal of the differential input stage 1 is connected to the first terminal of the output stage 3, and the second terminal of the output stage 3 is connected to the voltage output terminal.
Based on the above disclosure, in this embodiment, the triode is arranged at the input stage of the operational amplifier as the differential pair transistor, and the current cancellation circuit is arranged at one side of the differential pair transistor to cancel the base current of the differential pair transistor, so that the input current of the differential input stage 1 is greatly reduced, and on the premise of keeping the advantages of low noise and small offset voltage of the triode differential input pair, the input impedance of the operational amplifier approaches infinity is realized.
In a specific embodiment, the differential input stage 1 includes a first NPN transistor Q1, a second NPN transistor Q2, a first resistor R1, a second resistor R2, a third NPN transistor Q3, and a third resistor R3;
a base electrode of the first NPN type triode Q1 is connected to a positive input end VP, a collector electrode of the first NPN type triode Q1 is connected to a first end of the second resistor R2, an emitter electrode of the first NPN type triode Q1 is connected to a collector electrode of the third NPN type triode Q3, and a second end of the second resistor R2 is connected to a power supply VCC;
a base electrode of the second NPN triode Q2 is connected to a negative input terminal VN, a collector electrode of the second NPN triode Q2 is connected to a first end of the first resistor R1, an emitter electrode of the second NPN triode Q2 is connected to a collector electrode of the third NPN triode Q3, and a second end of the first resistor R1 is connected to a power supply VCC;
a base electrode of the third NPN transistor Q3 is connected to a bias voltage VBIAS, an emitter electrode of the third NPN transistor Q3 is connected to a first end of the third resistor R3, and a second end of the third resistor R3 is grounded.
In a specific embodiment, the input current cancellation circuit 2 includes a first PNP transistor Q6, a second PNP transistor Q7, a third PNP transistor Q8, a fourth PNP transistor Q9, a fourth NPN transistor Q4, a fifth NPN transistor Q5, and a fourth resistor R4;
an emitting electrode of the first PNP triode Q6 and an emitting electrode of the second PNP triode Q7 are both connected to a power supply, a base electrode of the first PNP triode Q6 and a base electrode of the second PNP triode Q7 are connected to a collector electrode of the first PNP triode Q6 and a base electrode of the fifth NPN triode Q5 respectively, and a collector electrode of the second PNP triode Q7 is connected to an emitting electrode of the third PNP triode Q8 and an emitting electrode of the fourth PNP triode Q9 respectively;
the base electrode of the third PNP triode Q8 and the base electrode of the fourth PNP triode Q9 are connected and then connected to the emitter electrode of the fifth NPN triode Q5, the collector electrode of the third PNP triode Q8 is connected to the negative input terminal VN, and the collector electrode of the fourth PNP triode Q9 is connected to the positive input terminal VP;
a base electrode of the fifth NPN transistor Q5 is connected to a collector electrode of the first PNP transistor Q6, a collector electrode of the fifth NPN transistor Q5 is connected to the power supply VCC, and an emitter electrode of the fifth NPN transistor Q5 is connected to a base electrode of the third PNP transistor Q8, a base electrode of the fourth PNP transistor Q9, and a collector electrode of the fourth NPN transistor Q4, respectively;
a base electrode of the fourth NPN transistor Q4 is connected to a bias voltage VBIAS, an emitter electrode of the fourth NPN transistor Q4 is connected to a first end of the fourth resistor R4, and a second end of the fourth resistor R4 is grounded.
In a specific embodiment, the first terminal of the output stage 3 is connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, respectively.
In a specific embodiment, the third NPN transistor Q3 and the fourth NPN transistor Q4 are a set 1: 1 mirror current mirror.
In a specific embodiment, the emitter areas of the fifth NPN transistor Q5, the first NPN transistor Q1, and the second NPN transistor Q2 are equal.
In one specific embodiment, the first PNP transistor Q6 and the second PNP transistor Q7 are a set 1: 1 mirror current mirror.
In a specific embodiment, the third PNP transistor Q8 and the fourth PNP transistor Q9 are a set 1: 1 mirror current mirror.
In a specific embodiment, the input current of the operational amplifier
The calculation formula is as follows:
wherein the content of the first and second substances,
representing the input current of the differential input stage,
representing the base current of the second NPN transistor Q2
Representing the collector current of the third PNP transistor Q8,
indicating the unity of amplification of all the transistors.
Based on the above disclosure, the derivation process of the above formula (1) is specifically as follows:
the differential input stage 1 comprises two differential inputs, namely a first NPN transistor Q1 and a second NPN transistor Q2, such that the input current of the differential input stage 1 is equal to the input current of the first NPN transistor Q1
Namely, the base currents of the first NPN transistor Q1 and the second NPN transistor Q2 are respectively measured by
And
and (4) showing. The two load resistors, i.e. the first resistor R1 and the second resistor R2, respectively flow current
And
and (4) showing. The relationship between the base current and the collector current of the triode can be known
。
Then, when the forward input terminal VP = the reverse input terminal VN, the amplifier tail current flowing through the third NPN transistor Q3
；
Setting the third NPN transistor Q3 and the fourth NPN transistor Q4 to have the same M value and emitter area, and setting the dimensions of the third resistor R3 and the fourth resistor R4 to be completely the same, so that the third NPN transistor Q3 and the fourth NPN transistor Q4 form a set 1: 1 mirror current mirror. Therefore, the current flowing through the collector of the fourth NPN transistor Q4:
the fifth NPN transistor Q5, the first NPN transistor Q1, and the second NPN transistor Q2 are set to have an M value and an emitter area equal to each other, and thus a base current flowing through the fifth NPN transistor Q5
Emitter current of the fifth NPN transistor Q5
The relationship of (1) is:
. As can be seen from the figure 2 of the drawings,
wherein the content of the first and second substances,
representing the base current of the third PNP transistor Q8,
represents the aboveThe collector current of the third PNP transistor Q8.
Since the first PNP transistor Q6 and the second PNP transistor Q7 are current mirror relationships, the collector currents of the first PNP transistor Q6 and the second PNP transistor Q7 are equal, i.e., the first PNP transistor Q6 and the second PNP transistor Q7 are in a same current mirror relationship, i.e., the collector currents of the first PNP transistor Q6 and the second PNP transistor Q7 are equal
Thus is provided with
Since the third PNP transistor Q8 and the fourth PNP transistor Q9 are current mirror relationships, the collector currents of the third PNP transistor Q8 and the fourth PNP transistor Q9 are equal, i.e., the collector currents are equal
To do so
Wherein the content of the first and second substances,
representing the emitter current of the fourth PNP transistor Q9.
According to the formulas (2) to (7), the following can be calculated:
therefore, the calculation formula of the input current of the operational amplifier is:
wherein the content of the first and second substances,
representing the input current of the differential input stage,
represents the base current of the second NPN transistor Q2,
representing the collector current of the third PNP transistor Q8,
indicating the unity of amplification of all the transistors.
As a practical application of this embodiment, for example, when the amplification factor of the triode of the operational amplifier
When the value is 100, assuming that the tail current of the input stage of the operational amplifier, i.e. the amplifier tail current Ic3=2uA of the third NPN transistor Q3, when the input current cancellation circuit 2 is not added, the input current is: ip = In = 9.9 nA; when the input current cancellation circuit 2 is added, the input current is calculated by the formula (1): ip = In = = -100 pA; it can be seen from this example that, after the input current cancellation circuit 2 is added, the current at the input end drops by 2 orders of magnitude, and the input impedance of the operational amplifier is effectively increased.
Based on the above disclosure, in the present embodiment, the tail current of the third NPN transistor Q3 of the mirror amplifier flows through the first PNP transistor Q6 while the emitter current of the fourth NPN transistor Q4 is the same as the collector current of the fifth NPN transistor Q5, the collector current of the second PNP transistor Q7 is equal to the base current of the fifth NPN transistor Q5, the collector current of the second PNP transistor Q7 flows through the third PNP transistor Q8, and the fourth PNP transistor Q9 compensates the bases of the second NPN transistor Q2 and the first NPN transistor Q1 respectively so as to cancel the input currents of the positive and negative input terminals VP and VN of the operational amplifier. By the arrangement of the circuit structure, the base current of the NPN type triode is effectively compensated, namely the currents of the inputs VP and VN of the operational amplifier are offset, so that the input current of the operational amplifier is extremely low, and the high input impedance characteristic of the NPN type input operational amplifier is realized.
Finally, it should be noted that: the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A cancellation circuit for an input current of an operational amplifier, comprising: a differential input stage (1), an input current cancellation circuit (2) and an output stage (3);
the first end of the differential input stage (1) and the first end of the input current counteracting circuit (2) are connected and then connected to a positive input end and a negative input end, the second end of the differential input stage (1) and the second end of the input current counteracting circuit (2) are connected and then connected to a power supply, the third end of the differential input stage (1) and the third end of the input current counteracting circuit (2) are connected and then connected to a bias voltage, and the fourth end of the differential input stage (1) and the fourth end of the input current counteracting circuit (2) are connected and then grounded;
the fifth end of the differential input stage (1) is connected with the first end of the output stage (3), and the second end of the output stage (3) is connected with the voltage output end.
2. The operational amplifier input current cancellation circuit according to claim 1, wherein the differential input stage (1) comprises a first NPN transistor Q1, a second NPN transistor Q2, a first resistor R1, a second resistor R2, a third NPN transistor Q3, and a third resistor R3;
a base electrode of the first NPN type triode Q1 is connected to a positive input end VP, a collector electrode of the first NPN type triode Q1 is connected to a first end of the second resistor R2, an emitter electrode of the first NPN type triode Q1 is connected to a collector electrode of the third NPN type triode Q3, and a second end of the second resistor R2 is connected to a power supply VCC;
a base electrode of the second NPN triode Q2 is connected to a negative input terminal VN, a collector electrode of the second NPN triode Q2 is connected to a first end of the first resistor R1, an emitter electrode of the second NPN triode Q2 is connected to a collector electrode of the third NPN triode Q3, and a second end of the first resistor R1 is connected to a power supply VCC;
a base electrode of the third NPN transistor Q3 is connected to a bias voltage VBIAS, an emitter electrode of the third NPN transistor Q3 is connected to a first end of the third resistor R3, and a second end of the third resistor R3 is grounded.
3. The operational amplifier input current cancellation circuit according to claim 2, wherein the input current cancellation circuit (2) comprises a first PNP transistor Q6, a second PNP transistor Q7, a third PNP transistor Q8, a fourth PNP transistor Q9, a fourth NPN transistor Q4, a fifth NPN transistor Q5, and a fourth resistor R4;
an emitting electrode of the first PNP triode Q6 and an emitting electrode of the second PNP triode Q7 are both connected to a power supply, a base electrode of the first PNP triode Q6 and a base electrode of the second PNP triode Q7 are connected to a collector electrode of the first PNP triode Q6 and a base electrode of the fifth NPN triode Q5 respectively, and a collector electrode of the second PNP triode Q7 is connected to an emitting electrode of the third PNP triode Q8 and an emitting electrode of the fourth PNP triode Q9 respectively;
the base electrode of the third PNP triode Q8 and the base electrode of the fourth PNP triode Q9 are connected and then connected to the emitter electrode of the fifth NPN triode Q5, the collector electrode of the third PNP triode Q8 is connected to the negative input terminal VN, and the collector electrode of the fourth PNP triode Q9 is connected to the positive input terminal VP;
a base electrode of the fifth NPN transistor Q5 is connected to a collector electrode of the first PNP transistor Q6, a collector electrode of the fifth NPN transistor Q5 is connected to the power supply VCC, and an emitter electrode of the fifth NPN transistor Q5 is connected to a base electrode of the third PNP transistor Q8, a base electrode of the fourth PNP transistor Q9, and a collector electrode of the fourth NPN transistor Q4, respectively;
a base electrode of the fourth NPN transistor Q4 is connected to a bias voltage VBIAS, an emitter electrode of the fourth NPN transistor Q4 is connected to a first end of the fourth resistor R4, and a second end of the fourth resistor R4 is grounded.
4. The operational amplifier input current cancellation circuit according to claim 2, wherein the first terminal of the output stage (3) is connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, respectively.
5. The cancellation circuit for operational amplifier input current according to claim 3, wherein the third NPN transistor Q3 and the fourth NPN transistor Q4 are a set of 1: 1 mirror current mirror.
6. The operational amplifier input current cancellation circuit according to claim 5, wherein the emitter areas of the fifth NPN transistor Q5, the first NPN transistor Q1 and the second NPN transistor Q2 are equal.
7. The cancellation circuit for operational amplifier input current according to claim 6, wherein the first PNP transistor Q6 and the second PNP transistor Q7 are a set of 1: 1 mirror current mirror.
8. The cancellation circuit for operational amplifier input current according to claim 7, wherein the third PNP transistor Q8 and the fourth PNP transistor Q9 are a set of 1: 1 mirror current mirror.
9. The cancellation circuit for input current of operational amplifier according to claim 8, wherein the input current of the operational amplifier
The calculation formula is as follows:
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| CN117254682A (en) * | 2023-11-20 | 2023-12-19 | 成都芯翼科技有限公司 | Anti-interference voltage conversion circuit |
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