WO2020172827A1

WO2020172827A1 - Variable-gain amplifier

Info

Publication number: WO2020172827A1
Application number: PCT/CN2019/076369
Authority: WO
Inventors: 李天一
Original assignee: 华为技术有限公司
Priority date: 2019-02-27
Filing date: 2019-02-27
Publication date: 2020-09-03
Also published as: CN113424442B; CN113424442A

Abstract

A variable-gain amplifier (VGA): a first common-source transistor pair constitutes a common-source, common-gate structure respectively with a first common-gate transistor pair and a second common-gate transistor pair, a second common-source transistor pair constitutes a common-source, common-gate structure respectively with a third common-gate transistor pair and a fourth common-gate transistor pair, a first load resistance is coupled respectively with a drain electrode of one common-gate transistor in the first common-gate transistor pair and a drain electrode of one common-gate transistor in the third common-gate transistor pair, a second load resistance is coupled respectively with a drain electrode of the other common-gate transistor in the first common-gate transistor pair and a drain electrode of the other common-gate transistor in the third common-gate transistor pair, a first virtual resistance is coupled respectively with a second virtual resistance, drain electrodes of both common-gate transistors in the second common-gate transistor pair, and drain electrodes of both common-gate transistors in the fourth common-gate transistor pair, a shunt circuit is coupled respectively with source electrodes of both common-gate transistors in the first common-gate transistor pair and the first virtual resistance, and a reverse parallel-connected circuit is coupled respectively with source electrodes of both common-gate transistors in the third common-gate transistor pair, the first load resistance, and the second load resistance. The embodiments of the present application increases the performance of the VGA.

Description

A variable gain amplifier

Technical field

The embodiments of the present application relate to the technical field of electronic circuits, in particular to a variable gain amplifier.

Background technique

The variable gain amplifier (VGA) is an important module in the high-bandwidth optoelectronic chip, which undertakes most of the gain adjustment function of the radio frequency path. Maintaining high linearity in a large gain range is an important measure of VGA performance index. However, although the existing VGA can guarantee a larger gain range, the linearity of the VGA is poor, resulting in poor performance of the VGA.

Summary of the invention

The embodiment of the application discloses a variable gain amplifier for improving the performance of a VGA.

The first aspect discloses a VGA, including a first variable gain circuit, a second variable gain circuit, a shunt circuit, an inverse parallel circuit, a first load resistance, a second load resistance, a first dummy resistance and a first Two virtual resistors, the first variable gain circuit may include a first cascode pair, a first cascode pair and a second cascode pair, and the second variable gain circuit may include a second cascode pair, a third The cascode pair and the fourth cascode pair; the first cascode pair and the first cascode pair and the second cascode pair form a cascode structure, and the second cascode pair and the third The cascode transistor pair and the fourth cascode transistor pair form a cascode structure, and the first load resistance is coupled to the drain of one cascode transistor in the first cascode transistor pair and a cascode transistor in the third cascode transistor pair. The second load resistor is coupled to the drain of the other cascode in the first cascode pair and the drain of the other cascode in the third cascode pair. The first virtual resistor is coupled to the second The dummy resistance, the drains of the two cascodes in the second cascode pair and the drains of the two cascodes in the fourth cascode pair, and the shunt circuit respectively couples the two cascodes in the first cascode pair. The source electrode of the tube and the first virtual resistance, and the anti-parallel circuit respectively couples the source electrode, the first load resistance and the second load resistance of the two common gate tubes in the third cascode tube pair. When the VGA works in the first zone, the shunt circuit can keep the current flowing through the two load resistors constant; when the VGA works in the second zone, the anti-parallel circuit can ensure that the current flowing through the two load resistors remains constant. In the case of changing, the gain of the VGA is changed within the preset range. It can be seen that since the working area of the VGA is divided into two working areas, the linearity of the VGA can be improved while the gain range of the VGA is ensured, so that the performance of the VGA can be improved. In addition, since the current flowing through the load resistor remains unchanged in the entire working area of the VGA, the common-mode output voltage of the VGA remains unchanged in the entire working area of the VGA, thereby further improving the performance of the VGA.

As a possible implementation, the anti-parallel circuit may be a fifth cascode pair composed of two cascode transistors. The first load resistor is coupled to the drain of one cascode transistor in the fifth cascode pair. Two load resistors are coupled to the drain of the other cascode in the fifth cascode pair, the source of one cascode in the fifth cascode pair is coupled to the source of the other cascode in the third cascode pair , The source of the other cascode in the fifth cascode pair is coupled to the source of the cascode in the third cascode pair.

As a possible implementation manner, the shunt circuit may be a sixth cascode pair composed of two cascode transistors. The first dummy resistor is respectively coupled to the drains of the two cascode transistors in the sixth cascode pair. The source of one cascode in the six cascode pair is coupled to the source of one cascode in the first cascode pair, and the source of the other cascode in the sixth cascode pair is coupled to the first cascode. Center the source of the other common gate transistor.

As a possible implementation manner, the shunt circuit may include a first shunt resistor and a second shunt resistor, the first virtual resistor is coupled to one end of the first shunt resistor and one end of the second shunt resistor, and the other end of the first shunt resistor is coupled The source of one common gate in the first cascode pair, and the other end of the second shunt resistor is coupled to the source of the other common gate in the first cascode pair.

As a possible implementation manner, the first load resistance, the second load resistance, the first virtual resistance, and the second virtual resistance are respectively used to couple the power supply.

As a possible implementation manner, the first variable gain circuit may further include a first current source and a second current source, and the second variable gain circuit may further include a third current source and a fourth current source, and the first current source The source and ground of one common source transistor in the first common source transistor pair are respectively coupled, the second current source is respectively coupled to the source and ground end of the other common source transistor in the first common source transistor pair, and the third current source is respectively The source electrode and the ground terminal of one common source tube in the second common source tube pair are coupled, and the fourth current source is respectively coupled to the source electrode and the ground terminal of the other common source tube in the second common source tube pair.

As a possible implementation manner, the first variable gain circuit may further include a first capacitor, and the second variable gain circuit may further include a second capacitor, where:

Two ends of the first capacitor are respectively coupled to the sources of the two common source transistors in the first common source transistor pair, and both ends of the second capacitor are respectively coupled to the sources of the two common source transistors in the second common source transistor pair.

As a possible implementation manner, the first variable gain circuit may further include a first degeneration resistor, and the second variable gain circuit may further include a second degeneration resistor, and both ends of the first degeneration resistor are respectively coupled to the first common source transistor. For the sources of the two common source transistors, the two ends of the second degeneration resistor are respectively coupled to the sources of the two common source transistors in the second common source transistor pair. The zero point formed by the capacitor and the emitter degeneration resistance can offset the main pole formed by the load resistance and the output end load capacitance, thereby expanding the bandwidth.

A second aspect discloses a VGA including a first variable gain circuit, a second variable gain circuit, a shunt circuit, an inverse parallel circuit, a first load resistance, a second load resistance, a first virtual resistance, and a second virtual resistance , The first variable gain circuit may include a first common tube pair, a first common tube pair, and a second common tube pair, and the second variable gain circuit may include a second common tube pair and a third common tube pair. Pair and the fourth common base tube pair, the first common base tube pair and the first common base tube pair and the second common base tube pair form a common base tube structure, the second common base tube pair and the third common base tube The pair and the fourth common base tube pair form a cascode structure. The first load resistor is coupled to the collector of one common base tube in the first common base tube pair and the collector of one common base tube in the third common base tube pair. , The second load resistor is respectively coupled to the collector of the other common base transistor in the first common base transistor pair and the collector of the other common base transistor in the third common base transistor pair, and the first virtual resistor is coupled to the second virtual resistor, The collectors of the two common base tubes in the second common base tube pair and the collectors of the two common base tubes in the fourth common base tube pair. The shunt circuit respectively couples the emission of the two common base tubes in the first common base tube pair. And the first virtual resistor, and the anti-parallel circuit respectively couples the emitter, the first load resistance and the second load resistance of the two common base transistors in the third common base transistor pair. When the VGA works in the first zone, the shunt circuit can keep the current flowing through the two load resistors constant; when the VGA works in the second zone, the anti-parallel circuit can ensure that the current flowing through the two load resistors remains constant. In the case of changing, the gain of the VGA is changed within the preset range. It can be seen that since the working area of the VGA is divided into two working areas, the linearity of the VGA can be improved while the gain range of the VGA is ensured, so that the performance of the VGA can be improved. In addition, since the current flowing through the load resistor remains unchanged in the entire working area of the VGA, the common-mode output voltage of the VGA remains unchanged in the entire working area of the VGA, thereby further improving the performance of the VGA.

As a possible implementation, the anti-parallel circuit may be a fifth common base transistor pair composed of two common base transistors. The first load resistor is coupled to the collector of one common base transistor in the fifth common base transistor pair. Two load resistors are coupled to the collector of the other common base tube in the fifth common base tube pair, and the emitter of one common base tube in the fifth common base tube pair is coupled to the emitter of the other common base tube in the third common base tube pair. , The emitter of the other common base tube in the fifth common base tube pair is coupled to the emitter of one common base tube in the third common base tube pair.

As a possible implementation, the shunt circuit may be a sixth common base transistor pair composed of two common base transistors. The first virtual resistor is respectively coupled to the collectors of the two common base transistors in the sixth common base transistor pair. The emitter of one common base tube in the six common base tube pair is coupled to the emitter of one common base tube in the first common base tube pair, and the emitter of the other common base tube in the sixth common base tube pair is coupled to the first common base tube. Center the emitter of the other common base tube.

As a possible implementation manner, the shunt circuit may include a first shunt resistor and a second shunt resistor, the first virtual resistor is coupled to one end of the first shunt resistor and one end of the second shunt resistor, and the other end of the first shunt resistor is coupled The emitter of one common base tube in the first common base tube pair, and the other end of the second shunt resistor is coupled to the emitter of the other common base tube in the first common base tube pair.

As a possible implementation manner, the first variable gain circuit may further include a first current source and a second current source, and the second variable gain circuit may further include a third current source and a fourth current source, and the first current source The emitter and the ground of one of the first common emitter are respectively coupled, the second current source is respectively coupled to the emitter and the ground of the other of the first common emitter, and the third current source is respectively The emitter and the ground terminal of one common emitter in the second common emitter pair are coupled, and the fourth current source is respectively coupled with the emitter and the ground terminal of the other common emitter in the second common emitter pair.

As a possible implementation manner, the first variable gain circuit may further include a first capacitor, and the second variable gain circuit may further include a second capacitor. Both ends of the first capacitor are respectively coupled to the two pairs of the first common emitter. The emitters of a common emission tube, and the two ends of the second capacitor are respectively coupled to the emitters of the two common emission tubes in the second common emission tube pair.

As a possible implementation manner, the first variable gain circuit may further include a first degeneration resistor, and the second variable gain circuit may further include a second degeneration resistor, and both ends of the first degeneration resistor are respectively coupled to the first common emitter. The emitters of the two common emitters are centered, and the two ends of the second degeneration resistor are respectively coupled to the emitters of the two common emitters of the second common emitter.

Description of the drawings

FIG. 1 is a schematic structural diagram of a VGA disclosed in an embodiment of the present application;

2 is a schematic diagram of gain, voltage and current of a VGA disclosed in an embodiment of the present application;

FIG. 3 is a schematic structural diagram of another VGA disclosed in an embodiment of the present application;

FIG. 4 is a schematic diagram of gain, voltage and current of another VGA disclosed in an embodiment of the present application;

FIG. 5 is a schematic diagram of THD obtained based on actual circuit parameters disclosed in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of another VGA disclosed in an embodiment of the present application;

FIG. 7 is a schematic diagram of gain, voltage, and current of another VGA disclosed in an embodiment of the present application;

FIG. 8 is a schematic diagram of another THD obtained based on actual circuit parameters disclosed in an embodiment of the present application;

FIG. 9 is a schematic structural diagram of another VGA disclosed in an embodiment of the present application;

FIG. 10 is a schematic structural diagram of another VGA disclosed in an embodiment of the present application;

FIG. 11 is a schematic structural diagram of another VGA disclosed in an embodiment of the present application.

detailed description

The embodiment of the application discloses a variable gain amplifier for improving the performance of a VGA. The detailed description is given below.

In order to better understand a variable gain amplifier disclosed in the embodiment of the present application, the following describes the application scenario of the embodiment of the present invention. Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a VGA disclosed in an embodiment of the present application. As shown in Figure 1, the VGA includes load resistors R1-R2, virtual resistors R3-R4, degeneration resistors R5, current sources B1-B2, first common base transistor pair, second common base transistor pair, common emitter pair and Capacitance C, where:

The common emitter pair and the first common base tube pair and the second common base tube pair form a common emitter common base structure. R1 is coupled to the power supply and the collector of a common base tube in the first common base tube pair, and R2 is coupled to the power supply respectively. With the collector of the other common base tube in the first common base tube pair, one end of R3 is coupled to one end of R4 and the collector of the two common base tubes in the second common base tube pair, the other end of R3 and the other end of R4 One end is used to couple the power supply, R5 respectively couples the emitters of the two common emitters in the common emitter pair, C and R5 are connected in parallel, and B1 respectively couples the emitter and ground of one of the common emitters in the common emitter pair, B2 Coupling the emitter and ground of the other common emitter in the common emitter pair respectively, the base electrode of one common emitter in the common emitter pair is the forward input end of the VGA, and the common emitter pair in the other common emitter. The base is the reverse input end of the VGA, one end of R1 is the reverse output end of the VGA, and one end of R2 is the forward output end of the VGA. The bases of the two common base transistors in the first common base tube pair are respectively The bias voltage V _{cp is} coupled, and the bases of the two common base transistors in the second common base transistor pair are respectively coupled to the bias voltage V _cn .

In the VGA shown in FIG. 1, the branch where the first common base tube pair is located is the main branch, and the branch where the second common base tube pair is located is the secondary branch. Please refer to FIG. 2. FIG. 2 is a schematic diagram of the gain, voltage, and current of a VGA disclosed in an embodiment of the present application. Among them, FIG. 2 is a schematic diagram of the gain, voltage and current of the VGA shown in FIG. 1. As shown in FIG. 2, the bias voltage V _cp of the first common base transistor to the base has an opposite trend to the bias voltage V _cn of the second common base transistor to the base. When the control voltage V _{GC is the} smallest, V _{cp is} at the minimum and V _{cn is} at the maximum, the main branch is completely closed, the secondary branch is fully turned on, and the bias current I _bias flows into the secondary branch completely, the main branch current and the load The current is zero, the gain A _V is 0, and the common-mode output voltage is the power supply voltage V _DD . As the control voltage V _GC continues to increase, V _cp rises and V _cn falls, the main branch is gradually turned on, the auxiliary branch is gradually closed, and the load current I _load and the gain _AV gradually rise. When V _cp rises to the maximum value and V _cn falls to the minimum value, the main branch is completely opened, the auxiliary branch is completely closed, the bias current I _bias completely flows into the main branch, the load current I _load reaches the maximum, and the gain A _V When the maximum gain A _{V_max is reached} , the common-mode output voltage is V _DD -R _L I _bias .

Please refer to FIG. 3, which is a schematic structural diagram of another VGA disclosed in an embodiment of the present application. As shown in Figure 3, the VGA includes load resistors R1-R2, virtual resistors R3-R4, degeneration resistors R5-R6, current sources B1-B4, a first common emitter pair, a second common emitter pair, and a first common emitter pair. Base tube pair, second common base tube pair, third common base tube pair, fourth common base tube pair and capacitors C1-C2, where:

The first common injection tube pair constitutes a common injection common base structure with the first common base tube pair and the second common base tube pair, and the second common injection tube pair constitutes a third common base tube pair and the fourth common base tube pair respectively. The cascode structure. One end of R1 is coupled to the power supply, the collector of a common base tube in the first common base tube pair, and the collector of a common base tube in the third common base tube pair. One end of R2 is coupled to the power supply, The collector of the other common base tube in the first common base tube pair and the collector of the other common base tube in the third common base tube pair. One end of R3 is coupled to one end of R4 and two in the second common base tube pair. The collector of the common base tube and the collector of the two common base tubes in the fourth common base tube pair, the other end of R3 and the other end of R4 are respectively coupled to the power supply, and R5 is respectively coupled to the two common emitters in the first common emitter pair The emitter of the tube, C1 and R5 are connected in parallel, B1 is respectively coupled to the emitter and ground of one of the first common emitter, and B2 is respectively coupled to the emitter of the other of the first common emitter And ground, R6 is coupled to the emitter of the two common emitters of the second common emitter, C2 and R6 are connected in parallel, and B3 is respectively coupled to the emitter and ground of one of the second common emitter, B4 is respectively coupled to the emitter and ground of the other common emission tube in the second common emission tube pair, the base of one common emission tube in the first common emission tube pair and the base of one common emission tube in the second common emission tube pair. It is the forward input end of the VGA, the base of the other common emission tube in the first common emission tube pair and the base of the other common emission tube in the second common emission tube pair are the reverse input end of the VGA, R1 One end is the reverse output end of the VGA, one end of R2 is the forward output end of the VGA, the bases of the two common base tubes in the first common base tube pair and the two common base tubes in the fourth common base tube pair The bases of are respectively coupled to the bias voltage V _cp , the bases of the two common base transistors in the second common base transistor pair and the bases of the two common base transistors in the third common base transistor pair are respectively coupled to the bias voltage V _cn .

In the VGA shown in Figure 3, the first common base tube pair, the second common base tube pair, and the first common emitter pair are located in high-gain modules. The third common base tube pair, the fourth common base tube pair and the The module where the two common emitters are located is a low gain module. In the high gain module, the branch where the first common base tube pair is located is the main branch, and the branch where the second common base tube pair is located is the secondary branch. In the low gain module, the branch where the third common base tube pair is located is the main branch, and the branch where the fourth common base tube pair is located is the secondary branch. Please refer to FIG. 4, which is a schematic diagram of gain, voltage, and current of another VGA disclosed in an embodiment of the present application. Among them, FIG. 4 is a schematic diagram of the gain, voltage and current of the VGA shown in FIG. 3. As shown in Figure 4, the bias voltage V _cp of the base of the first common base transistor pair and the fourth common base transistor pair is compared with the base bias voltage V _cp of the second common base transistor pair and the third common base transistor pair. The change trend of _cn is opposite. When the control voltage V _{GC is} minimum, V _{cp is} at the minimum and V _{cn is} at the maximum. The bias circuits of the high gain module all flow into the auxiliary branch, the main branch of the high gain module is completely closed, and the gain of the high gain module is 0 , The bias current of the low gain module all flows into the main branch, the current of the main branch of the low gain module reaches the maximum value I _bL , and the gain of the low gain module reaches the maximum value A _VL , and the total gain is A _VL , the load current I _load = I _bL , and the common-mode output voltage is V _DD -R _L I _bL . As the control voltage V _GC continues to increase, V _cp rises while V _cn falls. When V _{cp is} at the maximum and V _{cn is} at the minimum, all the bias currents of the high-gain module flow into the main branch. The branch current reaches the maximum value I _bH , the gain of the high gain module reaches the maximum value A _VH , the bias current of the low gain module all flows into the secondary branch, the current of the main branch of the low gain module is 0, and the gain of the low gain module If it is 0, the total gain is A _VH , the load current I _load =I _bH , and the common-mode output voltage is V _DD -R _L I _bH . It can be seen that the gain of the VGA shown in Figure 3 changes between A _VL and A _VH , the load current changes between I _bL and I _bH , and the common-mode output voltage is between V _DD -R _L I _bH and V _DD -R _L Change between I _bL .

The main indicator to measure the linearity of a VGA is total harmonic distortion (THD). THD is the square root of the ratio of the sum of the harmonic powers of the VGA output signal to the main power, which can be expressed as follows:

Among them, P _ω is the fundamental wave power, P _2ω is the second harmonic power, P _3ω is the third harmonic power, HD ₂ is the second harmonic distortion, and HD ₃ is the third harmonic distortion. For differential pairs, the second harmonic can be ignored, and THD is mainly affected by the third harmonic.

In the VGA shown in Figure 1

Among them, V _ω is the fundamental wave amplitude, V _3ω is the third harmonic amplitude, g _mH is the input tube transconductance, V _id is the amplitude of the input differential signal, V _T is the thermal voltage, and R _EH is the degeneration resistance. In order to consider the THD of the VGA under the same output amplitude and different gain A _V , assuming that the amplitude _Vod of the VGA output differential signal is constant, then:

Then the total harmonic distortion THD ₁ of the VGA shown in Figure ₁ is:

It can be seen that under other conditions that remain unchanged, THD ₁ increases sharply with the decrease of _AV , and the maximum value appears at the lowest gain. Therefore, when the maximum gain is unchanged, the increase in the gain range will reduce the value of the minimum gain, thereby greatly increasing the maximum THD in the entire gain range.

The gain of the VGA shown in Figure 3 can be expressed as follows:

A _V ＝A _VH ·α+A _VL ·(1-α)

Among them, A _VH is the gain of the high-gain module, A _VL is the gain of the low-gain module, α=(A _V -A _VL )/(A _VH -A _VL ) is the gain distribution ratio, as the control voltage of VGA rises , Α changes from 0 to 1. Based on the same derivation process described above, the fundamental wave amplitude V _ωH and the third harmonic amplitude V _{3ωH of the} high gain module can be expressed as follows:

Among them, g _mH is the input tube transconductance of the high gain module, and R _EH is the degeneration resistance of the high gain module. The amplitude of the fundamental wave and the third harmonic amplitude _V ωL module _V 3ωL low gain can be expressed as follows:

Among them, g _mL is the input tube transconductance of the low gain module, and R _EL is the degeneration resistance of the low gain module. VGA shown in Fig. 3 Total fundamental amplitude _{_{_{V ω = V ωH + V ωL}}} = α · A VH · V id + (1-α) · A VL · V id = A V · V id = V od, assuming :

Then the third harmonic amplitude V _3ω of the VGA shown in Figure 3 can be expressed as follows:

The total harmonic distortion THD ₂ of the VGA shown in Figure 3 is:

In order to find the maximum value of THD ₂ , we can take the derivative of A _V and let:

It can be seen that the maximum value of THD ₂ is not at the boundary of the gain control range, but first increases and then decreases as the gain decreases, and the maximum value appears somewhere in the middle. Substituting the _AV result of the above formula into the THD ₂ expression, the maximum value of THD ₂ can be obtained:

It can be seen that the smaller the k _H -k _{L is, the} smaller the THD _{2 is} . Theoretically, when k _H =k _L , the third harmonic cancels out, but in actual design, it is difficult to achieve due to the constraints of current and gain, but it is still far away. It is much better than the VGA shown in Figure 1. At the same time, THD _{2 is} inversely proportional to the gain range A _VH -A _VL . The larger the gain range, the worse the linearity in the entire gain range.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of THD obtained based on actual circuit parameters disclosed in an embodiment of the present application. As shown in Figure 5, the THD ₁ of the VGA shown in Figure 1 increases as the gain decreases, and the maximum value appears at the lowest gain; the THD ₂ of the VGA shown in Figure 3 first increases and then decreases as the gain decreases. Since the newly added low-gain module of the VGA shown in Figure 3 has a sharing effect on the original high-gain module, the THD ₂ increase speed of the VGA shown in Figure 3 is obviously slower, and the maximum gain is reached at the low position in the middle of the gain range. The value is also much smaller than the maximum value of the VGA shown in FIG. 1. It can be seen that the linearity of the VGA shown in FIG. 3 is higher than that of the VGA shown in FIG. 1 as a whole. However, although the linearity of the VGA shown in FIG. 3 is higher than the linearity of the VGA shown in FIG. 1 as a whole, the maximum value of THD is still large, so that the linearity of the VGA is poor, resulting in poor performance of the VGA. Furthermore, since the common-mode output voltage varies between V _DD -R _L I _bH and V _DD -R _L I _bL , the performance of the VGA is further deteriorated, and the next stage circuit cannot be guaranteed to work in a suitable area. Increased the difficulty of designing the subsequent RF module.

Please refer to FIG. 6, which is a schematic structural diagram of another VGA disclosed in an embodiment of the present invention. As shown in FIG. 6, the VGA may include a first variable gain circuit, a second variable gain circuit, a shunt circuit, an inverse parallel circuit, a first load resistor R1, a second load resistor R2, a first virtual resistor R3, and The second dummy resistor R4, the first variable gain circuit may include a first cascode pair, a first cascode pair, a second cascode pair, a degenerate resistor R5, a capacitor C1 and current sources B1-B2, and a second The variable gain circuit can include a second cascode pair, a third cascode pair, a fourth cascode pair, a degradation resistor R6, a capacitor C2, and a current source B3-B4. The anti-parallel circuit consists of two cascode pairs. The fifth cascode tube pair is composed of two cascode tubes, and the shunt circuit is a sixth cascode tube pair composed of two cascode tubes, where:

The first cascode pair constitutes a cascode structure with the first cascode pair and the second cascode pair respectively, and the second cascode pair constitutes a cascode structure with the third cascode pair and the fourth cascode pair, respectively In a cascode structure, one end of the first load resistor R1 is respectively coupled to the drain of a cascode in the first cascode pair, the drain of a cascode in the third cascode pair, and the fifth cascode. Align the drain of one cascode transistor, and one end of the second load resistor R2 is respectively coupled to the drain of the other cascode in the first cascode pair and the drain of the other cascode in the third cascode pair. And the drain of the other cascode in the fifth cascode pair, one end of the first dummy resistor R3 is respectively coupled to one end of the second dummy resistor R4, the drains of the two cascodes in the second cascode pair, The drains of the two cascodes in the fourth cascode pair and the drains of the two cascodes in the sixth cascode pair. The source of one cascode in the fifth cascode pair is coupled to the third cascode. The source of the other cascode in the cascode pair, the source of the other cascode in the fifth cascode pair is coupled to the source of one cascode in the third cascode pair, the sixth cascode pair The source of one cascode in the first cascode pair is coupled to the source of one cascode in the first cascode pair, and the source of the other cascode in the sixth cascode pair is coupled to the other cascode pair in the first cascode pair. The source of the gate tube, the other end of the first load resistor R1, the other end of the second load resistor R2, the other end of the first virtual resistor R3, and the other end of the second virtual resistor R4 are used to couple the power supply, the first current The source B1 is respectively coupled to the source and the ground terminal of one common source tube in the first common source tube pair, and the second current source B2 is respectively coupled to the source and ground terminal of the other common source tube in the first common source tube pair. The current source B3 is respectively coupled to the source and the ground terminal of one common source tube in the second common source tube pair, and the fourth current source B4 is respectively coupled to the source and ground terminal of the other common source tube in the second common source tube pair. Both ends of a capacitor C1 are respectively coupled to the sources of the two common source transistors in the first common source transistor pair, and both ends of the second capacitor C2 are respectively coupled to the sources of the two common source transistors in the second common source transistor pair. A degeneration resistor R5 is connected in parallel with the first capacitor C1, a second degeneration resistor R6 is connected in parallel with the second capacitor C2, the gate of one common source transistor in the first common source pair and one common source transistor in the second common source pair The gate of the VGA is the forward input end of the VGA, the gate of the other common source in the first common source pair and the gate of the other common source in the second common source pair are the reverse input end of the VGA. One end of a load resistor R1 is the reverse output end of the VGA, and one end of the second load resistor R2 is the forward output end of the VGA. The gates of the two common gate transistors and the fourth common gate in the first cascode pair are The gates of the two cascode tubes in the pair of cascode tubes are respectively coupled to the bias voltage V _cpH , the gates of the two cascode tubes in the second cascode tube pair are respectively coupled to the bias voltage V _cnH , and the third cascode tube is _centered The gates of the two cascode transistors are respectively coupled to the bias voltage V _cpH , the gates of the two cascode transistors in the fifth cascode pair are respectively coupled to the bias voltage V _cnL , and the sixth cascode transistor pair is in the two _cascodes The gates of the tubes are respectively coupled with a bias voltage V _c .

In the VGA shown in Figure 6, the module where the first variable gain circuit and the shunt circuit are located is a high-gain module, the branch where the first common-gate tube pair is located is the main branch of the high-gain module, and the second common-gate tube pair is located The branch is the secondary branch of the high-gain module, and the shunt circuit is used to shunt the above-mentioned main branch to ensure that the DC current flowing through the load resistance R1-R2 is less than the value of the bias current source B1-B2. The module where the second variable gain circuit and the inverse parallel circuit are located is a low gain module, the branch where the third cascode tube pair is located is the main branch of the low gain module, and the branch where the fourth cascode tube pair is located is the branch of the low gain module. Vice branch road. The gates of the two cascode transistors in the sixth cascode tube pair are coupled to each other and the bias voltage V _c can be set as required, but it must be ensured that the shunt circuit is always in working state during the VGA operation, that is, the sixth cascode tube The two common gate tubes in the center are always on. The resistors R1 and R2 are load resistors, the resistors R3 and R4 are dummy resistors of the resistors R1 and R2, and the values of R1-R4 are the same. Degradation resistors R5-R6 can increase bandwidth at the expense of amplifier gain through negative feedback, and at the same time increase linearity at the expense of effective transconductance of the input tube. The zero point formed by the parallel connection of the capacitor C1 and the resistor R5 and the zero point formed by the parallel connection of the capacitor C2 and the resistor R6 can be used to offset the main pole formed by the load resistance R1-R2 and the output load capacitance, thereby expanding the amplifier bandwidth. The value of B1-B2 is the same, the value of B3-B4 is the same, and the value of B1 is greater than the value of B3.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of gain, voltage, and current of another VGA disclosed in an embodiment of the present application. Among them, FIG. 7 is a schematic diagram of the gain, voltage and current of the VGA shown in FIG. 6. As shown in FIG. 7, the working area of the VGA includes a first area and a second area. In the first region, as the VGA control voltage V decreases in _{the GC,} the first common bias voltage V _CPH and the gate of the fourth cascode tube of the tube gradually decreases, the second common gate bias voltage V of the tube The bias voltage V _{cpL of the} _cnH and the third cascode pair gradually increases, the first cascode pair of the main branch of the high gain module and the fourth cascode pair of the secondary branch of the low gain module are gradually closed, and the high gain module The second cascode pair of the secondary branch and the third cascode pair of the main branch of the low gain module are gradually turned on. In the first region, the bias voltage V _cnL of the fifth cascode pair of the anti-parallel circuit is always at the lowest value. Therefore, the fifth cascode pair of the anti-parallel circuit is always turned off without affecting the gain control. The total gain of the VGA changes from the highest value A _{VH of} the high gain module to the maximum gain A _{VL of the} low gain module. In the first region, the total load current I _load is the sum of the current I _H flowing to the first cascode pair and the current I _L of the third cascode pair, as long as I _H =λI _bL , I _L =(1 -λ)I _bL , I _load =I _H +I _L =I _bL , it can be seen that in the first region, the total load current I _load remains unchanged, and the common-mode output voltage (that is, the difference between the power supply voltage and the voltage on the load resistance Value) also remains unchanged. At the junction of the first region and the second region, V _cpH drops to the minimum, V _cnH and V _cpL increase to the maximum, the first and fourth cascode pairs are in the off state, and the second cascode The tube pair and the third common-gate tube pair are in a conducting state. In the second region, the values of V _cpH , V _cnH and V _cpL remain unchanged. As the control voltage V _GC further decreases, the bias voltage V _cnL of the fifth cascode pair of the anti-parallel circuit gradually increases. . Since the fifth cascode pair of the anti-parallel circuit is in anti-parallel connection with the third cascode pair, the offsetting effect of the reverse current will continue to reduce the gain of the VGA, and finally, the total gain of the VGA will decrease from A _VL to A _{V_min} , in the second region, the total load current I _load flowing through the load resistance remains unchanged, and the common-mode output voltage (that is, the difference between the power supply voltage and the voltage on the load resistance) also remains unchanged. Therefore, the common-mode output voltage remains unchanged during the entire working process of the VGA. I _bH is the value of the bias current sources B1 and B2, and I _bL is the value of the bias current sources B3 and B4.

Please refer to FIG. 8, which is another schematic diagram of THD obtained based on actual circuit parameters disclosed in an embodiment of the present application. As shown in FIG. 8, the principle of the first area of the VGA shown in FIG. 6 is the same as that of the VGA shown in FIG. 3. Therefore, the THD of the first area and the second area are the same as the THD of the VGA shown in FIG. the same. However, the first area or the second area of the VGA shown in FIG. 6 is only a part of the total gain range, which is much smaller than the entire gain range of the VGA shown in FIG. 3, so the THD is relatively small. It can be seen that within the same bandwidth range, the VGA shown in Figure 6 has the highest linearity.

Please refer to FIG. 9, which is a schematic structural diagram of another VGA disclosed in an embodiment of the present invention. As shown in FIG. 9, the VGA may include a first variable gain circuit, a second variable gain circuit, a shunt circuit, an inverse parallel circuit, a first load resistor R1, a second load resistor R2, a first virtual resistor R3, and The second dummy resistor R4, the first variable gain circuit may include a first cascode pair, a first cascode pair, a second cascode pair, a degenerate resistor R5, a capacitor C1 and current sources B1-B2, and a second The variable gain circuit can include a second cascode pair, a third cascode pair, a fourth cascode pair, a degradation resistor R6, a capacitor C2, and a current source B3-B4. The anti-parallel circuit consists of two cascode pairs. The fifth common-gate tube pair formed by tubes, the shunt circuit includes a first shunt resistor R7 and a second shunt resistor R8, where:

The first cascode pair constitutes a cascode structure with the first cascode pair and the second cascode pair respectively, and the second cascode pair constitutes a cascode structure with the third cascode pair and the fourth cascode pair, respectively In a cascode structure, one end of the first load resistor R1 is respectively coupled to the drain of a cascode in the first cascode pair, the drain of a cascode in the third cascode pair, and the fifth cascode. Align the drain of one cascode transistor, and one end of the second load resistor R2 is respectively coupled to the drain of the other cascode in the first cascode pair and the drain of the other cascode in the third cascode pair. And the drain of the other cascode in the fifth cascode pair, one end of the first dummy resistor R3 is respectively coupled to one end of the second dummy resistor R4, the drains of the two cascodes in the second cascode pair, The drain of the two cascode transistors in the fourth cascode pair, one end of the first shunt resistor R7 and one end of the second shunt resistor R8, the source of one cascode transistor in the fifth cascode pair is coupled to the third common The source of the other cascode in the cascode pair, the source of the other cascode in the fifth cascode pair is coupled to the source of the cascode in the third cascode pair, the first shunt resistor R7 The other end is coupled to the source of one cascode in the first cascode pair, the other end of the second shunt resistor R8 is coupled to the source of the other cascode in the first cascode pair, and the other end of the first load resistor R1 One end, the other end of the second load resistor R2, the other end of the first virtual resistor R3, and the other end of the second virtual resistor R3 are respectively used for coupling power, and the first current source B1 is respectively coupled to one of the first common source transistor pair. The source and ground terminals of the source tube, the second current source B2 is respectively coupled to the source and ground terminal of the other common source tube in the first common source tube pair, and the third current source B3 is respectively coupled to one of the second common source tube pair The source and ground terminals of the common source tube, the fourth current source B4 is respectively coupled to the source and ground terminal of the other common source tube in the second common source tube pair, and both ends of the first capacitor C1 are respectively coupled to the first common source tube Center the sources of the two common source transistors, the two ends of the second capacitor C2 are respectively coupled to the sources of the two common source transistors in the second common source transistor pair, the first degeneration resistor R5 is connected in parallel with the first capacitor C1, Two degeneration resistors R6 are connected in parallel with the second capacitor C2. The gate of one common source transistor in the first common source pair and the gate of one common source transistor in the second common source pair are the positive input terminals of the VGA. The gate of the other common source transistor in the common source pair and the gate of the other common source transistor in the second common source pair are the reverse input end of the VGA, and one end of the first load resistor R1 is the reverse output of the VGA One end of the second load resistor R2 is the positive output end of the VGA. The gates of the two cascodes in the first cascode pair and the gates of the two cascodes in the fourth cascode pair are respectively _{Couple the} bias voltage V _cpH , the gates of the two cascode tubes in the second cascode pair are coupled to the bias voltage V _cnH , and the gates of the two cascode tubes in the third cascode pair are respectively coupled to the bias voltage V _cpH , the gates of the two cascode transistors in the fifth cascode pair are respectively coupled to the bias voltage V _cnL .

Among them, in Figure 9 compared with Figure 6, the other parts of the two VGAs are not used, but the internal structure of the shunt circuit is different. The working principle shown in FIG. 9 is the same as the working principle shown in FIG. 6, and the detailed description can refer to the description of the working principle corresponding to FIG. 6, which will not be repeated here.

Please refer to FIG. 10, which is a schematic structural diagram of another VGA disclosed in an embodiment of the present invention. As shown in FIG. 10, the VGA may include a first variable gain circuit, a second variable gain circuit, a shunt circuit, an inverse parallel circuit, a first load resistor R1, a second load resistor R2, a first virtual resistor R3, and The second virtual resistor R4, the first variable gain circuit may include a first common emitter pair, a first common transistor pair, a second common transistor pair, a degenerate resistor R5, a capacitor C1 and current sources B1-B2, and the second The variable gain circuit can include a second common emitter pair, a third common base transistor pair, a fourth common base transistor pair, a degradation resistor R6, a capacitor C2, and a current source B3-B4. The anti-parallel circuit consists of two common base transistors. The fifth common base tube pair composed of tubes, and the shunt circuit is the sixth common base tube pair composed of two common base tubes, where:

The first common injection tube pair constitutes a common injection common base structure with the first common base tube pair and the second common base tube pair, and the second common injection tube pair constitutes a third common base tube pair and the fourth common base tube pair respectively. The cascode structure, one end of the first load resistor R1 is respectively coupled to the collector of one common base tube in the first common base tube pair, the collector of one common base tube in the third common base tube pair, and the fifth common base tube For the collector of one common base tube, one end of the second load resistor R2 is coupled to the collector of the other common base tube in the first common base tube pair, and the collector of the other common base tube in the third common base tube pair. And the collector of the other common base tube in the fifth common base tube pair, one end of the first virtual resistor R3 is coupled to one end of the second virtual resistor R4, the collectors of the two common base tubes in the second common base tube pair, The collectors of two common base tubes in the fourth common base tube pair and the collectors of two common base tubes in the sixth common base tube pair. The emitter of one common base tube in the fifth common base tube pair is coupled to the third common base tube pair. The emitter of the other common base tube in the base tube pair, the emitter of the other common base tube in the fifth common base tube pair is coupled to the emitter of one common base tube in the third common base tube pair, the sixth common base tube pair The emitter of one common base tube is coupled to the emitter of one common base tube in the first common base tube pair, and the emitter of the other common base tube in the sixth common base tube pair is coupled to the other common base tube pair. The emitter of the base tube, the other end of the first load resistor R1, the other end of the second load resistor R2, the other end of the first virtual resistor R3, and the other end of the second virtual resistor R3 are used to couple the power supply, the first current The source B1 is respectively coupled to the emitter and the ground of one of the first common emitter, and the second current source B2 is respectively coupled to the emitter and the ground of the other of the first common emitter. The third The current source B3 is respectively coupled to the emitter and the ground terminal of one common emitter in the second common emitter pair, and the fourth current source B4 is respectively coupled to the emitter and the ground terminal of the other common emitter in the second common emitter pair. Both ends of a capacitor C1 are respectively coupled to the emitters of the two common emission tubes in the first common emission tube pair, and both ends of the second capacitor C2 are respectively coupled to the emitters of the two common emission tubes in the second common emission tube pair. A degenerate resistor R5 is connected in parallel with the first capacitor C1, and a second degenerate resistor R6 is connected in parallel with the second capacitor C2. The base of one common emission tube in the first common emission tube pair and the second common emission tube pair are common emission. The base of the tube is the forward input terminal of the VGA, the grid of the other common emitter in the first common emitter pair and the base of the other common emitter in the second common emitter pair are the reverse input terminal of the VGA , One end of the first load resistor R1 is the reverse output end of the VGA, one end of the second load resistor R2 is the forward output end of the VGA, the base and the first common base transistor of the first common base transistor pair The bases of the two common base transistors in the quadruple base transistor pair are respectively coupled to the bias voltage V _cpH , the bases of the two common base transistors in the second common base transistor pair are respectively coupled to the bias voltage V _cnH , and the third common base transistor is The bases of the two common base transistors in the pair are respectively coupled to the bias voltage V _cpH , the bases of the two common base transistors in the fifth common base transistor pair are respectively coupled to the bias voltage V _cnL , and the sixth common base transistor pair is two The base of the common base tube is coupled to the bias voltage V _c .

Wherein, FIG. 10 is compared with FIG. 6, except that the N-type metal oxide semiconductor (MOS) tube in the VGA is replaced with an npn-type triode. The working principle shown in FIG. 10 is the same as the working principle shown in FIG. 6, and the detailed description can refer to the description of the working principle corresponding to FIG. 6, which will not be repeated here.

Please refer to FIG. 11. FIG. 11 is a schematic structural diagram of another VGA disclosed in an embodiment of the present invention. As shown in FIG. 11, the VGA may include a first variable gain circuit, a second variable gain circuit, a shunt circuit, an inverse parallel circuit, a first load resistor R1, a second load resistor R2, a first virtual resistor R3, and The second virtual resistor R4, the first variable gain circuit may include a first common emitter pair, a first common transistor pair, a second common transistor pair, a degenerate resistor R5, a capacitor C1 and current sources B1-B2, and the second The variable gain circuit can include a second common emitter pair, a third common base transistor pair, a fourth common base transistor pair, a degradation resistor R6, a capacitor C2, and a current source B3-B4. The anti-parallel circuit consists of two common base transistors. The fifth common base tube pair composed of tubes, the shunt circuit includes a first shunt resistor R7 and a second shunt resistor R8, where:

The first common injection tube pair constitutes a common injection common base structure with the first common base tube pair and the second common base tube pair, and the second common injection tube pair constitutes a third common base tube pair and the fourth common base tube pair respectively. The cascode structure, one end of the first load resistor R1 is respectively coupled to the collector of one common base tube in the first common base tube pair, the collector of one common base tube in the third common base tube pair, and the fifth common base tube For the collector of one common base tube, one end of the second load resistor R2 is coupled to the collector of the other common base tube in the first common base tube pair, and the collector of the other common base tube in the third common base tube pair. And the collector of the other common base tube in the fifth common base tube pair, one end of the first virtual resistor R3 is coupled to one end of the second virtual resistor R4, the collectors of the two common base tubes in the second common base tube pair, The collector of the two common base transistors in the fourth common base tube pair, one end of the first shunt resistor R7 and one end of the second shunt resistor R8, the emitter of one common base tube in the fifth common base tube pair is coupled to the third common base tube The emitter of the other common base tube in the base tube pair, the emitter of the other common base tube in the fifth common base tube pair is coupled to the emitter of one common base tube in the third common base tube pair, the first shunt resistor R7 The other end is coupled to the emitter of one common base tube in the first common base tube pair, the other end of the second shunt resistor R8 is coupled to the emitter of the other common base tube in the first common base tube pair, and the other end of the first load resistor R1 One end, the other end of the second load resistor R2, the other end of the first virtual resistor R3, and the other end of the second virtual resistor R3 are respectively used to couple the power supply, and the first current source B1 is respectively coupled to the first common emitter pair. The emitter and the ground terminal of the radio tube, the second current source B2 is respectively coupled to the emitter and the ground terminal of the other common radio in the first common radio pair, and the third current source B3 is respectively coupled to the one in the second common radio tube pair The emitter and the ground of the common emitter, the fourth current source B4 is respectively coupled to the emitter and the ground of the other of the second common emitter, and the two ends of the first capacitor C1 are respectively coupled to the first common emitter For the emitters of the two common emitters, both ends of the second capacitor C2 are respectively coupled to the emitters of the two common emitters for the second pair of common emitters. The first degenerative resistor R5 is connected in parallel with the first capacitor C1. The two degenerate resistors R6 are connected in parallel with the second capacitor C2. The base of one common emitter in the first common emitter pair and the base of one common emitter in the second common emitter pair are the forward input terminals of the VGA. The gate of the other common emitter in the common emitter pair and the base of the other common emitter in the second common emitter pair are the reverse input end of the VGA. One end of the first load resistor R1 is the reverse of the VGA. To the output end, one end of the second load resistor R2 is the positive output end of the VGA, the bases of the two common base transistors in the first common base transistor pair and the bases of the two common base transistors in the fourth common base transistor pair. electrode coupled bias voltage V _cpH, a second group of two common base pipe common base transistor is coupled bias voltage V _cnH, a third group of two common base pipe of the common base transistor is coupled bias Set the voltage V _cpH , and the bases of the two common base transistors in the fifth common base transistor pair are respectively coupled to the bias voltage V _cnL .

Among them, Figure 11 is compared with Figure 10, the other parts of the two VGAs are not used, but the internal structure of the shunt circuit is different. The working principle shown in FIG. 11 is the same as the working principle shown in FIG. 10, and the detailed description can refer to the description of the working principle corresponding to FIG. 10, which will not be repeated here.

In Figure 6 and Figure 9 are the cascode structure composed of two NMOS tubes. Based on the same principle, various cascode structures composed of MOS tubes are also applicable to the VGA shown in Figure 6 and Figure 9 structure. In Figures 10 and 11, the cascode structure composed of two npn transistors is shown. Based on the same principle, various cascode structures composed of transistors are also suitable for the VGA shown in Figures 10-11. structure.

The specific implementations described above further describe the purpose, technical solutions and beneficial effects of this application in detail. It should be understood that the above are only specific implementations of this application and are not intended to limit the scope of this application. The protection scope, any modification, equivalent replacement, improvement, etc. made on the basis of the technical solution of this application shall be included in the protection scope of this application.

Claims

A variable gain amplifier VGA, which is characterized by comprising a first variable gain circuit, a second variable gain circuit, a shunt circuit, an anti-parallel circuit, a first load resistance, a second load resistance, a first dummy (dummy) ) A resistor and a second virtual resistor. The first variable gain circuit includes a first cascode pair, a first cascode pair and a second cascode pair, and the second variable gain circuit includes a second cascode pair. The source tube pair, the third cascode tube pair and the fourth cascode tube pair, of which:

The first cascode pair constitutes a cascode structure with the first cascode pair and the second cascode pair, respectively, and the second cascode pair forms a cascode structure with the third cascode pair, respectively. The tube pair and the fourth cascode tube pair form a cascode structure, and the first load resistor is respectively coupled to the drain of one cascode tube in the first cascode tube pair and the third cascode tube The drain of one cascode tube is centered, and the second load resistor is coupled to the drain of the other cascode tube in the first cascode tube pair and the other cascode tube in the third cascode tube pair. The first dummy resistor is coupled to the second dummy resistor, the drains of the two common gate transistors in the second cascode transistor pair, and the two common gate transistors in the fourth cascode transistor pair. The shunt circuit respectively couples the sources of the two cascode transistors in the first cascode transistor pair and the first virtual resistor, and the anti-parallel circuit couples the third cascode transistor respectively The source of the two common gate transistors, the first load resistance and the second load resistance in the tube pair.
The VGA according to claim 1, wherein the anti-parallel circuit is a fifth cascode pair consisting of two cascode transistors, wherein:

The inverse parallel circuit respectively coupling the sources of the two cascode transistors in the third cascode pair, the first load resistance and the second load resistance includes:

The first load resistor is coupled to the drain of one cascode in the fifth cascode pair, and the second load resistor is coupled to the drain of the other cascode in the fifth cascode pair, so The source of one cascode in the fifth cascode pair is coupled to the source of the other cascode in the third cascode pair, and the source of the other cascode in the fifth cascode pair The electrode is coupled to the source electrode of one cascode tube in the third cascode tube pair.
The VGA according to claim 1, wherein the shunt circuit is a sixth cascode tube pair composed of two cascode tubes, wherein:

The shunt circuit respectively coupling the sources of two cascode transistors in the first cascode transistor pair and the first virtual resistor includes:

The first virtual resistor is respectively coupled to the drains of two cascodes in the sixth cascode pair, and the source of one cascode in the sixth cascode pair is coupled to the first cascode The source of one cascode tube is centered, and the source of the other cascode tube in the sixth cascode tube pair is coupled to the source of the other cascode tube in the first cascode tube pair.
The VGA according to claim 1, wherein the shunt circuit comprises a first shunt resistor and a second shunt resistor, wherein:

The shunt circuit respectively coupling the sources of two cascode transistors in the first cascode transistor pair and the first virtual resistor includes:

The first virtual resistor is respectively coupled to one end of the first shunt resistor and one end of the second shunt resistor, and the other end of the first shunt resistor is coupled to the first common gate transistor pair. The source electrode, the other end of the second shunt resistor is coupled to the source electrode of the other cascode transistor in the first cascode pair.
The VGA according to any one of claims 1 to 4, wherein the first load resistance, the second load resistance, the first virtual resistance, and the second virtual resistance are respectively used for coupling power.
The VGA according to any one of claims 1-5, wherein the first variable gain circuit further comprises a first current source and a second current source, and the second variable gain circuit further comprises a third The current source and the fourth current source, where:

The first current source is respectively coupled to the source and the ground terminal of one common source tube in the first common source tube pair, and the second current source is respectively coupled to the other common source tube in the first common source tube pair The source and ground of the third current source are respectively coupled to the source and the ground of one of the second common source transistor pair, and the fourth current source is respectively coupled to the second common source transistor Center the source and ground of the other common source tube.
The VGA according to any one of claims 1 to 6, wherein the first variable gain circuit further comprises a first capacitor, and the second variable gain circuit further comprises a second capacitor, wherein:

Both ends of the first capacitor are respectively coupled to the sources of the two common source transistors in the first common source transistor pair, and both ends of the second capacitor are respectively coupled to the two common source transistors in the second common source transistor pair. The source of the source tube.
7. The VGA according to any one of claims 1-7, wherein the first variable gain circuit further comprises a first degradation resistor, and the second variable gain circuit further comprises a second degradation resistor, wherein:

Both ends of the first degeneration resistor are respectively coupled to the sources of the two common source transistors in the first common source transistor pair, and both ends of the second degeneration resistor are respectively coupled to the two sources of the second common source transistor pair. The source of a common source tube.
A VGA, characterized by comprising a first variable gain circuit, a second variable gain circuit, a shunt circuit, an inverse parallel circuit, a first load resistance, a second load resistance, a first virtual resistance and a second virtual resistance , The first variable gain circuit includes a first common emitter pair, a first common base transistor pair, and a second common base transistor pair, and the second variable gain circuit includes a second common emitter pair, a third common emitter pair, Base tube pair and the fourth common base tube pair, of which:

The first common injection tube pair forms a common injection common base structure with the first common base tube pair and the second common base tube pair, and the second common injection tube pair and the third common base tube pair respectively form a common base structure. The tube pair and the fourth common base tube pair form a cascode structure, and the first load resistor is respectively coupled to the collector of one common base tube in the first common base tube pair and the third common base tube Aligning the collector of one common base tube, the second load resistor is respectively coupled to the collector of the other common base tube in the first common base tube pair and the other common base tube in the third common base tube pair The first virtual resistor is coupled to the second virtual resistor, the collectors of the two common base transistors in the second common base transistor pair, and the two common base transistors in the fourth common base transistor pair. The shunt circuit couples the emitters of the two common base transistors in the first common base transistor pair and the first virtual resistor respectively, and the anti-parallel circuit is respectively coupled to the third common base transistor The emitter of the two common base tubes in the tube pair, the first load resistance and the second load resistance.
The VGA according to claim 9, wherein the anti-parallel circuit is a fifth common base transistor pair composed of two common base transistors, wherein:

The inverse parallel circuit respectively coupling the emitters of the two common base transistors in the third common base transistor pair, the first load resistance and the second load resistance includes:

The first load resistor is coupled to the collector of one common base transistor in the fifth common base transistor pair, and the second load resistor is coupled to the collector of the other common base transistor in the fifth common base transistor pair, so The emitter of one common base tube in the fifth common base tube pair is coupled to the emitter of the other common base tube in the third common base tube pair, and the emitter of the other common base tube in the fifth common base tube pair The pole is coupled to the emitter of one common base tube in the third common base tube pair.
9. The VGA according to claim 9, wherein the shunt circuit is a sixth common base transistor pair composed of two common base transistors, wherein:

The shunt circuit respectively coupling the emitters of the two common base transistors in the first common base transistor pair and the first virtual resistor includes:

The first virtual resistor is respectively coupled to the collectors of two common base transistors in the sixth common base transistor pair, and the emitter of one common base transistor in the sixth common base transistor pair is coupled to the first common base transistor The emitter of one common base tube is centered, and the emitter of the other common base tube in the sixth common base tube pair is coupled to the emitter of the other common base tube in the first common base tube pair.
The VGA according to claim 9, wherein the shunt circuit comprises a first shunt resistor and a second shunt resistor, wherein:

The shunt circuit respectively coupling the emitters of the two common base transistors in the first common base transistor pair and the first virtual resistor includes:

The first virtual resistor is respectively coupled to one end of the first shunt resistor and one end of the second shunt resistor, and the other end of the first shunt resistor is coupled to the first common base transistor pair. The other end of the second shunt resistor is coupled to the emitter of the other common base tube in the first common base tube pair.