CN114267669A - 边缘带凹口衬底封装以及相关联的系统和方法 - Google Patents

边缘带凹口衬底封装以及相关联的系统和方法 Download PDF

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Publication number
CN114267669A
CN114267669A CN202111072006.6A CN202111072006A CN114267669A CN 114267669 A CN114267669 A CN 114267669A CN 202111072006 A CN202111072006 A CN 202111072006A CN 114267669 A CN114267669 A CN 114267669A
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China
Prior art keywords
die
substrate
edge
back side
inward
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CN202111072006.6A
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Inventor
O·R·费伊
M·E·瓦勒
J·L·沃尔茨
D·W·萨瑟恩
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Micron Technology Inc
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Micron Technology Inc
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    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
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    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
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Abstract

提供用于具有边缘带凹口衬底的半导体装置的系统和方法。所述装置大体上包含衬底，所述衬底具有前侧、具有衬底触点的背侧和处于所述衬底的边缘处的向内凹口。所述装置包含裸片，所述裸片具有附接到所述衬底的所述前侧的作用侧并且定位成使得能够从所述衬底的所述背侧穿过所述向内凹口接入所述裸片的接合衬垫。所述装置包含线接合件，所述线接合件布设穿过所述向内凹口并且将所述裸片的所述接合衬垫电耦合到所述衬底触点。所述装置可另外包含第二裸片，所述第二裸片具有附接到所述第一裸片的所述背侧的作用侧并且定位成从所述第一裸片横向偏移以使得能够在所述第一裸片的所述边缘周围穿过所述向内凹口接入所述第二接合衬垫。

Description

边缘带凹口衬底封装以及相关联的系统和方法
技术领域
本公开大体针对于半导体装置，且在若干实施例中，更具体地说，针对于用边缘带凹口衬底进行封装的系统和方法。
背景技术
微电子装置，例如存储器装置、微处理器和发光二极管，通常包含安装到衬底且包覆在保护性覆盖物中的一或多个半导体裸片。半导体裸片包含功能特征，例如存储器单元、处理器电路、互连电路系统等。为减少半导体裸片所占的体积、同时增大所得经包封组合件的容量和/或速度，半导体裸片制造商承受着越来越大的压力。为满足这些和其它需求，半导体裸片制造商通常竖直叠加地堆叠多个半导体裸片，以增大半导体裸片所安装到的电路板或其它元件上的有限容积内的微电子装置的容量或性能。
一些半导体封装使用窗型衬底，所述窗型衬底具有穿过衬底的中心区的开口。裸片安放于开口上方，且接合线从裸片前侧的接合衬垫布设穿过开口到衬底背侧的触点以将裸片电耦合到衬底。窗型衬底通常使得接合线能够较短，这提高裸片和衬底之间的信号发射的效率和性能。在线接合之后，将包封物施涂到窗区域以保护裸片和衬底上的接合线和连接件。
窗型衬底的背侧可包含球栅阵列(BGA)表面安装型封装，其用以将微电子装置永久性地安装到另一组件。BGA相较于其它封装配置通常提供较大互连密度，且将引线从裸片连接到球体的迹线通常也较短，这实现高速下的较好性能。
发明内容
根据本申请案的一方面，提供一种半导体装置。所述半导体装置包括：包括硅的衬底，所述衬底具有前侧、具有衬底触点的背侧和处于所述衬底的边缘处的向内凹口；裸片，其具有背侧和附接到所述衬底的所述前侧的作用侧，所述裸片具有处于所述作用侧的边缘上的接合衬垫，且所述裸片定位成使得能够从所述衬底的所述背侧穿过所述向内凹口接入所述接合衬垫；和线接合件，其布设穿过所述向内凹口并且将所述裸片的所述接合衬垫电耦合到所述衬底触点。
根据本申请案的另一方面，提供一种半导体装置。所述半导体装置包括：包括硅的衬底，所述衬底具有前侧、具有第一衬底触点和第二衬底触点的背侧、处于所述衬底的第一边缘处的第一向内凹口，以及处于所述衬底的与所述第一边缘相对的第二边缘处的第二向内凹口；第一裸片，其具有背侧和附接到所述衬底的所述前侧的作用侧，所述第一裸片具有处于所述第一裸片的所述作用侧的边缘上的第一接合衬垫，所述第一裸片定位成使得能够从所述衬底的所述背侧穿过所述第一向内凹口接入所述第一接合衬垫；第二裸片，其具有背侧和附接到所述衬底的所述前侧的作用侧，所述第二裸片具有处于所述第二裸片的所述作用侧的边缘上的第二接合衬垫，所述第二裸片定位成使得能够从所述衬底的所述背侧穿过所述第二向内凹口接入所述第二接合衬垫；第一线接合件，其布设穿过所述第一向内凹口并且将所述第一接合件电耦合到所述第一衬底触点；和第二线接合件，其布设穿过所述第二向内凹口并且将所述第二接合衬垫电耦合到所述第二衬底触点。
根据本申请案的又一方面，提供一种半导体装置封装方法。所述半导体装置封装方法包括：在包括硅的衬底的边缘上形成向内凹口，所述衬底具有前侧和具有衬底触点的背侧；将裸片的作用侧附接在所述衬底的所述前侧上，使得能够从所述衬底的所述背侧穿过所述向内凹口接入所述裸片的所述作用侧的边缘上的接合衬垫；和通过布设穿过所述向内凹口的线接合件将所述裸片的所述接合衬垫电耦合到所述衬底触点。
附图说明
图1A和1B是示出根据本发明技术的实施例的具有边缘带凹口衬底的半导体装置的各个组装阶段的透视图。
图1C和1D是示出图1A和1B的半导体装置的各个组装阶段的放大横截面视图。
图1E是示出图1A和1B的半导体装置的组装阶段的透视图。
图2A和2B是示出根据本发明技术的实施例的制造具有边缘带凹口衬底的半导体装置的各个阶段的放大横截面视图。
图3是根据本发明技术的实施例的包含半导体装置的系统的示意图。
具体实施方式
本文公开的技术涉及半导体装置、具有半导体装置的系统，以及用于制造半导体装置的相关方法。术语“半导体装置”一般是指包含一或多个半导体材料的固态装置。半导体装置的实例包含逻辑装置、存储器装置和二极管等等。此外，术语“半导体装置”可以指成品装置或在变为成品装置之前的各个处理阶段处的组合件或其它结构。在一些实施例中，个别半导体装置可以“被封装”且包含包覆装置中的组件和电连接件的成型材料。
取决于其使用的上下文，术语“衬底”可指支撑电子组件(例如，裸片)的结构，例如晶片级衬底，或指经单分裸片级衬底，或用于裸片堆叠应用的另一裸片。可在晶片层级或在裸片层级执行本文中所描述的方法的适当步骤。此外，除非情境另有指示，否则可使用常规的半导体制造技术来形成本文中所公开的结构。举例来说，材料可使用化学气相沉积、物理气相沉积、原子层沉积、旋涂、电镀和/或其它合适的技术沉积。类似地，举例来说，可使用等离子蚀刻、湿式蚀刻、化学-机械平坦化或其它合适的技术移除材料。
本发明技术包含具有边缘带凹口衬底的半导体装置。衬底上的向内的边缘凹口被配置成使得紧凑线接合件可从裸片堆叠的互连接合衬垫布设到边缘带凹口衬底的相对侧上的触点。常规半导体装置封装使用布设于封装顶部的线环将裸片的接合衬垫电耦合到衬底的安装有裸片的侧部上的触点。这些类型的线环首先从裸片的接合衬垫向上延伸并且接着向下延伸到衬底，此配置会在模制之后增加封装的总高度并且可能超过针对大批量制造(HVM)的高度限制。常规窗型衬底具有可用以去除线接合件的向上环圈部分的中心开口；然而，一些裸片(例如NAND存储器裸片、随机存取存储器(例如，相变RAM和LPDRAM)等)在裸片的边缘处具有互连接合衬垫并且不兼容与常规窗型衬底一起使用。
本发明技术通常针对于经接合半导体装置，其具有边缘带凹口的封装衬底和附接到所述封装衬底的半导体裸片。所述封装衬底具有安装表面和阵列表面，裸片附接到所述安装表面，所述阵列表面与安装表面相对并且具有电触点和焊垫。半导体裸片具有作用侧，所述作用侧具有附接到安装表面的接合衬垫。接合衬垫处于裸片的边缘，且裸片定位于安装表面上，使得裸片的边缘上的接合衬垫与边缘凹口对准以用于从接合衬垫到衬底的阵列表面的线接合件进出。在堆叠配置中，裸片可横向偏移或阶梯式定位以允许接入堆叠中每一裸片的接合衬垫。线接合件可从裸片的作用侧形成，布设穿过边缘凹口，并且连接到衬底的阵列表面上的触点。这从线环去除向上或横向延伸超过衬底和裸片组合的包封体的部分。半导体装置可具有通过填充边缘凹口包覆裸片和线接合件的包封物，且可在单个模塑空腔中执行此过程。在一些实施例中，本发明技术减小模制之后的半导体装置的封装大小并且减小线接合件的平均长度。本发明技术的边缘凹口可被配置成遵守现有工业标准布局，包含电子装置工程设计联合协会(JEDEC)BGA布局等等。
图1A、1B和1E示出半导体装置100(“装置100”)的透视图，且图1C和1D示出装置100的各个组装阶段的放大横截面视图。装置100可为例如NAND存储器裸片堆叠的存储器阵列，其可另外包含一或多个逻辑裸片。装置100包含具有向内凹口(“凹口104”)、前侧112(例如，安装表面)和背侧114(例如，阵列表面)的硅衬底110。衬底110示出为在衬底的一个边缘上具有单个凹口104；然而，在其它实施例中，衬底110的任何数目个边缘具有凹口(例如，衬底的两个边缘上具有凹口，如图2A和2B中所示)，或可每一边缘包含多个凹口。凹口104可沿着边缘长度的任何百分比延伸并且具有进入衬底的任何深度，这可取决于堆叠106中的裸片数目，如将在下文更详细地描述。另外，凹口104示出为具有大体正方形拐角和垂直面，但可具有任何适当的形状，包含有角度的面、倒圆角等。
参考图1B，装置100具有任选微控制器102(例如，逻辑裸片)和附接到衬底110的前侧112的第一裸片120。第一裸片120包含背侧122和面向衬底110的前侧112的作用侧124。参考图1C，微控制器102经由互连件103电耦合到衬底110，且第一裸片120具有沿着第一裸片120的边缘的接合衬垫128。第一裸片120被定位成部分地悬突凹口104，使得第一裸片120的作用侧124的边缘上的接合衬垫128暴露以接纳线接合件126并且将第一裸片120电耦合到衬底110的触点118。虽然在横截面视图中仅示出单个接合衬垫128和单个触点118，但装置100通常具有大量接合衬垫128和触点118。
裸片堆叠106可具有第二裸片130，所述第二裸片130包含背侧132、在横向偏移配置中接合到第一裸片120的背侧122的作用侧134以及处于作用侧134上的接合衬垫138。第二裸片130被定位成部分地悬突第一裸片120和凹口104以使得第二裸片130的作用侧134的边缘上的接合衬垫138暴露以接纳线接合件136并且将第二裸片130电耦合到衬底110上的触点118。裸片堆叠106可类似地包含任何数目个额外裸片，例如第三裸片140和第四裸片150。第三裸片140包含背侧142、在横向偏移配置中接合到第二裸片130的背侧132的作用侧144以及处于作用侧144上的接合衬垫148。第三裸片140被定位成使第一裸片120和第二裸片130部分地悬突以及凹口104以使得第三裸片140的作用侧144的边缘上的接合衬垫148暴露以接纳线接合件146并将第三裸片140电耦合到衬底110上的触点118。第四裸片150包含背侧152、在横向偏移配置中接合到第三裸片140的背侧142的作用侧154以及处于作用侧154上的接合衬垫158。第四裸片150被定位成部分地悬突第一裸片120、第二裸片130和第三裸片140以及凹口104以使得第四裸片150的作用侧154的边缘上的接合衬垫158暴露以接纳线接合件156并且将第四裸片150电耦合到衬底110上的触点118。虽然在堆叠的横向偏移阶梯式配置中示出四个裸片，但在其它实施例中，用边缘带凹口衬底封装的任何数目个裸片在本发明技术的范围内。
参考图1D，装置100可另外包含在裸片120、130、140和150接合到衬底110并且电耦合到衬底110之后覆盖装置100的组件的封装模塑材料160。通过使液体模塑材料在模套(未示出)的边界内流过装置100的经安装组件上方的注道(未示出)来施涂封装模塑材料160。模套被配置成约束封装的外部形状并且容纳所述形状直到液体模塑材料固化。模塑材料160首先施涂到衬底110的前侧112和裸片120、130、140和150，并且接着流过凹口104并填满，进而保护衬底110的背侧114上的线接合件126、136、146和156以及触点118。在其它实施例中，在任何位置例如穿过横向注道、底部注道等施涂模塑材料160以形成装置100的外部封装形状。
图1E示出在用封装模塑材料160包覆微控制器102、裸片120、130、140和150等之后的装置100。封装装置100可通过互连布置(例如球栅阵列(BGA))电耦合到其它组件。通过在模塑材料160固体化之后将球体162(例如，焊球)附接到衬底110的背侧114来形成BGA。球体162可具有一直径使得模塑材料160的延伸超过背侧114的部分含于由装置100和安装表面之间的球体162大小产生的间隙内。其它互连配置也在本发明技术的范围内，包含支柱和其它合适的互连结构。
图2A和2B示出根据本发明技术的实施例配置的半导体装置200(“装置200”)(例如存储器阵列)的各个组装阶段的放大横截面视图。装置200在总体结构上类似于图1A-1E的装置100，但具有具多个裸片堆叠的双重边缘带凹口衬底配置。参考图1A-1E中的类似特征以相似参考标号示出装置200，但用200系列表示第一侧(图2A和2B的右侧)，且用300系列表示第二侧(图2A和2B的左侧)，且所述特征可具有变化和/或具有不同形状和大小。装置200包含硅衬底210，其具有第一向内凹口(“第一凹口204”)、第二向内凹口(“第二凹口304”)、前侧212(例如，安装表面)以及背侧214(例如，阵列表面)。装置200还可包含各种其它半导体组件，例如具有互连件203的微控制器202等。在此配置中，微控制器202可定位于裸片堆叠的中心，这允许从裸片堆叠到微控制器的均一迹线长度。
参考图2A，装置200具有靠近第一凹口204的第一裸片堆叠206和在衬底210的相对边缘靠近第二凹口304的第二裸片堆叠306。第一裸片堆叠206包含分别具有背侧222a-d和作用侧224a-d的第一、第二、第三和第四裸片220a-d。裸片220a-d定位成在横向偏移的阶梯式配置中悬突第一凹口204，这类似于装置100的裸片堆叠106。作用侧224a-d面朝衬底210的前侧212。每个作用侧224a-d横向偏移以部分地悬突第一凹口204，使得作用侧224a-d的边缘上的接合衬垫228a-d暴露以分别接纳线接合件226a-d，从而将裸片220a-d电耦合到衬底210的触点218。
第二裸片堆叠306包含分别具有背侧322a-d和作用侧324a-d的第一、第二、第三和第四裸片320a-d。裸片320a-d定位成在横向偏移的阶梯式配置中悬突第二凹口304，类似于装置100的裸片堆叠106，但与装置100的裸片堆叠106镜像对称。裸片320a-d的作用侧324a-d面朝衬底210的前侧212。每个作用侧324a-d横向偏移以部分悬突第二凹口304，使得作用侧324a-d的边缘上的接合衬垫328a-d暴露以分别接纳线接合件326a-d，从而将裸片320a-d电耦合到衬底210的触点318。虽然在第一裸片堆叠206和第二裸片堆叠306中的每一个中以横向偏移的阶梯式配置示出四个裸片，但在其它实施例中，任何数目个裸片布置于堆叠中以用边缘带凹口衬底进行封装，并且也在本发明技术的范围内。
参考图2B，如上文所描述，装置200包含在裸片堆叠206和306已经接合并电耦合到衬底210之后包覆装置200的组件的封装模塑材料260。通过使液体模塑材料在模套(未示出)的边界内流过装置200的经安装组件上方的注道(未示出)来施涂封装模塑材料260。模套被配置成约束封装的外部形状并且容纳所述形状直到液体模塑材料固化。模塑材料260首先施涂到衬底210的前侧212以及裸片堆叠206和306，并且接着流过第一凹口204和第二凹口304并填满，进而保护衬底210的背侧214上的线接合件226a-d和326a-d以及触点218和318。在其它实施例中，在任何位置例如穿过横向注道、底部注道等施涂模塑材料260以形成封装。虽然图中未示出，但装置200可通过类似于图1E中示出的BGA的BGA电耦合到其它组件。其它互连配置也在本发明技术的范围内，包含支柱和其它合适的互连结构。虽然在图2A-2B中描绘了装置200的一个示范性配置，但装置的任何适当的配置也在本发明技术的范围内，例如三个或四个凹口和对应裸片堆叠、与每边缘的一或多个凹口处于同一边缘的多个裸片堆叠等。
本文所描述的互连件可由适当的导电材料(例如铜(Cu))形成，且可具有电连接件(例如，锡银(SnAg)焊料盖)。在组装期间，焊料盖可经回焊、声波回焊或其它技术。接合衬垫可为铜焊垫并且可使用铜与铜接合或其它合适的技术接合。
图3是说明根据本发明技术的实施例的并入有半导体装置的系统的框图。具有上文参考图1A-2B所描述的特征的半导体装置中的任一个可并入到大量更大和/或更复杂的系统中的任一个中，所述系统的一个代表性实例为图3中示意性地展示的系统300。系统300可包含处理器302、存储器304(例如，SRAM、DRAM、快闪和/或其它存储器装置)、输入/输出装置306和/或其它子系统或组件308。上文参考图1A-2B所描述的半导体组合件、装置和装置封装可包含于图3中所示的元件中的任一个中。所得系统300可被配置成执行多种适当的计算、处理、存储、感测、成像和/或其它功能中的任一个。相应地，系统300的代表性实例包含但不限于计算机和/或其它数据处理器，例如台式计算机、手提式计算机、网络家电、手持式装置(例如，掌上型计算机、可穿戴式计算机、蜂窝或移动电话、个人数字助理、音乐播放器等)、平板计算机、多处理器系统、基于处理器的或可编程的消费型电子装置、网络计算机和微型计算机。系统300的额外代表性实例包含灯、相机、车辆等。在这些和其它实例中，系统300可容纳在单个单元中或例如通过通信网络分布在多个互连单元上。相应地，系统300的组件可包含本地和/或远程存储器存储装置和多种多样的合适的计算机可读媒体中的任一个。
如在前文描述中所使用，鉴于图中所展示的取向，术语“竖直”，“横向”，“上部”和“下部”可指半导体装置中的特征的相对方向或位置。举例来说，“上部”或“最上部”可指比另一特征更接近页面的顶部定位的特征。然而，这些术语应在广义上予以解释以包含具有例如颠倒或倾斜取向的其它取向的半导体装置，其中顶部/底部、上方/下方、高于/低于、向上/向下、左/右以及远侧/近侧可取决于取向而互换。此外，为了易于参考，贯穿本公开，相同附图标号用于标识类似或相似组件或特征，但使用相同附图标记并不暗示特征应理解为相同的。实际上，在本文中所描述的许多实例中，相同编号的特征具有结构和/或功能上彼此不同的多个实施例。此外，除非本文中具体地标注，否则相同着色可用以指示横截面中可在成分上类似的材料，但使用相同着色并不暗示材料应理解为相同的。
前述公开内容还可参考数量和数目。除非特别说明，否则不应将这些数量及数目视为限制性的，而应作为与新技术相关的可能数量或数目的示例。另外，在这点上，本公开可使用术语“多个”指代数量或数目。在这点上，术语“多个”表示大于一，例如，二、三、四、五等的任何数目。出于本公开的目的，短语“A、B和C中的至少一个”例如意指(A)、(B)、(C)、(A及B)、(A及C)、(B及C)，或(A、B及C)，包含列出多于三个元素时的所有进一步可能的排列。
从前文应了解，本文中已出于说明的目的描述了新技术的具体实施例，但可在不偏离本公开的情况下进行各种修改。因此，除受到所附权利要求书的限制外，本发明不受限制。此外，在特定实施例的上下文中描述的新技术的某些方面也可在其它实施例中组合或消除。此外，尽管已在那些实施例的上下文中描述了与新技术的某些实施例相关联的优势，但其它实施例也可显示此类优势，且并非所有的实施例都要展现此类优势以落入本公开的范围内。因此，本公开和相关联的技术可涵盖未明确地在本文中展示或描述的其它实施例。

Claims (20)

1.一种半导体装置，其包括：
包括硅的衬底，所述衬底具有前侧、具有衬底触点的背侧和处于所述衬底的边缘处的向内凹口；
裸片，其具有背侧和附接到所述衬底的所述前侧的作用侧，所述裸片具有处于所述作用侧的边缘上的接合衬垫，且所述裸片定位成使得能够从所述衬底的所述背侧穿过所述向内凹口接入所述接合衬垫；和
线接合件，其布设穿过所述向内凹口并且将所述裸片的所述接合衬垫电耦合到所述衬底触点。
2.根据权利要求1所述的半导体装置，其中所述裸片包括具有第一接合衬垫的第一裸片且所述线接合件包括将所述第一接合衬垫电耦合到所述衬底触点的第一线接合件，所述半导体装置另外包括：
第二裸片，其具有背侧和附接到所述第一裸片的所述背侧的作用侧，所述第二裸片具有处于所述作用侧的边缘上的第二接合衬垫，且所述第二裸片定位成从所述第一裸片横向偏移以使得能够在所述第一裸片的所述边缘周围穿过所述向内凹口接入所述第二接合衬垫；和
第二线接合件，其布设穿过所述向内凹口并且将所述第二接合衬垫电耦合到所述衬底触点。
3.根据权利要求2所述的半导体装置，其另外包括覆盖所述第一裸片和第二裸片、所述第一线接合件和第二线接合件并且至少部分地填充所述向内凹口的模塑材料。
4.根据权利要求2所述的半导体装置，其另外包括具有背侧和附接到所述第二裸片的所述背侧的作用侧的第三裸片，其中：
所述第三裸片具有处于所述第三裸片的所述作用侧的边缘上的第三接合衬垫；且
所述第三裸片定位成从所述第一裸片和第二裸片两者横向偏移以使得能够在所述第一裸片和第二裸片的所述边缘周围穿过所述向内凹口接入所述第三接合衬垫。
5.根据权利要求4所述的半导体装置，其另外包括布设穿过所述向内凹口并且将所述第三接合衬垫电耦合到所述衬底触点的第三线接合件。
6.根据权利要求5所述的半导体装置，其另外包括具有背侧和附接到所述第三裸片的所述背侧的作用侧的第四裸片，其中：
所述第四裸片具有处于所述第四裸片的所述作用侧的边缘上的第四接合衬垫；且
所述第四裸片定位成从所述第一裸片、第二裸片和第三裸片中的每一个横向偏移以使得能够在所述第一裸片、第二裸片和第三裸片的所述边缘周围穿过所述向内凹口接入所述第四接合衬垫。
7.根据权利要求6所述的半导体装置，其另外包括布设穿过所述向内凹口并且将所述第四接合衬垫电耦合到所述衬底触点的第四线接合件。
8.根据权利要求1所述的半导体装置，其另外包括接合到所述衬底的所述背侧并且通过所述第一线接合件电耦合到所述第一裸片并通过所述第二线接合件电耦合到所述第二裸片的互连件。
9.根据权利要求8所述的半导体装置，其中所述互连件包括球栅阵列。
10.一种半导体装置，其包括：
包括硅的衬底，所述衬底具有前侧、具有第一衬底触点和第二衬底触点的背侧、处于所述衬底的第一边缘处的第一向内凹口，以及处于所述衬底的与所述第一边缘相对的第二边缘处的第二向内凹口；
第一裸片，其具有背侧和附接到所述衬底的所述前侧的作用侧，所述第一裸片具有处于所述第一裸片的所述作用侧的边缘上的第一接合衬垫，所述第一裸片定位成使得能够从所述衬底的所述背侧穿过所述第一向内凹口接入所述第一接合衬垫；
第二裸片，其具有背侧和附接到所述衬底的所述前侧的作用侧，所述第二裸片具有处于所述第二裸片的所述作用侧的边缘上的第二接合衬垫，所述第二裸片定位成使得能够从所述衬底的所述背侧穿过所述第二向内凹口接入所述第二接合衬垫；
第一线接合件，其布设穿过所述第一向内凹口并且将所述第一接合衬垫电耦合到所述第一衬底触点；和
第二线接合件，其布设穿过所述第二向内凹口并且将所述第二接合衬垫电耦合到所述第二衬底触点。
11.根据权利要求10所述的半导体装置，其另外包括：
第三裸片，其具有背侧和附接到所述第一裸片的所述背侧的作用侧，所述第三裸片具有处于所述第三裸片的所述作用侧的边缘上的第三接合衬垫，且所述第三裸片定位成从所述第一裸片横向偏移以使得能够在所述第一裸片的所述边缘周围穿过所述第一向内凹口接入所述第三接合衬垫；
第四裸片，其具有背侧和附接到所述第二裸片的所述背侧的作用侧，所述第四裸片具有处于所述第四裸片的所述作用侧的边缘上的第四接合衬垫，且所述第四裸片定位成从所述第二裸片横向偏移以使得能够在所述第二裸片的所述边缘周围穿过所述第二向内凹口接入所述第四接合衬垫；
第三线接合件，其布设穿过所述第一向内凹口并且将所述第三接合衬垫电耦合到所述第一衬底触点；和
第四线接合件，其布设穿过所述第二向内凹口并且将所述第四接合衬垫电耦合到所述第二衬底触点。
12.根据权利要求10所述的半导体装置，其另外包括覆盖所述第一裸片和第二裸片、所述第一线接合件和第二线接合件并且至少部分地填充所述第一向内凹口和第二向内凹口的模塑材料。
13.根据权利要求10所述的半导体装置，其另外包括接合到所述衬底的所述背侧并且通过所述第一线接合件电耦合到所述第一裸片并通过所述第二线接合件电耦合到所述第二裸片的互连件。
14.根据权利要求13所述的半导体装置，其中所述互连件包括球栅阵列。
15.一种半导体装置封装方法，其包括：
在包括硅的衬底的边缘上形成向内凹口，所述衬底具有前侧和具有衬底触点的背侧；
将裸片的作用侧附接在所述衬底的所述前侧上，使得能够从所述衬底的所述背侧穿过所述向内凹口接入所述裸片的所述作用侧的边缘上的接合衬垫；和
通过布设穿过所述向内凹口的线接合件将所述裸片的所述接合衬垫电耦合到所述衬底触点。
16.根据权利要求15所述的方法，其中所述裸片包括具有第一接合衬垫的第一裸片且所述线接合件包括将所述第一接合衬垫电耦合到所述衬底触点的第一线接合件，所述方法另外包括：
在横向偏移位置中将第二裸片的作用侧附接在所述第一裸片的背侧上，使得能够从所述衬底的所述背侧穿过所述向内凹口接入所述第二裸片的所述作用侧的边缘上的第二接合衬垫；和
通过布设穿过所述向内凹口的第二线接合件将所述第二接合衬垫电耦合到所述衬底触点。
17.根据权利要求16所述的方法，其中所述衬底触点包括第一衬底触点，且所述向内凹口包括处于所述衬底的第一边缘上的第一向内凹口，所述方法另外包括：
在所述衬底的第二边缘上形成第二向内凹口，所述衬底具有处于所述背侧上的第二衬底触点；
将第三裸片的作用侧附接在所述衬底的所述前侧上，使得能够从所述衬底的所述背侧穿过所述第二向内凹口接入所述第三裸片的所述作用侧的边缘上的第三接合衬垫；和
通过布设穿过所述第二向内凹口的第三线接合件将所述第三接合衬垫电耦合到所述第二衬底触点。
18.根据权利要求17所述的方法，其另外包括：
在横向偏移位置中将第四裸片的作用侧附接在所述第三裸片的背侧上，使得能够从所述衬底的所述背侧穿过所述第二向内凹口接入所述第四裸片的所述作用侧的边缘上的第四接合衬垫；和
通过布设穿过所述第二向内凹口的第四线接合件将所述第四接合衬垫电耦合到所述第二衬底触点。
19.根据权利要求15所述的方法，其另外包括在所述裸片、所述线接合件上方施涂模塑材料并且至少部分地填充所述向内凹口。
20.根据权利要求19所述的方法，其另外包括通过所述线接合件将互连件接合到所述衬底的所述背侧并且将所述互连件电耦合到所述裸片。
CN202111072006.6A 2020-09-16 2021-09-14 边缘带凹口衬底封装以及相关联的系统和方法 Pending CN114267669A (zh)

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