CN114203797A - Super junction gallium oxide transistor based on heterojunction and manufacturing method and application thereof - Google Patents
Super junction gallium oxide transistor based on heterojunction and manufacturing method and application thereof Download PDFInfo
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- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 117
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 107
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
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- 238000000151 deposition Methods 0.000 claims description 11
- 238000011049 filling Methods 0.000 claims description 5
- 229910000480 nickel oxide Inorganic materials 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 claims description 4
- 238000012216 screening Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
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- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 2
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- 229910052751 metal Inorganic materials 0.000 claims description 2
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- 238000005468 ion implantation Methods 0.000 description 3
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- 238000011056 performance test Methods 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
Abstract
The invention discloses a heterojunction-based super junction gallium oxide transistor and a manufacturing method and application thereof, and belongs to the technical field of semiconductor materials and devices. The super-junction gallium oxide transistor comprises a super-junction structure, and the super-junction structure is formed by staggered gallium oxide-based heterogeneous PN junctions formed on a gallium oxide drift region of the transistor. According to the invention, the heterogeneous super-junction structure is formed in the drift region of the gallium oxide channel, the electric field distribution mode of the gallium oxide drift region is corrected, the peak electric field at the edge of the grid electrode is effectively reduced, the electric field in the drift region is diffused from the edge of the grid electrode to the direction of the drain electrode, the breakthrough of the restriction relation between the breakdown voltage and the on-resistance of the oxidant transistor is realized, higher breakdown voltage and lower on-resistance can be obtained, the gallium oxide device with excellent performance is obtained, and a solid foundation is laid for the wide application of the gallium oxide device in the field of electronic power.
Description
Technical Field
The invention belongs to the technical field of semiconductor materials and devices, and particularly relates to a heterojunction-based super junction gallium oxide transistor and a manufacturing method and application thereof.
Background
With the rapid development of integrated circuit technology, the related technology is continuously advanced, and higher power density and conversion efficiency are always pursued targets in the power electronics industry with wide application markets.
The mainstream devices in the electronic power field at present are Si power devices and recently emerging GaN and SiC devices, but the power density and conversion efficiency of the devices cannot be matched with other increasingly developed technologies, and under the condition that the assembly technology has no major breakthrough, even though power electronic equipment manufacturers continuously innovate in circuit design, various advanced topological architectures are proposed, and the efficiency or power density improvement effect brought to a power supply system still meets the bottleneck. In view of the above, many high voltage control equipment and power management related chip manufacturers have focused on the future product development to introduce new generation materials such as silicon carbide and gallium nitride, and hope to make the power density and conversion efficiency of power electronic applications higher by the fundamental breakthrough of materials and chip technology.
For power electronic power devices widely applied to power equipment such as power supplies, inverters and electric devices, key factors mainly considered for preparation materials of the power electronic power devices are as follows: 1. the critical breakdown electric field, the higher critical breakdown electric field can be more widely applied; 2. the melting point temperature is high, and the high melting point represents that the alloy has better high-temperature resistance; 3. the heat conductivity and good heat conductivity are convenient for the device to quickly dissipate heat generated in the work, so that the device can work stably; 4. the energy band gap, which is a decisive feature of power devices, because a larger band gap means that it can withstand the impact of higher load voltages, i.e. has a higher critical breakdown field, and thinner device dimensions can be used at a given voltage, which means less impedance, i.e. less power consumption and higher operating efficiency.
Therefore, the materials with the above characteristics are the basis for the development of power electronic devices and are also the focus of attention of researchers of power electronic devices. Gallium oxide, due to its forbidden bandwidth of about 4.8eV and the higher breakdown electric field characteristics obtained thereby, can withstand the impact of higher load voltage, has higher critical breakdown electric field and higher operation compared with the existing power device materials (e.g. Si forbidden bandwidth of 1.24eV, GaN forbidden bandwidth of 3.4eV, SiC forbidden bandwidth of 3.3eV), and is a research hotspot of power devices. Moreover, gallium oxide has a greater market potential than expensive GaN and SiC.
However, all power devices are under the same physical limit in development, that is, the breakdown voltage and the on-resistance of the device are in a negative correlation characteristic of square term, so that the breakdown voltage and the on-resistance are in a trade-off state. As a new gallium oxide power electronic device, the problem is inevitable in the development process, and the contradiction relationship between the breakdown voltage of the device and the on-resistance of the device exists, so that the development and application prospects of the device are restricted. Moreover, no effective design method is available in the existing gallium oxide power electronic power device, so that the restriction relationship can be effectively broken through, and better device performance can be realized.
Although a reduced-surface-field (RESURF) structure covering a P-type material above a drift region of a device has been proposed to improve the breakdown voltage of the device and reduce the on-resistance, the technique can only suppress the electric field reduction by the depletion of P to N, and the on-resistance is reduced due to the increase of the breakdown voltage; the technology cannot realize lower on-resistance under the same breakdown voltage, and cannot realize higher breakdown voltage under the same on-resistance.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a heterojunction-based super junction gallium oxide transistor and a manufacturing method and application thereof. The invention adopts the super junction structure of the gallium oxide heterojunction introduced into the gallium oxide transistor to break through the contradiction relationship between the breakdown voltage and the on-resistance of the device in the gallium oxide power electronic power device. Based on the super-junction concept used in silicon, a gallium oxide super-junction structure transistor based on gallium oxide heterojunction (heterojunction such as gallium oxide/nickel oxide) is designed, the conventional theoretical limit of gallium oxide materials in the power field can be broken through, the restriction relation of the square term change of breakdown voltage and on-resistance in a gallium oxide power device is solved, the linear correlation change relation is met, and the balance state between the breakdown voltage and the on-resistance is effectively improved. Compared with a device with a traditional structure, the super-junction gallium oxide transistor can realize lower on-resistance under the same breakdown voltage and can also realize higher breakdown voltage under the same on-resistance. The heterojunction super-junction structure can be effectively implemented for both gallium oxide vertical devices and planar devices, and the performance of the devices is improved.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a heterojunction-based super-junction gallium oxide transistor comprises a super-junction structure, wherein the super-junction structure is formed by staggered gallium oxide-based heterogeneous PN junctions formed on a gallium oxide drift region of the transistor.
Preferably, the gallium oxide drift region is etched with parallel-arranged trenches, and the trenches are filled with P-type heterogeneous materials, so as to form staggered gallium oxide-based heterogeneous PN junctions.
Preferably, the P-type heterogeneous material includes, but is not limited to: nickel oxide, iridium oxide, and the like.
Preferably, the filling method of the P-type heterogeneous material includes but is not limited to: atomic layer deposition, vapor deposition, solid phase deposition, physical phase epitaxy, physical deposition, and the like.
Preferably, the transistors include, but are not limited to: horizontal structure gallium oxide transistors, and the like.
Preferably, the transistor includes a gallium oxide substrate, a drain electrode, a source electrode, a gate electrode, and a protective layer, the gallium oxide substrate has a homogeneous or heterogeneous epitaxial conductive layer or a heterogeneous integrated conductive layer, the drain electrode and the source electrode are disposed at two ends of the conductive layer, a middle region of the conductive layer is the gallium oxide drift region, a super junction structure is constructed on the gallium oxide drift region, the gate electrode covers the super junction structure, and the protective layer is disposed above the gate electrode, the drain electrode, and the source electrode.
The invention also provides a manufacturing method of the super junction gallium oxide transistor based on the heterojunction, which comprises the following steps:
(1) screening the substrate: adopting a gallium oxide substrate with a homogeneous or heterogeneous epitaxial conductive layer or a gallium oxide substrate with a heterogeneous integrated conductive layer;
(2) etching the table top: etching a required pattern on the gallium oxide conducting layer of the substrate to form a mesa pattern;
(3) constructing a source drain electrode: carrying out ohmic characteristic improvement treatment on the set source drain region, depositing metal and annealing to form ohmic contact;
(4) constructing a super junction structure: etching gallium oxide grooves which are arranged in parallel in a gallium oxide drift region, and then filling a P-type heterogeneous material in the gallium oxide grooves to form staggered gallium oxide-based heterogeneous PN junctions;
(5) constructing a grid: covering and constructing a grid on the super junction structure;
(6) constructing a protective layer: a protective layer is constructed over the gate, drain and source electrodes.
Preferably, the gallium oxide substrate includes, but is not limited to: one of an alpha-gallium oxide material, a beta-gallium oxide material, a gamma-gallium oxide material, a delta-gallium oxide material, and an epsilon-gallium oxide material.
Preferably, the gallium oxide substrate has a roughness RMS < 1 nm.
Preferably, the process for improving ohmic characteristics includes, but is not limited to, ion implantation, etching, and the like.
Preferably, the method for constructing the gate comprises the following steps: and sequentially covering and depositing a grid medium and a grid field plate medium on the super junction structure, then carrying out grid field plate medium etching and grid metal deposition to form the grid with the grid field plate structure.
Preferably, the method for constructing the protective layer includes: and depositing a passivation material on the set areas of the gate electrode, the drain electrode and the source electrode to form a protective layer. Preferably, the passivation material includes, but is not limited to: at least one of silicon oxide, aluminum oxide and silicon nitride.
The invention also provides application of the heterojunction-based super junction gallium oxide transistor in the field of electronic power.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the gallium oxide heterojunction super-junction structure is introduced into the drift region of the gallium oxide transistor, so that the drift region of the gallium oxide device obtains a better electric field distribution condition, the appearance of a peak electric field is effectively inhibited, higher breakdown voltage and better device performance are realized, and the application field of the device is effectively expanded. Meanwhile, due to the introduction of the gallium oxide heterojunction super-junction structure, a gate edge electric field in a gallium oxide transistor can be effectively inhibited, and higher channel doping concentration is realized, so that lower device on-resistance is obtained, energy loss in device operation is effectively reduced, energy consumption of the device is improved, and higher energy utilization rate and conversion rate are realized.
Drawings
Fig. 1 is a flow chart of the fabrication of a horizontal structure gallium oxide heterojunction transistor of example 1;
FIG. 2 shows the results of performance tests of transistors according to examples 1 to 3 and comparative example 1.
Detailed Description
The technical solutions of the present invention will be further described with reference to the following embodiments, and it should be apparent that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The methods and procedures used in the examples are conventional in the art and, unless otherwise indicated. The starting materials used in the examples are all commercially available and are all the same species used in parallel experiments.
Example 1
A method for manufacturing a gallium oxide heterogeneous super junction transistor with a horizontal structure comprises the following steps:
(1) screening the substrate: adopting a gallium oxide substrate with roughness RMS less than 1nm and a homoepitaxy conductive layer (a gallium oxide substrate with a heteroepitaxy gallium oxide conductive layer or a gallium oxide substrate with a heterointegration gallium oxide conductive layer can also be adopted);
(2) etching the table top: etching a customized pattern on a gallium oxide conducting layer of a substrate to form a mesa pattern, as shown in fig. 1 (a);
(3) constructing a source drain electrode: performing ion implantation and activation on source and drain regions set at two ends of the conducting layer, and forming source and drain ohmic contacts through photoetching, metal deposition, stripping and annealing processes, as shown in fig. 1 (b);
(4) constructing a super junction structure: etching gallium oxide grooves which are arranged in parallel in a gallium oxide drift region in the middle region of the conducting layer (the depth of the grooves is the same as the thickness of the conducting layer, and the grooves are formed by penetrating the conducting layer instantly), forming gallium oxide strips between adjacent grooves, the specification of the grooves is consistent with that of the gallium oxide strips, the width of the grooves is 2 microns, and then filling nickel oxide in the gallium oxide grooves by a solid phase deposition method (the nickel oxide can also be filled by adopting an atomic layer deposition method, a vapor deposition method, an object phase epitaxy method or a physical deposition method and the like) to form staggered gallium oxide-based heterogeneous PN junctions, as shown in figures 1(c) and (d);
(5) constructing a grid with a grid field plate structure: sequentially performing gate dielectric deposition, gate field plate dielectric etching and gate metal deposition on a gate region (namely on the super junction structure) of a sample subjected to heterogeneous super junction structure preparation to form a gate with a gate field plate structure, as shown in fig. 1(e), or performing gate field plate structure preparation;
(6) constructing a protective layer: depositing silicon oxide (aluminum oxide or silicon nitride can also be adopted) on the set areas of the gate electrode, the drain electrode and the source electrode to form a protective layer, and finally carrying out a conventional contact electrode opening process to finish the integral preparation of the device, as shown in fig. 1 (f).
Example 2
Embodiment 2 provides a method for manufacturing a horizontal-structure gallium oxide heterojunction transistor, which is different from embodiment 1 only in that: the widths of the gallium oxide trenches in the step (4) are different, and the width of the gallium oxide trench etched in the embodiment 2 is 3 μm.
Example 3
Comparative example 1
Comparative example 1 differs from example 1 only in not containing a super junction structure, i.e., existing conventional gallium oxide transistors. The method of fabricating the horizontal structure gallium oxide transistor of comparative example 1 is as follows:
(1) screening the substrate: adopting a gallium oxide substrate with the roughness RMS less than 1nm and a homoepitaxial conductive layer;
(2) etching the table top: etching a customized pattern on the gallium oxide conducting layer of the substrate to form a mesa pattern;
(3) constructing a source drain electrode: performing ion implantation and activation on source and drain regions set at two ends of the conducting layer, and forming source and drain ohmic contacts through photoetching, metal deposition, stripping and annealing processes;
(4) constructing a grid with a grid field plate structure: sequentially performing gate dielectric deposition, gate field plate dielectric etching and gate metal deposition on a gallium oxide drift region in the middle region of the conducting layer to form a gate with a gate field plate structure;
(5) constructing a protective layer: and depositing silicon oxide on the set areas of the grid electrode, the drain electrode and the source electrode to form a protective layer, and finally performing a conventional contact electrode opening process to finish the integral preparation of the device.
And (3) performance testing:
the transistors prepared in examples 1 to 3 and comparative example 1 were subjected to a performance test in the following manner: the test was conducted in air using a 1505 machine in standard configuration.
The test results are shown in fig. 2.In FIG. 2, the Control Device group represents comparative example 1, WNiO2 μm represents example 1 group, W NiO3 μm represents example 2 group, WNiO4 μm represents example 3 set. As can be seen from fig. 2, the superjunction gallium oxide transistors of examples 1 to 3 can withstand higher gate voltages than the conventional gallium oxide transistor (comparative example 1).
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the protection scope of the present invention, and although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims (10)
1. The super-junction gallium oxide transistor based on the heterojunction is characterized by comprising a super-junction structure, wherein the super-junction structure is formed by staggered gallium oxide-based heterogeneous PN junctions formed on a gallium oxide drift region of the transistor.
2. The heterojunction-based superjunction gallium oxide transistor according to claim 1, wherein parallel-arranged trenches are etched on said gallium oxide drift region, and said trenches are filled with P-type hetero-material, thereby forming staggered gallium oxide-based hetero-PN junctions.
3. The heterojunction-based superjunction gallium oxide transistor of claim 2, wherein said P-type hetero-material is one of nickel oxide, iridium oxide.
4. The heterojunction-based superjunction gallium oxide transistor of claim 2, wherein the filling method of the P-type hetero-material is one of an atomic layer deposition method, a vapor deposition method, a solid phase deposition method, a physical phase epitaxy method, and a physical deposition method.
5. The heterojunction-based superjunction gallium oxide transistor of claim 1, wherein said transistor is a horizontal structure gallium oxide transistor.
6. The heterojunction-based superjunction gallium oxide transistor according to claim 5, wherein the transistor comprises a gallium oxide substrate, a drain electrode, a source electrode, a gate electrode, and a protective layer, wherein the gallium oxide substrate has a homogenous or heterogeneous epitaxial conductive layer or a heterogeneous integrated conductive layer thereon, the drain electrode and the source electrode are disposed at two ends of the conductive layer, a middle region of the conductive layer is the gallium oxide drift region, a superjunction structure is formed on the gallium oxide drift region, the gate electrode is covered on the superjunction structure, and the protective layer is disposed above the gate electrode, the drain electrode, and the source electrode.
7. The method for manufacturing the heterojunction-based superjunction gallium oxide transistor according to any of claims 1 to 6, comprising the following steps:
(1) screening the substrate: adopting a gallium oxide substrate with a homogeneous or heterogeneous epitaxial conductive layer or a gallium oxide substrate with a heterogeneous integrated conductive layer;
(2) etching the table top: etching a required pattern on the gallium oxide conducting layer of the substrate to form a mesa pattern;
(3) constructing a source drain electrode: carrying out ohmic characteristic improvement treatment on the set source drain region, depositing metal and annealing to form ohmic contact;
(4) constructing a super junction structure: etching gallium oxide grooves which are arranged in parallel in a gallium oxide drift region, and then filling a P-type heterogeneous material in the gallium oxide grooves to form staggered gallium oxide-based heterogeneous PN junctions;
(5) constructing a grid: covering and constructing a grid on the super junction structure;
(6) constructing a protective layer: a protective layer is constructed over the gate, drain and source electrodes.
8. The method of manufacturing a heterojunction-based superjunction gallium oxide transistor of claim 7, wherein said gallium oxide substrate is one of an α -gallium oxide material, a β -gallium oxide material, a γ -gallium oxide material, a δ -gallium oxide material, and an ∈ -gallium oxide material.
9. The method of fabricating a heterojunction-based superjunction gallium oxide transistor according to claim 7, wherein the roughness RMS of the gallium oxide substrate is < 1 nm.
10. Use of a heterojunction-based superjunction gallium oxide transistor according to any of claims 1 to 6 in the field of electronic power.
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