CN214753771U - GaN-based HEMT chip with high conductive efficiency - Google Patents

Abstract

The utility model discloses a GaN-based HEMT chip with high conductive efficiency, which comprises a silicon-based substrate and an epitaxial layer, wherein the epitaxial layer comprises a GaN epitaxial layer and an AlGaN epitaxial layer, the surface of the GaN epitaxial layer is uniformly provided with grooves, the AlGaN epitaxial layer is fixedly connected in the grooves formed on the surface of the GaN epitaxial layer, and the GaN epitaxial layer is fixedly connected on the surface of the top end of the silicon-based substrate; the utility model discloses a method that adopts the epitaxial layer of GaN sculpture slot has realized unevenness's AlGaN/GaN epitaxial layer design, has increased AlGaN epitaxial layer and GaN epitaxial layer area of contact, has increased the two-dimentional electron gas tightness in the epitaxial layer, has improved the current density that the chip switched on, has improved the electrically conductive efficiency of GaN base HEMT chip; meanwhile, the design also increases the contact area of the AlGaN epitaxial layer and the GaN epitaxial layer, increases the two-dimensional electron gas area in the epitaxial layer, and can save part of the chip area and reduce the cost of the GaN-based HEMT chip under the consideration of the voltage endurance capability of the chip.

Description

GaN-based HEMT chip with high conductive efficiency

Technical Field

The utility model relates to a semiconductor device makes technical field, specifically is a high conduction efficiency's gaN base HEMT chip.

Background

Silicon power MOSFETs offer many advantages to circuit designers, making them an obvious choice for many applications. It provides high switching speed and low on-resistance, unlike previous bipolar transistors, MOSFETs are not subject to thermal runaway. Further advances in manufacturing technology have made it possible to use devices with multiple transistors in parallel in a vertical configuration, further reducing on-resistance.

Over the course of decades, manufacturers have developed improvements to the basic design, setting new standards for on-resistance and breakdown voltage. However, these parameters often require compromises with each other in the MOSFET design. Techniques that increase the breakdown voltage tend to push the on-resistance high. Accordingly, competing devices such as Insulated Gate Bipolar Transistors (IGBTs) have been developed whose applications require higher breakdown voltage ratings than MOSFETs.

One option is to replace the material. Gallium nitride (GaN) and silicon carbide are potential alternatives to silicon, which can support a large increase in breakdown voltage without affecting on-resistance due to the higher band gap of these materials. Both SiC and GaN have higher critical electric field strengths than silicon, giving them a superior relationship between on-resistance and breakdown voltage. This allows the device to be made smaller and the electrical terminals to be more closely tied together for a given breakdown voltage requirement.

AlGaN/GaN HEMTs are representative of GaN-based devices, and have high efficiency due to the characteristics of direct band gap and wide band gap (3.4eV), high thermal conductivity and high-temperature radiation resistance, and can be applied to severe environments. Because AlGaN/GaN HEMTs which are mainstream at present are all grown along a Ga surface, because the forbidden bandwidths of AlGaN and GaN materials are different, the forbidden bandwidth of AlGaN is higher than that of GaN, the conduction band bottoms of AlGaN and GaN have a band step difference, the band step difference of the conduction band and a large amount of positive charges at the interface analyzed above can bend the energy band at the conduction band bottom, and the energy band bending can form a two-dimensional potential well at the heterojunction interface. This two-dimensional potential well will confine the previously discussed polarization-induced electrons in the well in only two dimensions along a plane parallel to the abrupt junction interface, and is therefore referred to as a two-dimensional electron gas (2 DEG). Therefore, in the Al (Ga) N/GaN abrupt heterojunction structure, even if the AlGaN barrier layer is not doped at all, the surface density of the induced 2DEG can be as high as 2 x 1013cm < -2 > by virtue of the huge amount of polarized positive charges.

However, when the AlGaN/GaN HEMT device is subjected to a large gate voltage bias during operation, the energy band of the AlGaN barrier is pulled low, and the 2DEG at the heterojunction interface directly crosses the barrier and enters the AlGaN barrier layer to move through tunneling or thermal excitation.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a under the prerequisite of the same chip area, and taken into account the pressure resistance of chip, improved the GaN base HEMT chip of a high conduction efficiency that chip conduction efficiency can reduce the chip cost simultaneously.

In order to achieve the above object, the utility model provides a following technical scheme: a high conduction efficiency GaN-based HEMT chip, comprising:

a silicon-based substrate;

the epitaxial layer comprises a GaN epitaxial layer and an AlGaN epitaxial layer, grooves are uniformly formed in the surface of the GaN epitaxial layer, and the AlGaN epitaxial layer is fixedly connected in the grooves formed in the surface of the GaN epitaxial layer;

and the GaN epitaxial layer is fixedly connected to the top end surface of the silicon-based substrate.

Preferably, the AlGaN epitaxial layer surface is formed with a P-GaN Gate, a source contact and a drain contact by deposition, photolithography and other processes.

Preferably, the AlGaN epitaxial layer forms a source contact hole and a drain contact hole through the first metal layer and the second metal layer.

Preferably, the AlGaN epitaxial layer is formed by an isolation oxide layer through an implantation process.

Preferably, a first insulating layer is deposited on the P-GaN Gate, the source contact and the drain contact.

Preferably, the surface of the P-GaN Gate is fixedly connected with a Gate metal, and a second insulating layer is deposited on the surface of the Gate metal.

Preferably, a third insulating layer is deposited on the surface of the first metal layer, and a passivation layer is arranged on the surface of the second metal layer.

Preferably, the grooves are uniformly distributed on the surface of the GaN epitaxial layer.

Preferably, the depth of the groove on the surface of the GaN epitaxial layer is less than 20 nm.

A preparation method of a GaN-based HEMT chip with high conduction efficiency comprises the following steps:

s1, selecting a raw material silicon-based substrate as preparation;

s2, growing a GaN epitaxial layer on the silicon-based substrate, wherein the thickness of the GaN epitaxial layer is about 1-2um, and performing a first photoetching process on the surface of the GaN epitaxial layer to form uniform grooves;

s3, growing an AlGaN epitaxial layer on the surface of the GaN epitaxial layer, wherein uneven GaN epitaxial layer and AlGaN epitaxial layer designs are formed due to the grooves;

s4, depositing doped P-GaN on the AlGaN epitaxial layer and performing a second photoetching Process (PG) to form P-GaN Gate so as to form an E-mode GaN-based device;

s5, depositing Ohmic Contact metal on the AlGaN epitaxial layer and carrying out a third photoetching process (OC) to form a source Contact and a drain Contact;

s6, performing a fourth photoetching process (IS) on the AlGaN epitaxial layer, forming an isolation oxide layer through an injection process, and depositing a first insulating layer on the P-GaN Gate, the source contact and the drain contact as a unit cell isolation function;

s7, carrying out a fifth photoetching process (GS) on the first insulating layer to expose the P-GaN Gate so as to lead out the grid electrode;

s8, depositing metal on the surface of the chip, carrying out a sixth photoetching process (GT) at the position of the P-GaN Gate to form Gate metal, and leading out the Gate through the Gate metal;

s9, depositing a second insulating layer on the gate metal and performing a seventh photolithography process (V0) to expose the source contact and the drain contact;

s10, depositing a first metal layer on the surface of the chip, carrying out an eighth photoetching process (M1), and leading out the source contact and the drain contact through the first metal layer;

s11, depositing a third insulating layer on the surface of the chip and performing a ninth photolithography process (V1) to expose the first metal layer on the source and the drain;

s12, depositing a second metal layer on the surface of the chip, performing a tenth photoetching process (M2), and leading out the source metal and the drain metal;

and S13, depositing a passivation layer on the surface of the chip, performing a tenth photoetching process (TP), forming a chip front surface protection layer, and exposing the routing areas of the grid electrode, the source electrode and the drain electrode to obtain the GaN-based HEMT chip with high conduction efficiency.

Compared with the prior art, the beneficial effects of the utility model are that:

1. the utility model discloses under the prerequisite of same chip area, improved the current density that the core switched on, compromise under the pressure resistance of chip, improved the cost that the chip can reduce the chip simultaneously of chip conduction efficiency.

2. The utility model discloses an evenly set up the slot on gaN epitaxial layer surface, carry out ALGaN epitaxial layer growth again after the slot etching is accomplished, form unevenness's AlGaN/gaN epitaxial layer design, increased the two-dimensional electron gas tightness at AlGaN epitaxial layer and gaN epitaxial layer interface, improved the current density that the chip switched on, improved the electrically conductive efficiency of gaN base HEMT chip.

3. The utility model discloses an adopt the method of gaN epitaxial layer sculpture slot to realize unevenness's AlGaN/gaN epitaxial layer design, increased AlGaN epitaxial layer and gaN epitaxial layer area of contact, increased the two-dimentional electron gas area in the epitaxial layer, under the withstand voltage ability of having taken into account the chip, partial chip area can be saved in this design, has reduced the cost of gaN base HEMT chip.

Drawings

Fig. 1 is a schematic view of the overall structure of the present invention;

fig. 2 is a schematic view of a partial structure of the present invention.

In the figure: a 10-silicon based substrate; 20-GaN epitaxial layer; 21-isolation oxide layer; 22-a trench; a 30-AlGaN epitaxial layer; 31-source contact; 32-drain contact; 33-P-GaN Gate; 34-gate metal; 40-a first insulating layer; 50-a second insulating layer; 60-a first metal layer; 70-a third insulating layer; 80-a second metal layer; 90-a passivation layer; 91-source contact hole; 92-a drain contact hole.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Example 1:

referring to fig. 1-2, the present invention provides a technical solution: a high conduction efficiency GaN-based HEMT chip, comprising: a silicon-based substrate 10 and an epitaxial layer.

The epitaxial layer comprises a GaN epitaxial layer 20 and an AlGaN epitaxial layer 30, grooves 22 are uniformly formed in the surface of the GaN epitaxial layer 20, and the AlGaN epitaxial layer 30 is fixedly connected to the grooves 22 formed in the surface of the GaN epitaxial layer 20.

In this embodiment, specifically, the trenches 22 are uniformly distributed on the surface of the GaN epitaxial layer 20.

In this embodiment, specifically, the depth of the trench 22 on the surface of the GaN epitaxial layer 20 is less than 20 nm.

Furthermore, the GaN epitaxial layer 20 adopts the groove 22 design to increase the two-dimensional electron gas density of the AlGaN/GaN interface, improve the current density of the chip conduction, and improve the conduction efficiency of the GaN-based HEMT chip; meanwhile, the design also increases the contact area of the AlGaN epitaxial layer and the GaN epitaxial layer, increases the two-dimensional electron gas area in the epitaxial layer, and can save part of the chip area and reduce the cost of the GaN-based HEMT chip under the consideration of the voltage endurance capability of the chip.

Wherein, the GaN epitaxial layer 20 is fixedly connected to the top surface of the silicon-based substrate 10.

The AlGaN epitaxial layer 30 is formed with a P-GaN Gate33, a source contact 31, and a drain contact 32 by deposition, photolithography, and other processes.

Further, the grooves 22 are uniformly formed in the whole surface of the GaN epitaxial layer 20, and it can be seen that the GaN epitaxial layer 20, the AlGaN epitaxial layer 30, the P-GaN Gate33, the source contact 31 and the drain contact 32 are all designed to be the uniform grooves 22, so that the two-dimensional electron gas density between the GaN epitaxial layer 20 and the AlGaN epitaxial layer 30 is increased, the on-current density is improved, and the conduction efficiency of the E-mode GaN-based HEMT chip is improved while the Gate control speed and the source and drain conduction speeds are ensured.

Wherein the AlGaN epitaxial layer 30 forms a source contact hole 91 and a drain contact hole 92 through the first metal layer 60 and the second metal layer 80.

Wherein, the AlGaN epitaxial layer 30 forms an isolation oxide layer 21 through an implantation process.

Wherein a first insulating layer 40 is deposited on the P-GaN Gate33, the source contact 31 and the drain contact 32.

The surface of the P-GaN Gate33 is fixedly connected with a Gate metal 34, and a second insulating layer 50 is deposited on the surface of the Gate metal 34.

Wherein, a third insulating layer 70 is deposited on the surface of the first metal layer 60, and a passivation layer 90 is disposed on the surface of the second metal layer 80.

According to the embodiment, the grooves are uniformly formed in the surface of the GaN epitaxial layer, the growth of the ALGaN epitaxial layer is carried out after the grooves are etched, the uneven AlGaN/GaN epitaxial layer design is formed, the two-dimensional electron gas density of the interface of the AlGaN epitaxial layer and the GaN epitaxial layer is increased, the current density of the conduction of the chip is improved, and the conduction efficiency of the GaN-based HEMT chip is improved; meanwhile, the contact area of the AlGaN epitaxial layer and the GaN epitaxial layer is increased, the two-dimensional electron gas area in the epitaxial layer is increased, part of the area of the chip can be saved by the design under the condition of considering the voltage endurance capability of the chip, and the cost of the GaN-based HEMT chip can be reduced.

The flow sheet process steps of the embodiment:

referring to fig. 1-2, the present invention provides a technical solution: a preparation method of a GaN-based HEMT chip with high conduction efficiency comprises the following steps:

s1, selecting the raw material silicon-based substrate 10 as preparation;

s2, growing a GaN epitaxial layer 20 on the silicon-based substrate 10, wherein the thickness of the GaN epitaxial layer 20 is about 1-2um, and performing a first photoetching process on the surface of the GaN epitaxial layer 20 to form uniform grooves 22;

s3, growing the AlGaN epitaxial layer 30 on the surface of the GaN epitaxial layer 20, wherein the uneven GaN epitaxial layer 20 and the AlGaN epitaxial layer 30 are designed due to the grooves 22;

s4, depositing doped P-GaN on the AlGaN epitaxial layer 30, and performing a second photoetching Process (PG) to form P-GaN Gate33 to form an E-mode GaN-based device;

s5, depositing Ohmic Contact metal on the AlGaN epitaxial layer 30 and performing a third photolithography process (OC) to form a source Contact 31 and a drain Contact 32;

s6, performing a fourth photolithography process (IS) on the AlGaN epitaxial layer 30, forming an isolation oxide layer 21 through an implantation process, and depositing a first insulating layer 40 on the P-GaN Gate33, the source contact 31 and the drain contact 32 as a unit cell isolation function;

s7, carrying out a fifth photoetching process (GS) on the first insulating layer 40 to expose the P-GaN Gate33 so as to lead out the Gate;

s8, depositing metal on the surface of the chip, carrying out a sixth photoetching process (GT) at the position of the P-GaN Gate33 to form a Gate metal 34, and leading out the Gate through the Gate metal 34;

s9, depositing the second insulating layer 50 on the gate metal 34 and performing a seventh photolithography process (V0) to expose the source contact 31 and the drain contact 32;

s10, depositing the first metal layer 60 on the chip surface and performing an eighth photolithography process (M1), and drawing the source contact 31 and the drain contact 32 through the first metal layer 60;

s11, depositing a third insulating layer 70 on the chip surface and performing a ninth photolithography process (V1) to expose the first metal layer 60 on the source and drain;

s12, depositing a second metal layer 80 on the surface of the chip, performing a tenth photoetching process (M2), and leading out the source metal and the drain metal;

and S13, depositing a passivation layer 90 on the surface of the chip, performing a tenth photoetching process (TP), forming a chip front surface protection layer, and exposing routing areas of the grid electrode, the source electrode and the drain electrode to obtain the GaN-based HEMT chip with high conduction efficiency.

The utility model discloses use P-gaN te's E-mode gaN base HEMT device structure to explain the utility model's design as the legend, but the E-mode gaN base HEMT device structure of other designs is also suitable for, for example the E-mode gaN base HEMT device of ditch slot Gate design also is suitable for to other D-mode gaN base HEMT device structures are also suitable for equally.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

The above only is the embodiment of the present invention, not limiting the patent scope of the present invention, all the equivalent structures or equivalent processes that are used in the specification and the attached drawings or directly or indirectly applied to other related technical fields are included in the patent protection scope of the present invention.

Claims (9)

1. A GaN-based HEMT chip with high conduction efficiency, comprising:

a silicon-based substrate (10);

the GaN epitaxial layer comprises a GaN epitaxial layer (20) and an AlGaN epitaxial layer (30), grooves (22) are uniformly formed in the surface of the GaN epitaxial layer (20), and the AlGaN epitaxial layer (30) is fixedly connected to the grooves (22) formed in the surface of the GaN epitaxial layer (20);

the GaN epitaxial layer (20) is fixedly connected to the top end surface of the silicon-based substrate (10).

2. The high conduction efficiency GaN-based HEMT chip according to claim 1, wherein: and forming a P-GaN Gate (33), a source contact (31) and a drain contact (32) on the surface of the AlGaN epitaxial layer (30) by processes such as deposition, photoetching and the like.

3. The high conduction efficiency GaN-based HEMT chip according to claim 1, wherein: the AlGaN epitaxial layer (30) forms a source contact hole (91) and a drain contact hole (92) through a first metal layer (60) and a second metal layer (80).

4. The high conduction efficiency GaN-based HEMT chip according to claim 1, wherein: the AlGaN epitaxial layer (30) forms an isolation oxide layer (21) through an implantation process.

5. The high conduction efficiency GaN-based HEMT chip according to claim 2, wherein: a first insulating layer (40) is deposited over the P-GaN Gate (33), source contact (31), and drain contact (32).

6. The high conduction efficiency GaN-based HEMT chip according to claim 2, wherein: the surface of the P-GaN Gate (33) is fixedly connected with a Gate metal (34), and a second insulating layer (50) is deposited on the surface of the Gate metal (34).

7. The high conduction efficiency GaN-based HEMT chip according to claim 3, wherein: and a third insulating layer (70) is deposited on the surface of the first metal layer (60), and a passivation layer (90) is arranged on the surface of the second metal layer (80).

8. The high conduction efficiency GaN-based HEMT chip according to claim 1, wherein: the grooves (22) are uniformly distributed on the surface of the GaN epitaxial layer (20).

9. The high conduction efficiency GaN-based HEMT chip according to claim 1, wherein: the depth of the groove (22) on the surface of the GaN epitaxial layer (20) is less than 20 nm.

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