CN114171588A - 双向导通槽栅功率mos器件结构及制造方法 - Google Patents

双向导通槽栅功率mos器件结构及制造方法 Download PDF

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CN114171588A
CN114171588A CN202111473730.XA CN202111473730A CN114171588A CN 114171588 A CN114171588 A CN 114171588A CN 202111473730 A CN202111473730 A CN 202111473730A CN 114171588 A CN114171588 A CN 114171588A
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conductive type
groove
doped region
lightly doped
heavily doped
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CN114171588B (zh
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乔明
陈勇
刘文良
方冬
张发备
张波
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University of Electronic Science and Technology of China
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Abstract

本发明提供一种双向导通槽栅功率MOS器件结构及其制造方法，在硅片表面形成栅极、源极和漏极，实现双向导通双向耐压的功率MOS器件，可用于锂电池BMS防护等应用环境下。相比于传统BMS中采用双管串联的方式以及其他实现双向导通的结构，本发明提出的器件结构具有以下优点：第一，本发明提出的器件仅需要占据传统方式一半甚至更小的面积，极大地提高了集成度；第二，本发明所提出的器件结构制造工艺简单且制造成本也不高，降低了工艺制造上的问题；第三，本发明所提出的器件结构漏极和源极可以对换，实现上真正意义上的对称结构和双向导通双向耐压；第四，本发明所提出的器件结构由于漏极、源极和栅极均在硅片表面，因此易于集成，增加了应用环境。

Description

双向导通槽栅功率MOS器件结构及制造方法
技术领域
本发明属于半导体功率器件技术领域，主要涉及一种双向功率半导体器件及其制造方法。
背景技术
功率MOS器件具有集成度高、导通电阻低、开关速度快、开关损耗小的特点，广泛应用于各类电源管理及开关转换，有着广阔的发展和应用前景。然而传统功率MOS器件的漏源非对称结构导致的功率MOS器件单向耐压、单向导电的特性限制了功率MOS器件的应用。
在一些低功耗DC-DC转换器IC、锂离子电池充放电等需要双向耐压，双向导电的应用环境下，由于没有单一的器件可以作为双向自换向开关，因此双向开关(BDS)是由常用的固态器件组合而成的。为了建立一个具有双向导通能力的复合BDS，有必要将两个分立器件反串联，即两个单向电压器件或反并联，即两个单向电流器件，如图1所示；其应用在锂离子充放电环境中的等效电路如图2所示。然而，这种方案一方面需要两个大面积的功率MOS器件，增加了成本，降低了系统集成度；另一方面，两个功率MOS器件串联也极大地增大了电路的导通电阻，增大了电路损耗等问题。另一种可能性是通过对传统的纵向和横向器件结构进行创新，如图3、4、5所示。图3所示单槽双栅功率MOS结构其实和传统的双MOS导通结构差别不大，只是通过在单槽内引入两个栅极来减小元胞的尺寸，然而对工艺制造提出了较高的要求。而图4所示的纵向的沟槽栅功率MOS器件结构则是通过在纵向上引入双耐压pn结，其制造成本和工艺难度也不低。图5所示的横向的平面栅功率MOS器件结构则因为其大尺寸等造成的导通电阻较大，影响其在双向导通功率开关的应用。
发明内容
为解决上述问题，本发明提供了一种双向导通槽栅功率MOS器件结构及其制造方法，通过本发明提出的双向导通的功率MOS结构，在单个功率MOS管面积下，实现了源漏极可互换的双向导通双向耐压的要求。
为实现上述发明目的，本发明技术方案如下：
一种双向导通槽栅功率MOS器件结构，包括：
第二导电类型重掺杂衬底20，位于第二导电类型重掺杂衬底20上的第二导电类型轻掺杂外延层21，位于第二导电类型轻掺杂外延层21上的槽，位于槽内部的第一栅极多晶硅11，其中栅氧化层03被夹在第一栅极多晶硅11和所述槽之间，其厚度由栅极工作电位决定；第一导电类型轻掺杂区32位于所述槽两侧，其中第一导电类型轻掺杂区32底部低于所述槽的底部；第一导电类型重掺杂区31位于第一导电类型轻掺杂区32表面；第一导电类型重掺杂区31表面为介质层01，介质层01上方引出源极51和漏极61。
作为优选方式，所述槽底部注入推结形成第二导电类型沟调区23。
作为优选方式，所述槽内部的第一栅极多晶硅11上方设有分离栅极多晶硅13。
作为优选方式，第一导电类型轻掺杂区32内部设有第二导电类型掺杂区22，第二导电类型掺杂区22在第一导电类型轻掺杂区32内部左侧、中部或右侧。
作为优选方式，第二导电类型重掺杂衬底20和第二导电类型外延层21之间设有埋氧层77。
作为优选方式，槽内部的第一栅极多晶硅11为阶梯型、或者漏斗型、或U型，或降低表面场阶梯氧化物RSO型结构。
作为优选方式，所述源极和漏极进行互换。
作为优选方式，当所述结构为N型沟道时，第一导电类型为n型掺杂，第二导电类型为p型掺杂；当所述结构为P型沟道时，第一导电类型为p型掺杂，第二导电类型为n型掺杂；
并且/或者重掺杂的掺杂浓度大于1E19，轻掺杂的掺杂浓度低于1E18。
本发明还提供一种双向导通槽栅功率MOS器件的制造方法，包括以下步骤：
步骤1，选择第二导电类型重掺杂衬底20；
步骤2，在第二导电类型重掺杂衬底20表面外延生长第二导电类型外延层21；
步骤3，在第二导电类型外延层21表面光刻、刻蚀形成U形槽，并在槽内形成栅氧化层03和第一栅极多晶硅11；
步骤4，通过一次或多次第一导电类型杂质离子注入，在第二导电类型外延层21表面形成第一导电类型轻掺杂区32，所述第一导电类型轻掺杂区32底部低于所述槽的底部。
步骤5，通过一次或多次第一导电类型杂质离子注入，在第一导电类型轻掺杂区32表面形成第一导电类型重掺杂区31，所述第一导电类型重掺杂区31底部低于第一栅极多晶硅11顶部；
步骤6，通过淀积、光刻、刻蚀工艺形成介质层01和接触孔，表面金属化，通过光刻刻蚀工艺，形成表面金属接触层，构成源极51和漏极61。
本发明还提供第二种双向导通槽栅功率MOS器件结构的制造方法，包括以下步骤：
步骤1，选择第二导电类型重掺杂衬底20；
步骤2，在第二导电类型重掺杂衬底20表面通过外延生长第二导电类型外延层21；
步骤3，在第二导电类型外延层21表面光刻、刻蚀形成U形槽，并在槽内形成牺牲氧化层；
步骤4，通过一次或者多次的第二导电类型杂质离子注入向槽底沟道区注入，形成第二导电类型沟调区23，然后进行牺牲氧刻蚀；
步骤5，在槽内形成栅氧化层03，然后向深槽内淀积多晶硅，形成第一栅极多晶硅11；
步骤6，通过一次或多次第一导电类型杂质离子注入，在第二导电类型外延层21表面形成第一导电类型轻掺杂区32，所述第一导电类型轻掺杂区32底部低于所述槽的底部；
步骤7，通过一次或多次第一导电类型杂质离子注入，在第一导电类型轻掺杂区32表面形成第一导电类型重掺杂区31，所述第一导电类型重掺杂区31底部低于第一栅极多晶硅11顶部；
步骤8，通过淀积、光刻、刻蚀工艺形成介质层01和接触孔，表面金属化，通过光刻刻蚀工艺，形成表面金属接触层，构成源极51和漏极61。
本发明的有益效果为：本发明提供一种双向导通槽栅功率MOS器件结构及其制造方法，在硅片表面形成栅极、源极和漏极，实现双向导通双向耐压的功率MOS器件，可用于锂电池BMS防护等应用环境下。相比于传统BMS中采用双管串联的方式以及其他实现双向导通的结构，本发明所提出的器件结构具有以下优点：第一，本发明所提出的器件仅需要占据传统方式一半甚至更小的面积，极大地提高了集成度；第二，本发明所提出的器件结构制造工艺简单且制造成本也不高，降低了工艺制造上的问题；第三，本发明所提出的器件结构漏极和源极可以对换，实现上真正意义上的对称结构和双向导通双向耐压；第四，本发明所提出的器件结构由于漏极、源极和栅极均在硅片表面，因此易于集成，增加了应用环境。
附图说明
图1为传统的漏极短接MOS导通器件结构示意图。
图2为传统的漏极短接MOS等效电路图。
图3为单槽双栅功率MOS器件结构示意图。
图4为纵向的沟槽栅功率MOS器件结构示意图。
图5为横向的平面栅功率MOS器件结构示意图。
图6为本发明实施例1提出的双向导通槽栅功率MOS器件结构示意图。
图7为本发明实施例2提出的双向导通槽栅功率MOS器件结构示意图。
图8为本发明实施例3提出的双向导通槽栅功率MOS器件结构示意图。
图9为本发明实施例4提出的双向导通槽栅功率MOS器件结构示意图。
图10为实施例5对应的双向导通槽栅功率MOS器件结构示意图。其中(a)、(b)、(c)分别为第二导电类型掺杂区22在第一导电类型轻掺杂区32内部的右侧、中部、左侧。
图11为实施例6对应的双向导通槽栅功率MOS器件结构示意图。
图12为实施例7对应的双向导通槽栅功率MOS器件结构示意图。
图13为实施例8对应的双向导通槽栅功率MOS器件结构示意图。
图14为实施例9对应的双向导通槽栅功率MOS器件结构示意图。
图15为实施例10对应的双向导通槽栅功率MOS器件结构示意图。
图16为实施例11对应的双向导通槽栅功率MOS器件结构示意图。
图17为实施例1对应的制造方法工艺流程图。
图18为实施例2对应的制造方法工艺流程图。
图19为实施例5对应的制造方法工艺流程图。
图20为实施例9对应的制造方法工艺流程图。
图21为实施例1对应的双向耐压的I-V仿真曲线。
附图中，各标号所代表的部件列表如下：
01为介质层，03为栅氧化层，11为第一栅极多晶硅，12为第二栅极多晶硅，13为分离栅极多晶硅，20为第二导电类型重掺杂衬底，21为第二导电类型外延层，22为第二导电类型掺杂区，23为第二导电类型沟调区，24为第二导电类型重掺杂区，30为第一导电类型重掺杂衬底，31为第一导电类型重掺杂区，32为第一导电类型轻掺杂区，33为第一导电类型掺杂区，51为源极，61为漏极，77为埋氧层。
具体实施方式
以下结合附图对本发明的原理和特征进行描述，所举实例只用于解释本发明，并非用于限定本发明的范围。
实施例1
如图6所示，本实施例提供一种双向导通槽栅功率MOS器件结构，包括：
第二导电类型重掺杂衬底20，位于第二导电类型重掺杂衬底20上的第二导电类型轻掺杂外延层21，位于第二导电类型轻掺杂外延层21上的槽，位于槽内部的第一栅极多晶硅11，其中栅氧化层03被夹在第一栅极多晶硅11和所述槽之间，其厚度由栅极工作电位决定；第一导电类型轻掺杂区32位于所述槽两侧，其中第一导电类型轻掺杂区32底部低于所述槽的底部；第一导电类型重掺杂区31位于第一导电类型轻掺杂区32表面；第一导电类型重掺杂区31表面为介质层01，介质层01上方引出源极51和漏极61。
本实施例还提供一种上述双向导通槽栅功率MOS器件结构的制造方法，如图17所示。
包括以下步骤：
步骤1，选择第二导电类型重掺杂衬底20；
步骤2，在第二导电类型重掺杂衬底20表面外延生长第二导电类型外延层21；
步骤3，在第二导电类型外延层21表面光刻、刻蚀形成U形槽，如图17中(a)，并在槽内形成栅氧化层03和第一栅极多晶硅11；
步骤4，通过一次或多次第一导电类型杂质离子注入，在第二导电类型外延层21表面形成第一导电类型轻掺杂区32，所述第一导电类型轻掺杂区32底部低于所述槽的底部，如图17中(b)；
步骤5，通过一次或多次第一导电类型杂质离子注入，在第一导电类型轻掺杂区32表面形成如图17中(c)的第一导电类型重掺杂区31，所述第一导电类型重掺杂区31底部低于第一栅极多晶硅11顶部；
步骤6，通过淀积、光刻、刻蚀工艺形成如图17中(c)的介质层01和接触孔，表面金属化，通过光刻刻蚀工艺，形成表面金属接触层，构成源极51和漏极61，如图17中(d)。
在本发明提出的一种双向导通槽栅功率MOS器件结构中，漏极和源极均在表面且可互换，当栅极不加电位时，MOS管沟道关闭时，无论哪个电极加高电位，都可以通过外延层的耗尽来承受高压，从而实现双向耐压的目的，如图21仿真曲线所示；当两个MOS管沟道开启时，电流方向将随电压方向而改变，从而实现双向电流导通的目的。同时该器件结构工艺制造成本和难度均不大；并且仅需要占据传统方式一半甚至更小的面积，极大地提高了集成度；该结构由于特殊性减小了传统意义上的漂移区电阻，减小了整体的导通电阻；再者源、漏和栅极均在表面，因此是可以用于集成的应用环境下。
实施例2
如图7所示，本实施例提供一种双向导通槽栅功率MOS器件结构，本实施例和实施例1的区别在于：所述槽底部注入推结形成第二导电类型沟调区23，其一次或多次注入能量大小可以不同以形成不同的结深，有效的对阈值进行调整，并防止了沟道区发生穿通的发生。
如图18所示，本实施例还提供一种上述双向导通槽栅功率MOS器件结构的制造方法，包括以下步骤：
步骤1，选择第二导电类型重掺杂衬底20；
步骤2，在第二导电类型重掺杂衬底20表面通过外延生长第二导电类型外延层21；
步骤3，在第二导电类型外延层21表面光刻、刻蚀形成U形槽，如图18中(a)，并在槽内形成牺牲氧化层，如图18中(b)；
步骤4，通过一次或者多次的第二导电类型杂质离子注入向槽底沟道区注入，形成第二导电类型沟调区23，然后进行牺牲氧刻蚀；
步骤5，在槽内形成栅氧化层03，然后向槽内淀积多晶硅，形成第一栅极多晶硅11；如图18中(c)；
步骤6，通过一次或多次第一导电类型杂质离子注入，在第二导电类型外延层21表面形成第一导电类型轻掺杂区32，所述第一导电类型轻掺杂区32底部低于所述槽的底部；
步骤7，通过一次或多次第一导电类型杂质离子注入，在第一导电类型轻掺杂区32表面形成如图18中(d)的第一导电类型重掺杂区31，所述第一导电类型重掺杂区31底部低于第一栅极多晶硅11顶部；
步骤8，通过淀积、光刻、刻蚀工艺形成如图18中(d)的介质层01和接触孔，表面金属化，通过光刻刻蚀工艺，形成表面金属接触层，构成源极51和漏极61。如图18中(e)。
实施例3
如图8所示，本实施例提供一种双向导通槽栅功率MOS器件结构，本实施例和实施例1的区别在于：所述槽内部的第一栅极多晶硅11上方设有分离栅极多晶硅13。
分离栅结构可作为体内场板的辅助耗尽作用，可进一步提高该器件结构的耐压和进一步的改善整体的导通电阻。
实施例4
如图9所示的双向导通槽栅功率MOS器件结构，本实施例和实施例1的区别在于：在第二导电类型轻掺杂外延层21引入第一导电类型掺杂区33，第一导电类型掺杂区33在第二导电类型轻掺杂外延层21两侧，可以在同等电压等级下更进一步的降低器件的导通电阻，能够降低器件的开关损耗。
实施例5
如图10所示的双向导通槽栅功率MOS器件结构，本实施例和实施例1的区别在于：第一导电类型轻掺杂区32内部设有第二导电类型掺杂区22，第二导电类型掺杂区22在第一导电类型轻掺杂区32内部左侧、中部或右侧，图10中(a)、(b)、(c)分别为第二导电类型掺杂区22在第一导电类型轻掺杂区32内部的右侧、中部、左侧。
如图19所示，本实施例还提供一种上述双向导通槽栅功率MOS器件结构的制造方法，包括以下步骤：
步骤1，选择第二导电类型重掺杂衬底20；
步骤2，在第二导电类型重掺杂衬底20表面通过外延生长第二导电类型轻掺杂外延层21；
步骤3，在第二导电类型轻掺杂外延层21表面光刻、刻蚀形成U形槽，如图19中(a)，并在槽内形成栅氧化层03和第一栅极多晶硅11，如图19中(b)；
步骤4，通过一次或多次第一导电类型杂质离子注入，在第二导电类型外延层21表面形成第一导电类型轻掺杂区32，所述第一导电类型轻掺杂区32底部低于槽的底部；
步骤5，通过第二导电类型杂质离子注入，在第一导电类型轻掺杂区32内形成第二导电类型掺杂区22，如图19中(c)；
步骤6，通过一次或多次第一导电类型杂质离子注入，在第一导电类型轻掺杂区32和第二导电类型掺杂区22表面形成如图19中(d)的第一导电类型重掺杂区31，所述第一导电类型重掺杂区31底部低于栅极多晶硅11顶部；
步骤8，通过淀积、光刻、刻蚀工艺形成如图19中(d)的介质层01和接触孔，表面金属化，通过光刻刻蚀工艺，形成表面金属接触层，构成源极51和漏极61，如图19中(e)。
第二导电类型掺杂区22的引入可以在同等电压等级下更进一步的降低器件的导通电阻，能够降低器件的开关损耗；该结构和图9结构不同之处在于第二导电类型外延层21和第一导电类型轻掺杂区32的浓度不一样，即器件参与主要耐压的区域不同，导致我们引入电荷补偿的区域不同；此外图10中(a)(b)(c)三种情况的区别为引入的第二导电类型轻掺杂的超结条的位置，不同的位置对第一导电类型的辅助耗尽起到不同的效果。
实施例6
如图11所示，本实施例提供一种双向导通槽栅功率MOS器件结构，本实施例和实施例1的区别在于：槽内部的第一栅极多晶硅11为阶梯型，这是出于本发明提出的结构反型沟道位置特殊以及对氧化层厚度和辅助耗尽的考虑。
实施例7
如图12所示，本实施例提供一种双向导通槽栅功率MOS器件结构，本实施例和实施例1的区别在于：槽内部的第一栅极多晶硅11为漏斗型，即靠近槽底处的多晶硅宽于其上方多晶硅；这是由于本发明提出的结构反型沟道位置和特殊的应用条件所提出。
实施例8
如图13所示，本实施例提供一种双向导通槽栅功率MOS器件结构，本实施例和实施例1的区别在于：槽内部的第一栅极多晶硅11为U型；且源极和漏极直接引出，增大了接触面积进而减小了接触电阻。
实施例9
如图14所示，本实施例提供一种双向导通槽栅功率MOS器件结构，本实施例和实施例1的区别在于：槽内部的第一栅极多晶硅11为降低表面场阶梯氧化物RSO(RESURFStepped Oxide)型结构；且源极和漏极直接引出，增大了接触面积进而减小了接触电阻。
如图20所示，本实施例还提供一种上述双向导通槽栅功率MOS器件结构的制造方法，包括以下步骤：
步骤1，选择第二导电类型重掺杂衬底20；
步骤2，在第二导电类型重掺杂衬底20表面通过外延生长第二导电类型轻掺杂外延层21；
步骤3，在第二导电类型轻掺杂外延层21表面光刻、刻蚀形成U形槽，并在槽内形成栅氧化层03；
步骤4，淀积多晶硅并进行回刻，同时对槽侧壁氧化层进行回刻；如图20中(a)；
步骤5，在槽内进行氧化层的生长，并淀积多晶硅形成一次阶梯第一栅极多晶硅11；
步骤6，通过一次或多次第一导电类型杂质离子注入，在第二导电类型外延层21表面形成第一导电类型轻掺杂区32，如图20中(b)，所述第一导电类型轻掺杂区32底部低于深槽的底部；
步骤7，通过一次或多次第一导电类型杂质离子注入，在第一导电类型轻掺杂区32表面形成如图20中(c)的第一导电类型重掺杂区31，所述第一导电类型重掺杂区31底部低于第一栅极多晶硅11顶部；
步骤8，通过淀积、光刻、刻蚀工艺形成如图20中(c)的介质层01和接触孔，表面金属化，通过光刻刻蚀工艺，形成表面金属接触层，构成源极51和漏极61，如图20中(d)。
实施例10
如图15所示，本实施例提供一种双向导通槽栅功率MOS器件结构，本实施例和实施例1的区别在于：第二导电类型重掺杂衬底20和第二导电类型外延层21之间设有埋氧层77。引入的埋氧层可以避免对衬底电位的考虑，衬底也可以换成第一导电类型重掺杂。
实施例11
如图16所示，本实施例提供一种双向导通槽栅功率MOS器件结构，本实施例和实施例4的区别在于：第二导电类型重掺杂衬底20和第二导电类型外延层21之间设有埋氧层77。引入的埋氧层，可以避免对衬底电位的考虑，故衬底可以换成第一导电类型重掺杂；并且由于超结结构的引入可以在同等电压等级下更进一步的降低器件的导通电阻。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

1.一种双向导通槽栅功率MOS器件结构，其特征在于包括：
第二导电类型重掺杂衬底(20)，位于第二导电类型重掺杂衬底(20)上的第二导电类型轻掺杂外延层(21)，位于第二导电类型轻掺杂外延层(21)上的槽，位于槽内部的第一栅极多晶硅(11)，其中栅氧化层(03)被夹在第一栅极多晶硅(11)和所述槽之间，其厚度由栅极工作电位决定；第一导电类型轻掺杂区(32)位于所述槽两侧，其中第一导电类型轻掺杂区(32)底部低于所述槽的底部；第一导电类型重掺杂区(31)位于第一导电类型轻掺杂区(32)表面；第一导电类型重掺杂区(31)表面为介质层(01)，介质层(01)上方引出源极(51)和漏极(61)。
2.权利要求1所述的一种双向导通槽栅功率MOS器件结构，其特征在于：所述槽底部注入推结形成第二导电类型沟调区(23)。
3.根据权利要求1所述的一种双向导通槽栅功率MOS器件结构，其特征在于：所述槽内部的第一栅极多晶硅(11)上方设有分离栅极多晶硅(13)。
4.根据权利要求1所述的一种双向导通槽栅功率MOS器件结构，其特征在于：第一导电类型轻掺杂区(32)内部设有第二导电类型掺杂区(22)，第二导电类型掺杂区(22)在第一导电类型轻掺杂区(32)内部左侧、中部或右侧。
5.根据权利要求1所述的一种双向导通槽栅功率MOS器件结构，其特征在于：第二导电类型重掺杂衬底(20)和第二导电类型外延层(21)之间设有埋氧层(77)。
6.根据权利要求1所述的一种双向导通槽栅功率MOS器件结构，其特征在于：槽内部的第一栅极多晶硅(11)为阶梯型、或者漏斗型、或U型，或降低表面场阶梯氧化物RSO型结构。
7.根据权利要求1至6任意一项所述的一种双向导通槽栅功率MOS器件结构，其特征在于：所述源极和漏极进行互换。
8.根据权利要求1至6任意一项所述的一种双向导通槽栅功率MOS器件结构，其特征在于：当所述结构为N型沟道时，第一导电类型为n型掺杂，第二导电类型为p型掺杂；当所述结构为P型沟道时，第一导电类型为p型掺杂，第二导电类型为n型掺杂；
并且/或者重掺杂的掺杂浓度大于1E19，轻掺杂的掺杂浓度低于1E18。
9.权利要求1所述的一种双向导通槽栅功率MOS器件结构的制造方法，其特征在于包括以下步骤：
步骤1，选择第二导电类型重掺杂衬底(20)；
步骤2，在第二导电类型重掺杂衬底(20)表面外延生长第二导电类型外延层(21)；
步骤3，在第二导电类型外延层(21)表面光刻、刻蚀形成U形槽，并在槽内形成栅氧化层(03)和第一栅极多晶硅(11)；
步骤4，通过一次或多次第一导电类型杂质离子注入，在第二导电类型外延层(21)表面形成第一导电类型轻掺杂区(32)，所述第一导电类型轻掺杂区(32)底部低于所述槽的底部。
步骤5，通过一次或多次第一导电类型杂质离子注入，在第一导电类型轻掺杂区(32)表面形成第一导电类型重掺杂区(31)，所述第一导电类型重掺杂区(31)底部低于第一栅极多晶硅(11)顶部；
步骤6，通过淀积、光刻、刻蚀工艺形成介质层(01)和接触孔，表面金属化，通过光刻刻蚀工艺，形成表面金属接触层，构成源极(51)和漏极(61)。
10.权利要求2所述的一种双向导通槽栅功率MOS器件结构的制造方法，其特征在于包括以下步骤：
步骤1，选择第二导电类型重掺杂衬底(20)；
步骤2，在第二导电类型重掺杂衬底(20)表面通过外延生长第二导电类型外延层(21)；
步骤3，在第二导电类型外延层(21)表面光刻、刻蚀形成U形槽，并在槽内形成牺牲氧化层；
步骤4，通过一次或者多次的第二导电类型杂质离子注入向槽底沟道区注入，形成第二导电类型沟调区(23)，然后进行牺牲氧刻蚀；
步骤5，在槽内形成栅氧化层(03)，然后向槽内淀积多晶硅，形成第一栅极多晶硅(11)；
步骤6，通过一次或多次第一导电类型杂质离子注入，在第二导电类型外延层(21)表面形成第一导电类型轻掺杂区(32)，所述第一导电类型轻掺杂区(32)底部低于所述槽的底部；
步骤7，通过一次或多次第一导电类型杂质离子注入，在第一导电类型轻掺杂区(32)表面形成第一导电类型重掺杂区(31)，所述第一导电类型重掺杂区(31)底部低于第一栅极多晶硅(11)顶部；
步骤8，通过淀积、光刻、刻蚀工艺形成介质层(01)和接触孔，表面金属化，通过光刻刻蚀工艺，形成表面金属接触层，构成源极(51)和漏极(61)。
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