CN114171504A - 硅裸片的笔直导线接合 - Google Patents
硅裸片的笔直导线接合 Download PDFInfo
- Publication number
- CN114171504A CN114171504A CN202110531569.0A CN202110531569A CN114171504A CN 114171504 A CN114171504 A CN 114171504A CN 202110531569 A CN202110531569 A CN 202110531569A CN 114171504 A CN114171504 A CN 114171504A
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- Prior art keywords
- connection pads
- die
- solder
- silicon
- dies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 130
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 130
- 239000010703 silicon Substances 0.000 title claims abstract description 130
- 229910000679 solder Inorganic materials 0.000 claims abstract description 82
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052741 iridium Inorganic materials 0.000 claims description 4
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 230000004907 flux Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 239000007921 spray Substances 0.000 claims 1
- 230000008569 process Effects 0.000 description 30
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 230000005484 gravity Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010285 flame spraying Methods 0.000 description 2
- 238000004093 laser heating Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 230000003647 oxidation Effects 0.000 description 1
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- 125000006850 spacer group Chemical group 0.000 description 1
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Abstract
本发明公开了一种方法,其包含堆叠数个硅裸片,使得所述裸片的一个或多个边缘竖直对齐,其中所述一个或多个边缘包含数个连接垫。所述方法还包含在大体上垂直于所述一个或多个边缘的轴线上定位连接导线。所述连接导线包含在其上形成的数个焊料块。所述焊料块以与所述裸片上的第一组经对齐连接垫之间的距离相关联的间隔隔开。所述连接导线定位成使得所述焊料块与所述第一组经对齐连接垫接触。所述方法还包含施加热以使所述焊料块回流并将所述连接导线物理地和电气地耦合到所述连接垫。
Description
相关申请的交叉引用
本申请要求2020年9月11提交的第63/077,069号美国临时专利申请的优先权和权益,此申请的全部内容以引用的方式并入本文中。
背景技术
本申请大体上涉及在硅裸片之间提供电气连接,且更确切地说,涉及沿着竖直边缘电气地连接硅裸片。
在某些硅裸片结构中,连接垫放在裸片的顶部或底部。这占用了用于形成晶体管的宝贵空间,并且当裸片堆叠时,它们之间所需的连接要求裸片以阶梯形交错排列,从而导致形成完整或封装的集成装置需要更多空间。
发明内容
本文中所描述的工艺、装置和系统描述了沿着硅裸片的竖直边缘电气地连接裸片,从而降低所需要的横向空间要求。确切地说,通过将连接垫放在裸片的竖直边缘上,裸片可以竖直堆叠,而不需要使裸片交错排列来实现经由位于顶部或底部的连接垫形成的连接。实际上,可以沿着竖直对齐、在边缘安装的连接垫来进行线性连接,由此使硅裸片以完全竖直布置的方式堆叠。这减小了硅裸片的横向覆盖区,由此实现更小的总体外观尺寸。此外,晶体管大体上是在硅裸片的顶部和/或底部上而不是在竖直边缘上形成的。通过将连接垫放在边缘上,硅裸片上先前未使用的空间可以用于互连,从而为硅裸片顶部和/或底部上的晶体管形成腾出空间。
本文中所描述的方法和系统提供一种新颖且有利的连接技术,用于利用在边缘形成的连接垫将硅裸片互连,且具体来说,用于竖直堆叠的硅裸片。
本公开还提供一种设备,其包含衬底和两个或更多个硅裸片,其中第一裸片设置在所述衬底上,且第二裸片设置或堆叠在所述第一裸片上。所述硅裸片包含与所述衬底平行的上部平坦表面、与所述上部平坦表面平行且与所述第一平坦表面间隔第一距离的下部平坦表面、设置在所述上部平坦表面和所述下部平坦表面之间且垂直于所述上部平坦表面和所述下部平坦表面的第一边缘部分,及设置在所述第一边缘部分上且竖直对齐的第一组连接垫。所述设备进一步包含配置成耦合到所述一个或多个连接垫的导电元件,和数个焊料块。所述焊料块耦合到所述导电元件且以与所述第一组连接垫之间的距离相关联的间隔隔开。在一些实施例中,所述焊料块包含第一凹槽,所述第一凹槽具有量度为与所述第一边缘部分的宽度大致相同的宽度,且配置成将所述硅裸片的边缘接受在所述第一凹槽内。
本公开提供一种方法,其包含:堆叠数个硅裸片,使得所述硅裸片的一个或多个边缘竖直对齐,其中一个或多个边缘包含数个连接垫。所述方法还包含在大体上垂直于所述一个或多个边缘的轴线上定位大体上线性导体,其中所述线性导体与所述连接垫中的一个或多个接触。所述方法进一步包含向所述一个或多个连接垫及与所述一个或多个连接垫接触的所述线性导体的一个或多个部分施加导电焊料。所述方法还包含施加热以使所述焊料回流,以使所述焊料将所述线性导体的所述一个或多个部分物理地和电气地耦合到与其接触的所述一个或多个连接垫。
本公开还提供一种方法,其包含堆叠数个硅裸片,使得所述数个硅裸片的一个或多个边缘竖直对齐,其中所述一个或多个边缘包含数个连接垫。所述方法还包含在大体上垂直于所述一个或多个边缘的轴线上定位连接导线。所述连接导线包含数个焊料块。所述焊料块以与所述硅裸片上的第一组经对齐连接垫之间的距离相关联的间隔隔开。所述连接导线定位成使得所述焊料块与所述第一组经对齐连接垫接触。所述方法还包含施加热以使所述焊料块回流,以使所述焊料块将所述连接导线物理地耦合到所述经对齐连接垫。
以这种方式,本公开的各个方面至少在硅裸片互连及其设计和架构的技术领域中实现了改进。虽然本公开特别适用于连接堆叠式裸片,但本领域技术人员将理解,本公开可在其它实施例中使用,例如,其中裸片与衬底正交设置的实施例。上述概要仅旨在给出本公开的各个方面的总体思路,并不以任何方式限制本公开的范围。
附图说明
图1是根据本公开的一些实施例的连接一个或多个硅裸片的已知方法的透视图。
图2a是根据本公开的一些实施例的具有一个或多个竖直边缘连接垫的硅裸片的透视图。
图2b是根据本公开的一些实施例的图2a的硅裸片的横截面侧视图。
图3是根据本公开的一些实施例的示出连接两个或更多个硅裸片的工艺的流程图。
图4a是根据本公开的一些实施例的硅裸片的横截面,示出了在图3中描述的工艺的一部分。
图4b是根据本公开的一些实施例的硅裸片的横截面,示出了在图3中描述的工艺的另一部分。
图5是根据本公开的一些实施例的使用在图3中描述的工艺电气地耦合的两个硅裸片的透视图。
图6是根据本公开的一些实施例的焊料块的仰视图。
图7是根据本公开的一些实施例的示出连接多个硅裸片以形成封装式IC或另一封装式硅装置的工艺的流程图。
图8是根据本公开的一些实施例的准备进行电气耦合的多个硅裸片的透视图。
图9是根据本公开的一些实施例的电气耦合的多个硅裸片的透视图。
图10是根据本公开的一些实施例的耦合到衬底的多个硅裸片的透视图。
图11是根据本公开的一些实施例的耦合到衬底的硅裸片的替代布置。
具体实施方式
在以下描述中,为了提供对本公开的一个或多个方面的理解,阐述了许多细节,例如基于硅的裸片配置、硅裸片电气互连方法等等。本领域技术人员将很容易清楚,这些具体细节仅仅是示例性的,并不意图限制本申请的范围。以下描述仅旨在给出本公开的各个方面的总体思路,并不以任何方式限制本公开的范围。
图1是在封装式集成电路(“封装式IC”)或例如存储器装置的另一封装式硅装置(“封装”)内连接一个或多个硅裸片100的常规方法的透视图。如图1所示,硅裸片100包含定位在硅裸片100的顶表面104上的一个或多个连接垫102。为了连接硅裸片100的连接垫102,硅裸片100交错排列,使得每个后续硅裸片的连接垫102被暴露或可以接近。硅裸片的这种交错需要封装内的额外空间,由此常常使封装的大小增加。此外,随着更多的裸片被堆叠,上部裸片将更加突出,以致它们偏离中心,这可能会导致裸片倾斜和/或使裸片承受可能致使裸片开裂的应力。
现在转向图2a,根据一些实施例,示出了具有定位在竖直边缘204上的一个或多个连接垫202a、202b的硅裸片200的透视图。裸片200具有大体上平坦的上部表面206和大体上平坦的下部表面208,所述下部表面与所述上部表面206平行且与所述上部表面206间隔第一距离。在示出的实施例中,第一距离是裸片200的宽度。竖直边缘204设置在上部平坦表面206和下部平坦表面208之间且垂直于上部平坦表面206和下部平坦表面208。通过在竖直边缘上定位连接垫202a、202b,可以竖直堆叠一个或多个硅裸片200,而不必像图1所示的那样使硅裸片200交错或偏移。这使得在集成电路内堆叠多个硅裸片200时所需的空间更小。
图2b是硅裸片200的横截面侧视图,示出了连接垫202a。如图2b中所示,连接垫202a可与上部表面206和下部表面208部分地重叠。然而,在一些实施例中,在上部表面206和/或下部表面208上可能不存在连接垫202a的外部重叠。例如,连接垫202a(和连接垫202b)可能只在竖直边缘204上暴露,而连接垫202a的其余部分位于硅裸片200内。在一些实施例中,连接垫可具有25微米的第一长度210。然而,还设想了超过25微米或小于25微米的长度。在一些实施例中,此长度可以等于硅裸片200的竖直边缘204的宽度。
现在转向图3,根据一些实施例,示出了用于连接两个或更多个硅裸片的工艺300。在工艺框302处,将导电连接导线定位到第一硅裸片的第一连接垫上。连接导线可由一种或多种金属或其它导电材料构造而成,例如铜、铝、金、钯、铟、铱、各种银/锡混合物、铅以及二元和/或三元金属合金等。在一个实施例中,连接导线包括铜芯,此铜芯用诸如锡之类的金属镀覆,以免铜发生氧化。在一个实施例中,连接导线是圆形或大体上圆形导线。然而,在其它实例中,连接导线可以是扁平或带状导线。在一些实施例中,连接导线可具有大致24μm的直径。在其它实施例中,连接导线可具有在约16μm到约50μm的范围内的直径。在其它另外实施例中,连接导线可具有小于16μm或大于50μm的直径。
在一些实施例中,硅裸片定位成使得连接导线能够跨连接垫铺设,并使用重力维持其位置。这可参见图4a,其示出了定位到硅裸片404的连接垫402上的导电连接导线400。然而,在其它实施例中,可以使用各种其它方法将连接导线保持在连接垫上的适当位置。
一旦连接导线400定位在第一硅裸片的第一连接垫402上,就在工艺框304处向第一连接垫402和连接导线400施加液态焊料。这可参见图4b,其示出了施加到第一连接垫402继而又涵盖连接导线400的一大块液态焊料406。在一些实施例中,焊料是金焊料。在其它实施例中,焊料可以是银焊料、钯焊料、铱焊料、铟焊料、银/锡混合物焊料、一种或多种二元或三元金属合金焊料、铅焊料或其它可以施加的焊料类型。一般来说,加热焊料,将焊料回流成液态以供分配到连接垫402上。
一旦焊料被施加,就在工艺框306处向焊料、连接导线400和/或第一连接垫施加热。热使焊料熔化或回流,使焊料在第一连接垫和连接导线之间产生焊接点。在一些实施例中,第一连接垫和/或连接导线可以涂上焊剂材料,以促进在第一连接垫和连接导线之间形成适当的焊接点。尽管上述工艺300是关于使用焊料将连接导线400连接到第一连接垫402来描述的,但是经考虑,可以使用其它连接工艺,例如焊接、钎焊、激光焊接等等。
可以跨多个硅裸片使用工艺300。例如,如图5所示,在第一边缘506上具有第一连接垫502的第一硅裸片500与在第二硅裸片508的第一边缘512上具有第二连接垫510的第二硅裸片508对齐。经考虑,第一硅裸片500和第二硅裸片508的大小相同,并使它们的相关连接垫502、510处于相同位置,以促进硅裸片500、508的堆叠。如上文关于工艺300所描述,跨第一连接垫502和第二连接垫510两者定位连接导线514。与上文类似,硅裸片500、508可定位成使得第一连接垫502和第二连接垫510面朝上,使得重力能够在连接导线514上施加向下力,由此辅助将连接导线保持在适当位置。接着,可以将液态焊料放在第一连接垫502上的第一团块(或“斑点”)516中,然后放在第二连接垫510上的第二团块518中。然后,施加热以使焊料回流,从而促进连接导线514与第一连接垫502和第二连接垫510之间的焊接点。
在一些实施例中,可以向连接垫(以及相关联的焊料团块和连接导线)集中施加热,例如经由火焰喷射或激光加热。然而,在其它实施例中,向硅裸片(例如硅裸片500、508)施加一般热,以促进在裸片的连接垫处使焊料熔化或回流。例如,硅裸片可以放在回流熔炉中或经受全面式热源,例如经由扩散炉。
现在转向图6,根据一些实施例,示出了焊料块600的仰视图。焊料块600可由各种焊接材料制成,例如铟、金、银、钯、铱、铅或其它可以施加的焊料类型。如图6所示,焊料块600可具有方形形状,但是还设想了其它形状。焊料块600可包含第一槽或凹槽602和第二槽或凹槽604。第一槽602的大小可设定成容纳连接导线,例如上文所描述的那些连接导线。在一个实施例中,第一槽的宽度为大致15微米。然而,还设想了小于15微米或大于15微米的宽度。第一槽602在焊料块600内的位置可比第二槽604深,使得第二槽604能够收纳整个或部分连接垫,例如上文所描述的连接垫。
如上所述,第二槽604配置成收纳硅裸片的连接垫的全部或一部分,如上文所论述。在一个实施例中,第二槽604的宽度是25微米。然而,设想了大于25微米和小于25微米的宽度。另外,应理解,第二槽604的大小可设定成根据需要容纳不同大小的连接垫。例如,第二槽604可以比硅裸片的连接垫的宽度宽大致10%。然而,在适当时,第二槽可以宽超过10%或小于10%。第二槽604的深度可设定成接受连接垫的深度,使得在加热焊料块600时能够形成有效的焊接点(在下文更详细地描述)。例如,第二槽的深度可以是5微米。然而,还设想了大于5微米和小于5微米的深度。
在一些实施例中,焊料块600可在连接导线的制造期间耦合到连接导线。例如,多个焊料块600可以耦合到连接导线,并以与硅裸片之间的间隔相关联的距离隔开。这可允许连接导线被放置成与多个硅裸片接触,使得焊料块600定位在相应硅裸片的连接垫上方。
现在转向图7,根据一些实施例,示出了用于连接多个硅裸片以形成集成电路的工艺700。在工艺框702处,将两个或更多个硅裸片定位在一起。如上文所描述,可以竖直堆叠硅裸片,使得裸片边缘与共同轴线对齐。在一些实例中,可以在硅裸片之间放置裸片附接膜或裸片附接膜粘合剂,使这些硅裸片相对于彼此固定在适当位置。在其它实施例中,可以在硅裸片之间放置糊剂或其它液态粘合剂来使这些硅裸片相对于彼此固定在适当位置。在一些实施例中,裸片附接膜可在硅裸片之间提供等于裸片附接膜的厚度的间隔距离。例如,裸片附接膜可具有10微米的厚度。然而,还设想了大于10微米或小于10微米的厚度。在其它另外实施例中,裸片附接膜的大小可设定成未达到裸片的边缘,使得裸片边缘处存在微小的间隙。在另外其它实施例中,可以使用例如硅裸片坯料的间隔物来隔开邻近裸片。
硅裸片还可定位成使得连接垫面朝上。例如,可以旋转固持裸片的工件卡盘(workchuck),以便将连接垫旋转到面朝上,以允许重力帮助将连接导线保持在适当位置,如本文进一步描述的那样。在一些实施例中,工件卡盘可配置成在多个位置旋转硅裸片,以允许不同的连接垫在导线接合/焊接工艺中面朝上。经进一步考虑,硅裸片的定位采用已知的裸片定位技术。
硅裸片的定位在图8中示出。如图8中所示,根据一些实施例,设备包含第一硅裸片802、第二硅裸片804和第三硅裸片806。硅裸片802、804、806中的每一个包含两个连接垫808、810、812、814、816、818。第一硅裸片802和第二硅裸片804由第一裸片附接膜820隔开,第二硅裸片804和第三硅裸片806由第二裸片附接膜822隔开。如图8中所示,连接垫808、812、816呈第一对齐形式并形成第一组,且连接垫810、814和818呈第二对齐形式并形成第二组。
一旦在工艺框702处已定位硅裸片,就在工艺框704处将具有两个或更多个集成焊料块的连接导线定位到所述两个或更多个硅裸片上。在一个实施例中,连接导线定位成使得集成焊料块与一组竖直对齐的连接垫(即,第一组或第二组)对齐。例如,如图9所示,第一连接导线902分别定位在第一硅裸片802、第二硅裸片804和第三硅裸片806的连接垫808、812和816上方。第一连接导线902具有第一焊料块906、第二焊料块908和第三焊料块910,它们间隔开以与连接垫808、812和814对齐,如所示。类似地,第二连接导线904分别定位在第一硅裸片802、第二硅裸片804和第三硅裸片806的连接垫810、814和818上方。第一连接导线902具有第一焊料块912、第二焊料块914和第三焊料块916,它们间隔开以与连接垫808、812和814对齐,如所示。
现在重新转到图7,一旦在工艺框704中定位连接导线,就在工艺框706处施加热以使焊料块回流。在一个实施例中,向焊料块、连接垫和连接导线施加热,如上文所描述。在一些实施例中,可以向焊料块(以及相关联的连接垫和连接导线)集中施加热,例如经由火焰喷射或激光加热。然而,在其它实施例中,向硅裸片施加一般热,以促进在裸片的连接垫处使焊料熔化或回流。例如,硅裸片可以放在回流熔炉中或经受全面式热源,例如经由扩散炉。
现在转向图10,上文所描述的硅裸片802、804和806经由连接导线902、904耦合到衬底1000。衬底1000可包含第一连接垫1002和第二连接垫1004,它们分别用于连接到第一连接导线902和第二连接导线904。在一些实施例中,衬底1000可包含通道1006。在一些实施例中,通道1006允许连接导线902、904安装到衬底1000上,而不需要连接导线进行任何弯曲或其它变形。尽管图8、9和10的实例示出了经由两个连接导线连接的三个硅裸片的实例,但是经考虑,上文所描述的工艺700可以根据需要扩展成与超过三个硅裸片以及与超过两个连接导线一起使用。因此,图8、9和10的实例仅出于说明性目的,不应被理解为将本文描述的工艺限制为图中所示的特定组件。
现在转向图11,以组合件1100的形式示出了硅裸片的替代布置。组合件1100包含第一硅裸片1102、第三硅裸片1104和第五硅裸片1106,它们包含位于硅裸片1102、1104和1106的第一边缘1110上的连接垫1108。第二硅裸片1112、第四硅裸片1114和第六硅裸片1116分别交替地定位在第一硅裸片1102、第三硅裸片1104和第五硅裸片1106之间。第二硅裸片1112、第四硅裸片1114和第六硅裸片1116包含位于与第一硅裸片1102、第三硅裸片1104和第五硅裸片1106的第一边缘相对的第二边缘1120上的连接垫1118。第一连接导线1122耦合到第一硅裸片1102、第三硅裸片1104和第五硅裸片1106的连接垫1108,且第二连接导线1124耦合到第二硅裸片1112、第四硅裸片1114和第六硅裸片1116的连接垫1118。第一连接导线1122在第一衬底连接垫1128处耦合到衬底1126。类似地,第二连接导线1124经由第二连接垫1130耦合到衬底1126。
组合件1100被称为双通道结构,实现了每隔一个裸片进行一次连接。此配置还可因为硅裸片的交替而实现连接之间存在更多空间,从而减小了由连接导线焊接到裸片连接垫造成的短路风险。将连接导线连接到连接垫的焊接点可以使用上文所描述的工艺来完成,例如工艺300和/或工艺700,由此能够沿着相应硅裸片的竖直侧面进行连接。在一些实例中,可以使用四通道结构,如此可以在硅裸片的给定边缘上每隔三个裸片进行一次连接。图11中所示的实例是出于说明性目的,并且经考虑,可以根据给定应用的需要使用上文所描述的双通道或四通道设计来连接多个裸片。
所描述的实施例特别适用于电气地连接堆叠式硅裸片。例如,一些版本的电子存储器装置包含多个堆叠式NAND裸片。因此,具有多个NAND裸片堆叠在衬底上的存储器装置将得益于本文所公开的特征和裸片电气互连方法。
关于本文中所描述的工艺、系统、方法、启发法等,应理解,虽然所述工艺的步骤等等已经被描述为根据某一排序的顺序进行,但是所述工艺可以按所描述步骤以除本文中所描述的次序以外的次序进行的方式来实践。此外应理解,可以同时进行某些步骤,可以添加其它步骤,也可以省略本文中所描述的某些步骤。换句话说,本文中对工艺的描述是为了说明某些实施例而提供的,并且绝不应理解为限制权利要求书。
如本文中所使用,术语大体上意指约、几乎或在所修饰的术语的上下10-20%内。例如,“大体上线性”意指对象在完全线性(即,笔直)的10-20%内。类似地,“大体上圆形”意指对象可相对于正圆形尺寸具有10-20%的变形或偏转。
因此,应理解,以上描述打算是说明性而非限制性的。在阅读以上描述后,将清楚除所提供的实例以外的许多实施例和应用。本发明的范围不应参考以上描述来确定,而是应参考所附权利要求书以及此类权利要求书授权的等效物的全部范围来确定。预期并希望在本文所讨论的技术中出现未来的发展,并且所公开的装置、方法和设备将被合并到这些未来的实施例中。总之,应理解,本申请能够修改和改变。
除非本文中明确地进行相反指示,否则权利要求书中所用的所有术语都旨在具有如在本文中所描述的技术方面博学的人员所理解的其最广泛的合理构造和其普通含义。具体地说,除非权利要求书相反地叙述了明确限制,否则例如“一”、“所述(the/said)”等单数冠词的使用应理解为列举一个或多个所表示的要素。
提供摘要,使得读者能够快速确定本技术公开的性质。在理解以下内容的情况下进行提交:摘要将不会用于解释或限制权利要求书的范围或含义。另外,在前述具体实施方式中,可以看出在各种实施例中,出于精简本公开的目的而将各种特征分组在一起。不应将本公开的此方法解释为反映以下意图:要求保护的实施例需要比每一权利要求中明确叙述的特征多的特征。相反,如所附权利要求书所反映,本发明主题在于单个所公开实施例的不到全部的特征。因此,所附权利要求书特此被并入到具体实施方式中,其中每一权利要求独自作为单独主张的主题。
Claims (20)
1.一种设备,其包括:
衬底;
两个或更多个硅裸片,其中第一裸片设置在所述衬底上,且第二裸片堆叠在所述第一裸片上,并且所述裸片包括:
上部平坦表面,其与所述衬底平行;
下部平坦表面,其与所述上部平坦表面平行且与所述上部平坦表面间隔第一距离;
至少第一边缘部分,其设置在所述上部平坦表面和所述下部平坦表面之间且垂直于所述上部平坦表面和所述下部平坦表面;以及
至少第一组连接垫,其设置在所述至少第一边缘部分上,并且其中所述第一组连接垫彼此竖直对齐;
导电元件,其配置成耦合到所述第一组连接垫;以及
多个焊料块,其耦合到所述导电元件且以与所述第一组连接垫中的所述连接垫之间的距离相关联的间隔隔开。
2.根据权利要求1所述的设备,其中所述焊料块配置成被加热,使得所述焊料块回流并在所述导电元件和所述第一组连接垫之间产生焊接连接。
3.根据权利要求1所述的设备,其中所述焊料块包括第一凹槽,所述第一凹槽具有量度为与所述第一距离大致相同的宽度且配置成在所述第一凹槽内接受所述硅裸片的边缘。
4.根据权利要求3所述的设备,其中所述第一凹槽的所述宽度比所述第一边缘部分的宽度宽10%。
5.根据权利要求4所述的设备,其中所述第一边缘部分的所述宽度是25微米。
6.根据权利要求1所述的设备,其中所述导电元件电气地连接到所述衬底。
7.根据权利要求6所述的设备,其中所述衬底包含通道,且所述导电元件在所述通道内电气地连接到所述衬底。
8.根据权利要求1所述的设备,其进一步包括用于将所述第一裸片附接到所述第二裸片的构件。
9.根据权利要求1所述的设备,其进一步包括裸片附接膜,所述裸片附接膜设置在所述第一裸片和所述第二裸片之间且物理地连接所述第一裸片和所述第二裸片。
10.根据权利要求1所述的设备,其进一步包括用于隔开所述第一裸片与所述第二裸片的构件。
11.根据权利要求1所述的设备,其中所述导电元件包括镀锡铜线。
12.根据权利要求1所述的设备,其中所述两个或更多个硅裸片的第一子集在所述第一边缘上具有所述第一组连接垫,且所述两个或更多个硅裸片的第二子集在第二边缘上具有第二组连接垫,其中所述第二边缘不同于所述第一边缘。
13.根据权利要求12所述的设备,其中所述两个或更多个硅裸片布置成使得所述两个或更多个硅裸片的所述第一子集中的每个硅裸片与所述两个或更多个硅裸片的所述第二子集交替。
14.根据权利要求1所述的设备,其中所述导电元件和所述连接垫中的至少一个涂覆有焊剂材料。
15.根据权利要求1所述的设备,其中所述导电焊料包括选自由以下组成的群组的至少一个:金、铟、铱、镀锡铜和钯。
16.一种方法,其包括:
堆叠多个硅裸片,使得所述多个硅裸片的一个或多个边缘竖直对齐,其中所述一个或多个边缘包含多个连接垫;
在大体上垂直于所述一个或多个边缘的轴线上定位大体上线性导体,其中所述线性导体与所述多个连接垫中的一个或多个接触;
向所述一个或多个连接垫及与所述一个或多个连接垫接触的所述线性导体的一个或多个部分施加导电焊料;以及
施加热以使所述焊料回流,以使所述焊料将所述线性导体的所述一个或多个部分物理地和电气地耦合到与其接触的所述一个或多个连接垫。
17.根据权利要求16所述的方法,其进一步包括用焊剂层涂覆所述线性导体。
18.根据权利要求16所述的方法,其中通过向所述一个或多个连接垫及与所述一个或多个连接垫接触的所述线性导体的所述一个或多个部分施加受热的液态焊料来施加所述导电焊料。
19.一种方法,其包括:
堆叠多个硅裸片,使得所述多个硅裸片的一个或多个边缘竖直对齐,其中所述一个或多个边缘包含多个连接垫;
在大体上垂直于所述一个或多个边缘的轴线上定位连接导线,其中所述连接导线包括以与所述多个硅裸片上的第一组经对齐连接垫之间的距离相关联的间隔隔开的多个焊料块,并且其中所述连接导线定位成使得所述多个焊料块与所述第一组经对齐连接垫接触;
施加热以使所述焊料块回流,以使所述焊料块将所述连接导线物理地耦合到所述经对齐连接垫。
20.根据权利要求19所述的方法,其中使用火焰喷射加热工艺以使所述焊料块回流。
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US17/171,576 US11456272B2 (en) | 2020-09-11 | 2021-02-09 | Straight wirebonding of silicon dies |
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JPS6118164A (ja) | 1984-07-04 | 1986-01-27 | Mitsubishi Electric Corp | 半導体装置 |
JPH1084012A (ja) | 1996-09-06 | 1998-03-31 | Hitachi Ltd | 半導体装置 |
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US6089920A (en) | 1998-05-04 | 2000-07-18 | Micron Technology, Inc. | Modular die sockets with flexible interconnects for packaging bare semiconductor die |
JP2001156250A (ja) | 1999-11-24 | 2001-06-08 | Seiko Epson Corp | 半導体チップ、マルチチップパッケージ,および半導体装置と、並びに、それを用いた電子機器 |
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KR20090034081A (ko) * | 2007-10-02 | 2009-04-07 | 삼성전자주식회사 | 적층형 반도체 패키지 장치 및 이의 제작 방법 |
TWI355061B (en) | 2007-12-06 | 2011-12-21 | Nanya Technology Corp | Stacked-type chip package structure and fabricatio |
US9153517B2 (en) * | 2008-05-20 | 2015-10-06 | Invensas Corporation | Electrical connector between die pad and z-interconnect for stacked die assemblies |
JP5112275B2 (ja) * | 2008-12-16 | 2013-01-09 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
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