CN114134565A - Method for preparing InP film based on GaAs substrate - Google Patents

Method for preparing InP film based on GaAs substrate Download PDF

Info

Publication number
CN114134565A
CN114134565A CN202111325697.6A CN202111325697A CN114134565A CN 114134565 A CN114134565 A CN 114134565A CN 202111325697 A CN202111325697 A CN 202111325697A CN 114134565 A CN114134565 A CN 114134565A
Authority
CN
China
Prior art keywords
layer
gaas substrate
inp
buffer layer
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111325697.6A
Other languages
Chinese (zh)
Other versions
CN114134565B (en
Inventor
徐鹏飞
王岩
罗帅
季海铭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Huaxing Laser Technology Co ltd
Original Assignee
Jiangsu Huaxing Laser Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Huaxing Laser Technology Co ltd filed Critical Jiangsu Huaxing Laser Technology Co ltd
Priority to CN202111325697.6A priority Critical patent/CN114134565B/en
Publication of CN114134565A publication Critical patent/CN114134565A/en
Application granted granted Critical
Publication of CN114134565B publication Critical patent/CN114134565B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)

Abstract

The invention discloses a method for preparing an InP film based on a GaAs substrate, which comprises the following steps: (1) selecting a GaAs substrate; (2) growing a GaAs buffer layer on the GaAs substrate; (3) preparing a composite buffer layer on the GaAs buffer layer, wherein the composite buffer layer is composed of a graphene layer and GaxIn1‑xThe P material layers are alternately grown, the lowest layer is a graphene layer, and the uppermost layer is GaxIn1‑xA P material layer; (4) and growing an InP film on the composite buffer layer. The invention is based on a single crystal GaAs substrate, adopts graphene and Ga with uniformly distributed nano-pillar structuresxIn1‑ xThe composite buffer layer combined by the P material is used for preparing the InP film, so that the mismatch stress generated when an InP material layer is epitaxially grown on the GaAs substrate can be eliminated, the defect density of the material layer is reduced, and the crystal quality of the InP film is improved. Book (I)The invention can prepare InP materials based on the GaAs substrate with mature technology and lower cost, and finally realizes the preparation of InP photoelectronic devices on the GaAs substrate.

Description

Method for preparing InP film based on GaAs substrate
Technical Field
The invention belongs to the technical field of semiconductor films, and particularly relates to a method for preparing an InP film based on a GaAs substrate.
Background
The III-V group compound material InP can be applied to various photoelectric devices such as solar cells, semiconductor lasers and the like. The bonded five-junction solar cell can be manufactured based on InP materials, and the theoretical efficiency of the space spectrum can reach over 36%. The InP-based material can also be used for manufacturing long-wavelength semiconductor lasers, can be applied to the fields of long-wavelength communication, long-distance detection and the like, and has huge market demands. However, the conventional technology for preparing the InP photoelectric material is mainly based on an expensive InP substrate, which makes the manufacturing cost of the InP photoelectric device high. The most mature substrate material of the III-V materials is GaAs, which has been widely used in semiconductor Light Emitting Diodes (LEDs) and semiconductor lasers. The cost of an InP photoelectric device can be obviously reduced by preparing an InP material based on a GaAs substrate, but because InP and GaAs have larger lattice constants, the adoption of the GaAs substrate to grow an InP thin film can introduce more material defects, and a plurality of technical problems need to be overcome.
Disclosure of Invention
The invention aims to overcome the defects and shortcomings of the prior art and provides a method for preparing an InP film based on a GaAs substrate.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method for preparing an InP thin film based on a GaAs substrate comprises the following steps:
(1) selecting a GaAs substrate;
(2) growing a GaAs buffer layer on the GaAs substrate;
(3) preparing a composite buffer on the GaAs buffer layerA composite buffer layer composed of graphene layer and GaxIn1- xThe P material layers are alternately grown, the lowest layer is the graphene layer, the uppermost layer is the GaxIn1-xA P material layer;
(4) and growing an InP thin film on the composite buffer layer.
In the above technical solution, in the step (3), each layer of the GaxIn1-xThe P material layer is formed of different composition materials.
In the above technical scheme, in the step (3), the number of graphene atomic layers in the graphene layer is 2-5, and the Ga layer isxIn1-xThe Ga component x of each layer in the P material layer is gradually reduced from bottom to top, x is more than 0 and less than 0.5, and the reduction step length of x is 0.05-0.1.
In the technical scheme, in the step (3), the number of alternately grown pairs is 5-10 pairs.
In the above technical solution, in the step (3), each layer of the GaxIn1-xThe upper surface of the P material layer is provided with nano-columns.
In the above technical scheme, the mesa of the nano-pillar is square, the side length is 10-50nm, the height of the nano-pillar is 20-100nm, and the distance between adjacent nano-pillars is 100-1000 nm.
In the above technical solution, in the step (1), the GaAs substrate is a single crystal GaAs substrate.
In the above technical solution, in the step (2), the thickness of the GaAs buffer layer is 300-1000 nm.
In the above technical solution, in the step (4), the growth thickness of the InP thin film is greater than 100 nm.
The invention has the beneficial effects that: the preparation method utilizes graphene and Ga with uniformly distributed nano-pillar structuresxIn1-xThe P combined composite buffer layer can eliminate the mismatch stress generated when an InP material layer is epitaxially grown on the GaAs substrate, reduce the defect density of the material layer and improve the crystal quality of the InP film.
Drawings
FIG. 1 is a schematic structural diagram of an InP thin film prepared based on a GaAs substrate;
wherein: 10. a GaAs substrate; 20. a GaAs buffer layer; 30. a composite buffer layer; 31. a graphene layer; 32. gaxIn1-xA P material layer; 40. an InP thin film.
Detailed Description
To better illustrate the objects, aspects and advantages of the present invention, the present invention will be further described with reference to specific embodiments. This invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present invention will only be defined by the appended claims.
The invention provides a method for preparing an InP film based on a GaAs substrate, as shown in FIG. 1, the InP film prepared by the method has a structure diagram, and is sequentially laminated from bottom to top into a GaAs substrate 10, a GaAs buffer layer 20, a composite buffer layer 30 and an InP film layer 40. Wherein the composite buffer layer 30 is composed of graphene layer 31 and GaxIn1-xThe P material layers 32 are alternately composed.
The following is one embodiment of the above-described specific preparation process for preparing an InP thin film based on a GaAs substrate, including the steps of:
(1) selecting a 4-inch single crystal GaAs wafer as a substrate 10;
(2) growing a GaAs buffer layer 20 on the GaAs substrate 10 by adopting a chemical vapor deposition technology, wherein the thickness of the buffer layer is 500 nm;
(3) preparing a composite buffer layer 30 on the GaAs buffer layer 20 by combining a chemical vapor deposition technology and a nano-lithography technology, wherein the composite buffer layer 30 is composed of a graphene layer 31 and GaxIn1-xThe P material layers 32 are alternately grown, and the lowermost layer is the graphene layer 31 and the uppermost layer is GaxIn1-xA layer of P material 32. Wherein, the number of graphene atomic layers in the graphene layer 31 is 3, and GaxIn1-xThe Ga component x of each layer in the P material layer 32 is gradually reduced from bottom to top, x is more than 0 and less than 0.5, and the reduction step size of x is 0.1. Each layer of GaxIn1-xP material is allForming nano columns on the surface of the substrate by adopting a nano photoetching technology, wherein the surface of each nano column is square, the side length is 20nm, the height of each nano column is 50nm, and the distance between every two adjacent nano columns is 500 nm;
(4) an InP film 40 is prepared on the composite buffer layer 30 by using a chemical vapor deposition technology, and the thickness of the film layer is 500 nm.
The invention is based on a single crystal GaAs substrate, adopts graphene and Ga with uniformly distributed nano-pillar structuresxIn1-xThe composite buffer layer combined by the P material is used for preparing the InP film, so that the mismatch stress generated when an InP material layer is epitaxially grown on the GaAs substrate can be eliminated, the defect density of the material layer is reduced, and the crystal quality of the InP film is improved. The invention can prepare InP materials based on the GaAs substrate with mature technology and lower cost, finally realizes the preparation of InP photoelectronic devices on the GaAs substrate, has stronger application value and is worth popularizing.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (9)

1. A method for preparing an InP film based on a GaAs substrate is characterized in that: the method comprises the following steps:
(1) selecting a GaAs substrate (10);
(2) growing a GaAs buffer layer (20) on the GaAs substrate (10);
(3) preparing a composite buffer layer (30) on the GaAs buffer layer (20), wherein the composite buffer layer (30) is composed of a graphene layer (31) and GaxIn1-xP material layers (32) are alternately grown, the lowest layer is the graphene layer (31), the uppermost layer is the GaxIn1-xA P material layer (32);
(4) and growing an InP thin film (40) on the composite buffer layer (30).
2. The method of claim 1, further comprising: in step (3), each layer of the GaxIn1-xThe P material layer (32) is formed of a different composition material.
3. The method of claim 1, further comprising: in the step (3), the number of graphene atomic layers in the graphene layer (31) is 2-5, and the GaxIn1-xThe Ga component x of each layer in the P material layer (32) is gradually reduced from bottom to top, x is more than 0 and less than 0.5, and the reduction step size of x is 0.05-0.1.
4. The method of claim 1, further comprising: in the step (3), the number of alternate growth pairs is 5-10 pairs.
5. The method of claim 1, further comprising: in step (3), each layer of the GaxIn1-xThe upper surface of the P material layer (32) is provided with nano columns.
6. The method of claim 5, further comprising: the mesa of the nano-column is square, the side length is 10-50nm, the height of the nano-column is 20-100nm, and the distance between the adjacent nano-columns is 100-1000 nm.
7. The method of claim 1, further comprising: in step (1), the GaAs substrate (10) is a single crystal GaAs substrate.
8. The method of claim 1, further comprising: in the step (2), the thickness of the GaAs buffer layer (20) is 300-1000 nm.
9. The method of claim 1, further comprising: in the step (4), the InP thin film (40) is grown to a thickness of more than 100 nm.
CN202111325697.6A 2021-11-10 2021-11-10 Method for preparing InP film based on GaAs substrate Active CN114134565B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111325697.6A CN114134565B (en) 2021-11-10 2021-11-10 Method for preparing InP film based on GaAs substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111325697.6A CN114134565B (en) 2021-11-10 2021-11-10 Method for preparing InP film based on GaAs substrate

Publications (2)

Publication Number Publication Date
CN114134565A true CN114134565A (en) 2022-03-04
CN114134565B CN114134565B (en) 2023-04-25

Family

ID=80392680

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111325697.6A Active CN114134565B (en) 2021-11-10 2021-11-10 Method for preparing InP film based on GaAs substrate

Country Status (1)

Country Link
CN (1) CN114134565B (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965224A (en) * 1988-02-16 1990-10-23 Oki Electric Industry Co., Ltd. Process for fabricating an INP semiconductor thin film on silicon
JP2005333095A (en) * 2003-06-13 2005-12-02 Sumitomo Chemical Co Ltd Compound semiconductor, manufacturing method of the same and compound semiconductor element
CN102560634A (en) * 2012-02-20 2012-07-11 华南理工大学 Method for growing InGaAs film on GaAs substrate
CN102723405A (en) * 2012-06-26 2012-10-10 中国科学院苏州纳米技术与纳米仿生研究所 Method for preparing double-faced growth efficient wide-spectrum absorption multi-junction solar cell
CN202616233U (en) * 2012-05-15 2012-12-19 深圳信息职业技术学院 A tensile strain germanium thin film epitaxy structure
CN105552187A (en) * 2015-12-16 2016-05-04 中国科学院半导体研究所 GaN thin film prepared by GaN nano-patterned substrate homoepitaxy and method
CN106653973A (en) * 2016-12-19 2017-05-10 华灿光电（浙江）有限公司 LED chip and preparation method thereof
CN106684699A (en) * 2016-12-06 2017-05-17 超晶科技（北京）有限公司 Two-dimensional material flexible substrate structure, semiconductor light emitting device and manufacturing method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965224A (en) * 1988-02-16 1990-10-23 Oki Electric Industry Co., Ltd. Process for fabricating an INP semiconductor thin film on silicon
JP2005333095A (en) * 2003-06-13 2005-12-02 Sumitomo Chemical Co Ltd Compound semiconductor, manufacturing method of the same and compound semiconductor element
CN102560634A (en) * 2012-02-20 2012-07-11 华南理工大学 Method for growing InGaAs film on GaAs substrate
CN202616233U (en) * 2012-05-15 2012-12-19 深圳信息职业技术学院 A tensile strain germanium thin film epitaxy structure
CN102723405A (en) * 2012-06-26 2012-10-10 中国科学院苏州纳米技术与纳米仿生研究所 Method for preparing double-faced growth efficient wide-spectrum absorption multi-junction solar cell
CN105552187A (en) * 2015-12-16 2016-05-04 中国科学院半导体研究所 GaN thin film prepared by GaN nano-patterned substrate homoepitaxy and method
CN106684699A (en) * 2016-12-06 2017-05-17 超晶科技（北京）有限公司 Two-dimensional material flexible substrate structure, semiconductor light emitting device and manufacturing method thereof
CN106653973A (en) * 2016-12-19 2017-05-10 华灿光电（浙江）有限公司 LED chip and preparation method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SANG-HOON BAE，ET AL.: "Graphene-assisted spontaneous relaxation towards dislocation-free heteroepitaxy", 《NATURE NANOTECHNOLOGY》 *

Also Published As

Publication number Publication date
CN114134565B (en) 2023-04-25

Similar Documents

Publication Publication Date Title
US8962991B2 (en) Pseudomorphic window layer for multijunction solar cells
US9437769B2 (en) Four-junction quaternary compound solar cell and method thereof
CN103325663B (en) The preparation method of heterostructure is received in the compound of nanowire sidewalls growth quantum point
US20070151595A1 (en) Solar cell with superlattice structure and fabricating method thereof
CN103236480B (en) A kind of epitaxial wafer of light-emitting diode and manufacture method thereof
CN1929153A (en) InGaN series broad band solar battery comprising multiple quanta structure
US20110220190A1 (en) Solar cell having a graded buffer layer
CN102388466A (en) Photovoltaic cell
US20140116494A1 (en) High-Efficiency Four-Junction Solar Cells and Fabrication Methods Thereof
WO2012154455A1 (en) Window structure for solar cell
CN105474360A (en) III-V or II-VI compound semiconductor films on graphitic substrates
CN102254918A (en) Tandem solar cell and manufacturing method
CN104300058B (en) A kind of green-yellow light LED of the wide barrier structure containing doping
CN209104183U (en) A kind of high performance green diode multi-quantum pit structure
CN105576068B (en) Double-face-growing InP five-junction solar battery
CN101859814A (en) Method for growing InGaP/GaAs/Ge three-junction solar cell on silicon substrate
EP2758996B1 (en) Varying bandgap solar cell
CN114134565B (en) Method for preparing InP film based on GaAs substrate
CN114171615B (en) Silicon-based multi-junction solar cell and gradual change buffer layer thereof
CN210778633U (en) Nitride multi-junction solar cell
TW201318189A (en) Laminated body for manufacturing compound semiconductor solar cell, compound semiconductor solar cell, and method for manufacturing compound semiconductor solar cell
CN114024210B (en) Silicon-based vertical cavity surface emitting laser
CN111261744A (en) Multi-junction solar cell and preparation method thereof
CN1624996A (en) High-indium component gallium arsenic/indium gallium arsenic quantum pit structure and preparation method thereof
WO2005038889A1 (en) The method for allngan epitaxial growth on silicon substrate

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant