CN114114825B - 一种掩模版优化方法及晶体管栅极制作工艺方法 - Google Patents
一种掩模版优化方法及晶体管栅极制作工艺方法 Download PDFInfo
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- CN114114825B CN114114825B CN202210096861.9A CN202210096861A CN114114825B CN 114114825 B CN114114825 B CN 114114825B CN 202210096861 A CN202210096861 A CN 202210096861A CN 114114825 B CN114114825 B CN 114114825B
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000005457 optimization Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000012937 correction Methods 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 238000001259 photo etching Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000012360 testing method Methods 0.000 claims description 11
- 239000011159 matrix material Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005259 measurement Methods 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 238000002474 experimental method Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 abstract description 4
- 238000012545 processing Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000013480 data collection Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
Description
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202210096861.9A CN114114825B (zh) | 2022-01-27 | 2022-01-27 | 一种掩模版优化方法及晶体管栅极制作工艺方法 |
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CN202210096861.9A CN114114825B (zh) | 2022-01-27 | 2022-01-27 | 一种掩模版优化方法及晶体管栅极制作工艺方法 |
Publications (2)
Publication Number | Publication Date |
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CN114114825A CN114114825A (zh) | 2022-03-01 |
CN114114825B true CN114114825B (zh) | 2022-04-15 |
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CN202210096861.9A Active CN114114825B (zh) | 2022-01-27 | 2022-01-27 | 一种掩模版优化方法及晶体管栅极制作工艺方法 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100842751B1 (ko) * | 2007-05-21 | 2008-07-01 | 주식회사 하이닉스반도체 | 듀얼폴리실리콘 게이트에 대한 광근접효과 보정 방법 |
CN102194675A (zh) * | 2010-03-11 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | 制作半导体器件栅极的方法 |
CN113759659A (zh) * | 2021-09-08 | 2021-12-07 | 广东省大湾区集成电路与系统应用研究院 | 光源掩模优化方法及光刻仿真装置 |
-
2022
- 2022-01-27 CN CN202210096861.9A patent/CN114114825B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100842751B1 (ko) * | 2007-05-21 | 2008-07-01 | 주식회사 하이닉스반도체 | 듀얼폴리실리콘 게이트에 대한 광근접효과 보정 방법 |
CN102194675A (zh) * | 2010-03-11 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | 制作半导体器件栅极的方法 |
CN113759659A (zh) * | 2021-09-08 | 2021-12-07 | 广东省大湾区集成电路与系统应用研究院 | 光源掩模优化方法及光刻仿真装置 |
Non-Patent Citations (1)
Title |
---|
Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs;Xu Mizo 等;《Journal of Semiconductors》;20150430;第36卷(第4期);第044007-1至044007-4页 * |
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CN114114825A (zh) | 2022-03-01 |
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Effective date of registration: 20220922 Address after: 510000 building a, No. 136, Kaiyuan Avenue, Huangpu Development Zone, Guangzhou, Guangdong Patentee after: Guangdong Dawan District integrated circuit and System Application Research Institute Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 building a, No. 136, Kaiyuan Avenue, Huangpu Development Zone, Guangzhou, Guangdong Patentee before: Guangdong Dawan District integrated circuit and System Application Research Institute Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |
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Effective date of registration: 20240802 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Country or region after: China Address before: 510000 building a, No. 136, Kaiyuan Avenue, Huangpu Development Zone, Guangzhou, Guangdong Patentee before: Guangdong Dawan District integrated circuit and System Application Research Institute Country or region before: China Patentee before: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. |