CN114094014B - Metal capacitor structure and preparation method thereof - Google Patents
Metal capacitor structure and preparation method thereof Download PDFInfo
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- CN114094014B CN114094014B CN202210024334.7A CN202210024334A CN114094014B CN 114094014 B CN114094014 B CN 114094014B CN 202210024334 A CN202210024334 A CN 202210024334A CN 114094014 B CN114094014 B CN 114094014B
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
The invention provides a metal capacitor structure and a preparation method thereof, wherein the metal capacitor structure comprises the following steps: a substrate; the capacitor structure comprises a bottom metal layer, a first interlayer dielectric layer, a middle metal layer, a second interlayer dielectric layer and a top metal layer which are sequentially stacked on the substrate; the first openings are positioned in the top metal layer and expose the surface of the second interlayer dielectric layer; and the second openings penetrate through the second interlayer dielectric layer and the middle metal layer from the bottom of part of the first openings downwards until the surface of the first interlayer dielectric layer is exposed. The invention increases the capacitance value of the metal capacitor structure and reduces the thickness of the metal capacitor structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a metal capacitor structure and a preparation method thereof.
Background
Metal-insulator-metal (MIM) capacitors are widely used in analog and radio frequency circuits due to their small parasitic resistance. Different application requirements, parasitic resistance requirements for metal capacitors are also different. When the metal capacitor is used for a radio frequency circuit, the capacitance resistance is low due to high frequency (GHz), and the total impedance of the parasitic resistance in the whole metal capacitor is high, so that the total impedance needs to be reduced as much as possible. However, for low frequency analog circuits, such as in panel driver chip applications, the metal capacitor used as a charge pump memory requires a higher Breakdown voltage, and the corresponding Time Dependent Dielectric Breakdown (TDDB) voltage requirement for the metal capacitor is higher.
Fig. 1 is a schematic cross-sectional view of a metal capacitor structure, referring to fig. 1, the metal capacitor structure includes a substrate 10, a capacitor structure formed on the substrate 10, an opening (not shown), a passivation layer 30, a plurality of first electrical connecting members 41 and second electrical connecting members 42, the capacitor structure includes a bottom metal layer 21, an interlayer dielectric layer 22 and a top metal layer 23 stacked on the substrate 10 in sequence, the opening is located on the top metal layer 23 and exposes the interlayer dielectric layer 22, the passivation layer 30 fills the opening and covers the top metal layer 23, the first electrical connecting members 41 and the second electrical connecting members 42 are formed on the passivation layer 30, the first electrical connecting members 41 penetrate through the passivation layer 30 and the interlayer dielectric layer 22 and are electrically connected with the bottom metal layer 21, and the second electrical connecting members 42 penetrate through the passivation layer 30 and are electrically connected with the top metal layer 23. The thickness and the width of an interlayer dielectric layer 22 opposite to each other between a bottom metal layer 21 and a top metal layer 23 determine a capacitance value of the metal capacitor structure, the thinner the thickness of the dielectric layer is, the larger the capacitance value is, but the lower the breakdown voltage of the metal capacitor structure is, the worse the reliability under the working voltage is (represented by time dependent dielectric breakdown TDDB), TDDB is one of reliability indexes for evaluating the quality of the dielectric layer, constant voltage is applied to two ends of the metal capacitor structure to enable the metal capacitor structure to be in an accumulation state, after a period of time, the dielectric layer can be broken down, the period of time is the service life of the metal capacitor structure under the condition, and if the TDDB performance of the metal capacitor structure is reduced, the metal capacitor structure is easy to break down to cause chip failure.
Fig. 2 is a schematic cross-sectional view of a metal capacitor structure, please refer to fig. 2, in order to increase a capacitance value of the metal capacitor structure and maintain a breakdown voltage of the metal capacitor structure, a second metal capacitor structure 52 is formed on the first metal capacitor structure 51 in an overlapping manner to form a new metal capacitor structure, so as to increase the capacitance value of the metal capacitor structure.
Disclosure of Invention
The invention aims to provide a metal capacitor structure and a preparation method thereof, so as to increase the capacitance value of the metal capacitor structure and reduce the thickness of the metal capacitor structure.
In order to achieve the above object, the present invention provides a metal capacitor structure, including:
a substrate;
the capacitor structure comprises a bottom metal layer, a first interlayer dielectric layer, a middle metal layer, a second interlayer dielectric layer and a top metal layer which are sequentially stacked on the substrate;
the first openings are positioned in the top metal layer and expose the surface of the second interlayer dielectric layer;
and the second openings penetrate through the second interlayer dielectric layer and the middle metal layer from the bottom of part of the first openings downwards until the surface of the first interlayer dielectric layer is exposed.
Optionally, the method further includes:
a passivation layer located on the top metal layer and filling the first opening and the second opening;
and the plurality of electric connecting pieces are positioned on the passivation layer, one part of the electric connecting pieces penetrate through the passivation layer and are electrically connected with the top metal layer, and also penetrate through the passivation layer in the first opening and the second opening and the first interlayer dielectric layer and are electrically connected with the bottom metal layer, and the rest part of the electric connecting pieces penetrate through the passivation layer in the first opening and the second interlayer dielectric layer and are electrically connected with the middle metal layer.
Optionally, the bottom metal layer, the middle metal layer, and the top metal layer are made of one or more of titanium, copper, and aluminum.
Optionally, the first interlayer dielectric layer and the second interlayer dielectric layer are made of any one of silicon nitride, silicon oxide, or silicon oxynitride.
Optionally, the material of the electrical connector includes any one of tungsten, aluminum or copper.
A method for preparing a metal capacitor structure comprises the following steps:
providing a substrate;
forming a capacitor structure on the substrate, wherein the capacitor structure comprises a bottom metal layer, a first interlayer dielectric layer, a middle metal layer, a second interlayer dielectric layer and a top metal layer which are sequentially stacked on the substrate;
forming a plurality of first openings in the top metal layer and exposing the surface of the second interlayer dielectric layer; and the number of the first and second groups,
and forming a plurality of second openings which penetrate through the second interlayer dielectric layer and the middle metal layer from the bottom of part of the first openings to the bottom of the first opening until the surface of the first interlayer dielectric layer is exposed.
Optionally, after forming the second opening, the method further includes:
forming a passivation layer on the top metal layer and filling the first opening and the second opening; and the number of the first and second groups,
and forming a plurality of electric connecting pieces on the passivation layer, wherein one part of the electric connecting pieces penetrate through the passivation layer and are electrically connected with the top metal layer, and also penetrate through the passivation layer in the first opening and the second opening and the first interlayer dielectric layer and are electrically connected with the bottom metal layer, and the rest part of the electric connecting pieces penetrate through the passivation layer in the first opening and the second interlayer dielectric layer and are electrically connected with the middle metal layer.
Optionally, the step of forming the capacitor structure, the first opening and the second opening includes:
sequentially forming the bottom metal layer, the first interlayer dielectric layer, the middle metal layer, the second interlayer dielectric layer, the top metal layer and a patterned photoresist layer on the substrate from bottom to top, wherein the patterned photoresist layer is provided with an opening;
etching the top metal layer by taking the patterned photoresist layer as a mask to form the first opening, wherein the transverse width of the first opening is greater than that of the opening;
etching the second interlayer dielectric layer and the middle metal layer downwards along part of the first opening in sequence to form a second opening; and the number of the first and second groups,
and removing the patterned photoresist layer.
Optionally, a wet etching process is used to etch the top metal layer to form the first opening.
Optionally, the etchant for the wet etching process includes ammonia, hydrogen peroxide and deionized water.
In the metal capacitor structure and the preparation method thereof provided by the invention, the capacitor structure comprises a bottom metal layer, a first interlayer dielectric layer, a middle metal layer, a second interlayer dielectric layer and a top metal layer which are sequentially stacked on a substrate; the first openings are positioned in the top metal layer and expose the surface of the second interlayer dielectric layer; the second openings penetrate through the second interlayer dielectric layer and the middle metal layer from the bottom of part of the first openings downwards until the surface of the first interlayer dielectric layer is exposed. In the invention, the capacitance value of the metal capacitor structure is determined by the relative first interlayer dielectric layer between the bottom metal layer and the middle metal layer and the relative second interlayer dielectric layer between the middle metal layer and the top metal layer, so that the capacitance value of the metal capacitor structure can be increased by adding one second interlayer dielectric layer; and the bottom metal layer, the middle metal layer and the top metal layer are directly formed by superposition, and then are led out and connected through the electric connecting piece, so that the thickness of the metal capacitor structure can be reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a metal capacitor structure.
Fig. 2 is a schematic cross-sectional view of another metal capacitor structure.
Fig. 3 is a flowchart of a method for manufacturing a metal capacitor structure according to an embodiment of the present invention.
Fig. 4A to 4E are schematic cross-sectional views of corresponding steps in a method for manufacturing a metal capacitor structure according to an embodiment of the invention, where fig. 4E is a schematic cross-sectional view of a metal capacitor structure according to an embodiment of the invention.
Wherein the reference numerals are:
10. 100-a substrate; 21. 201-bottom metal layer; 22-interlayer dielectric layer; 23. 203-top metal layer; 30. 600-a passivation layer; 41-a first electrical connection; 42-a second electrical connection; 51-a first metal capacitor structure; 52-a second metal capacitor structure; 202-intermediate metal layer; 301-a first interlayer dielectric layer; 302-a second interlayer dielectric layer; 400-a patterned photoresist layer; 410-an opening; 510-a first opening; 520-a second opening; 710-a first plug; 720-a second plug; 730-a third plug; 810-a first pad; 820-second pad.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 4E is a schematic cross-sectional view of the metal capacitor structure provided in this embodiment. Referring to fig. 4E, the present embodiment provides a metal capacitor structure, which includes a substrate 100, a capacitor structure, a plurality of first openings, a plurality of second openings, a passivation layer 600, and a plurality of electrical connectors, wherein the capacitor structure is formed on the substrate 100, the substrate 100 includes a device structure, a metal interconnection structure, and a metal interconnection layer (not shown), and the capacitor structure is formed on the metal interconnection layer to connect the capacitor structure and the metal interconnection structure.
The capacitor structure includes a bottom metal layer 201, a first interlayer dielectric layer 301, a middle metal layer 202, a second interlayer dielectric layer 302 and a top metal layer 203 stacked on a substrate 100 in sequence. In this embodiment, the bottom metal layer 201, the middle metal layer 202, and the top metal layer 203 are made of one or more of titanium, copper, and aluminum, and may further include nitrogen, preferably, the bottom metal layer 201 is a copper-aluminum alloy, and the middle metal layer 202 and the top metal layer 203 are made of titanium nitride; the material of the first interlayer dielectric layer 301 and the second interlayer dielectric layer 302 includes one of silicon nitride, silicon oxide or silicon oxynitride, and preferably silicon nitride with a high dielectric constant is used.
A plurality of first openings are positioned in the top metal layer 203 and expose the surface of the second interlayer dielectric layer 302; second openings penetrate through the second interlayer dielectric layer 302 and the middle metal layer 202 from the bottom of part of the first openings to the bottom until the surface of the first interlayer dielectric layer 301 is exposed. To completely remove the intermediate metal layer 202 within the first opening, several second openings may also extend from the bottom of a portion of the first opening down into the first interlayer dielectric layer 301. The passivation layer 600 is located on the top metal layer 203 and fills the first opening and the second opening; the first and second openings are not labeled in the figure because the passivation layer 600 fills the first and second openings. After the passivation layer 600 is located on the top metal layer 203 and fills the first opening and the second opening, the passivation layer 600 covers the first interlayer dielectric layer 301, the middle metal layer 202, the second interlayer dielectric 302 and the top metal layer 203, and the surface of the passivation layer 600 is flat.
The plurality of electrical connectors are located on the passivation layer 600, and the plurality of electrical connectors include a plurality of first electrical connectors and a plurality of second electrical connectors, wherein the first electrical connectors penetrate through the passivation layer 600 and are electrically connected with the top metal layer 203, the first electrical connectors further penetrate through the passivation layer 600 and the first interlayer dielectric layer 301 in the first opening and the second opening and are electrically connected with the bottom metal layer 201, and the second electrical connectors penetrate through the passivation layer 600 and the second interlayer dielectric layer 302 in the first opening and are electrically connected with the middle metal layer 202. The first electric connecting piece comprises a first bonding pad 810, a plurality of first plugs 710 and a second plug 720, and the second electric connecting piece comprises a second bonding pad 820 and a plurality of third plugs 730; the first plug 710 penetrates through the passivation layer 600 and the first interlayer dielectric layer 301 in the first opening and the second opening and is electrically connected with the bottom metal layer 201, the second plug 720 penetrates through the passivation layer 600 and is electrically connected with the top metal layer 203, and the first pad 810 is electrically connected with the first plug 710 and the second plug 720 to form a first electric connector; the third plug 730 penetrates through the passivation layer 600 and the second interlayer dielectric layer 302 in the first opening and is electrically connected to the middle metal layer 202, and the second pad 820 is electrically connected to the third plug 730 to form a second electrical connection. In this embodiment, the material of the electrical connector includes any one of tungsten, aluminum, or copper, but is not limited to the above material.
The capacitance value of the metal capacitor structure is determined by the first interlayer dielectric layer 301 opposite to the bottom metal layer 201 and the middle metal layer 202 and the second interlayer dielectric layer 301 opposite to the middle metal layer 202 and the top metal layer 203, so that the capacitance value of the metal capacitor structure can be increased by adding one layer of the second interlayer dielectric layer 301; and the bottom metal layer 201, the middle metal layer 202 and the top metal layer 203 are directly formed by superposition, and the bottom metal layer 201, the middle metal layer 202 and the top metal layer 203 are led out and connected through the electric connecting piece, so that the thickness of the metal capacitor structure can be reduced.
Fig. 3 is a flowchart of a method for manufacturing a metal capacitor structure according to an embodiment of the present invention. Referring to fig. 3, the present embodiment provides a method for manufacturing a metal capacitor structure, including:
step S1: providing a substrate;
step S2: forming a capacitor structure on a substrate, wherein the capacitor structure comprises a bottom metal layer, a first interlayer dielectric layer, a middle metal layer, a second interlayer dielectric layer and a top metal layer which are sequentially stacked;
step S3: forming a plurality of first openings in the top metal layer and exposing the surface of the second interlayer dielectric layer; and the number of the first and second groups,
step S4: and forming a plurality of second openings which penetrate through the second interlayer dielectric layer and the middle metal layer from the bottom of part of the first openings downwards until the surface of the first interlayer dielectric layer is exposed.
Fig. 4A to 4E are schematic cross-sectional views of corresponding steps in the method for manufacturing the metal capacitor structure provided in this embodiment, and the method for manufacturing the metal capacitor structure provided in this embodiment is described in detail with reference to fig. 4A to 4E.
Referring to fig. 4A, step S1 is executed: providing a substrate 100, including a device structure, a metal interconnection structure and a metal interconnection layer (not shown in the figure) in the substrate 100, and subsequently forming a capacitor structure on the metal interconnection layer to connect the capacitor structure and the metal interconnection structure.
Referring to fig. 4A, step S2 is executed: a bottom metal layer 201, a first interlayer dielectric layer 301, an intermediate metal layer 202, a second interlayer dielectric layer 302, a top metal layer 203 and a patterned photoresist layer 400 are sequentially stacked from bottom to top on a substrate 100, wherein the patterned photoresist layer 400 has an opening 410. In this embodiment, the bottom metal layer 201, the middle metal layer 202, and the top metal layer 203 are made of one or more of titanium, copper, and aluminum, and may further include nitrogen, preferably, the bottom metal layer 201 is a copper-aluminum alloy, and the middle metal layer 202 and the top metal layer 203 are made of titanium nitride; the material of the first interlayer dielectric layer 301 and the second interlayer dielectric layer 302 includes one of silicon nitride, silicon oxide or silicon oxynitride, and preferably silicon nitride with a high dielectric constant is used.
Referring to fig. 4B, step S3 is executed: and etching the top metal layer 203 by using the patterned photoresist layer 400 as a mask by using a wet etching process to form a first opening 510, wherein the lateral width of the first opening 510 is greater than that of the opening 410, and after the wet etching, part of the surface of the second interlayer dielectric layer 302 is exposed by the first opening 510. In this embodiment, it is preferable that the material of the top metal layer 203 is titanium nitride, the material of the second interlayer dielectric layer 302 is silicon nitride, and the etchant used in the wet etching process includes ammonia, hydrogen peroxide and deionized water, but is not limited to the above etchant, and an etchant with a high selectivity ratio to the second interlayer dielectric layer 302 is required to be selected for the top metal layer 203 and the second interlayer dielectric layer 302 which are made of different materials, so that when the top metal layer 203 is wet etched, the influence of the etchant on the second interlayer dielectric layer 302 is reduced.
Referring to fig. 4C, step S4 is executed: sequentially etching the second interlayer dielectric layer 302 and the middle metal layer 202 downwards along the opening 410 and a part of the first opening 510 to remove the second interlayer dielectric layer 302 and the middle metal layer 202 below the opening 410 and expose the surface of the first interlayer dielectric layer 301; in order to completely remove the middle metal layer 202, the etching may be stopped in the first interlayer dielectric layer 301, that is, a part of the thickness of the first interlayer dielectric layer 301 is also etched to remove a part of the thickness of the second interlayer dielectric layer 302, the middle metal layer 202 and the first interlayer dielectric layer 301 under the opening 410 to form a second opening 520, and the second opening 520 penetrates through the second interlayer dielectric layer 302 and the middle metal layer 202 from the bottom of a part of the first opening 510 and extends into the first interlayer dielectric layer 301. Further, the patterned photoresist layer 400 is removed.
Referring to fig. 4D, after forming the second opening 520, the method further includes:
a passivation layer 600 is formed on the top metal layer 203 using chemical vapor deposition, and the passivation layer 600 fills the first and second openings. After the passivation layer 600 is located on the top metal layer 203 and fills the first opening and the second opening, the passivation layer 600 covers the first interlayer dielectric layer 301, the middle metal layer 202, the second interlayer dielectric 302 and the top metal layer 203, and the surface of the passivation layer 600 is flat. In the present embodiment, the passivation layer 600 includes silicon nitride or silicon oxide.
Referring to fig. 4E, further, forming the passivation layer 600 further includes:
a number of electrical connections are formed on the passivation layer 600 and extend through the passivation layer 600. The plurality of electrical connectors include a plurality of first electrical connectors passing through the passivation layer 600 and electrically connected to the top metal layer 203, the first electrical connectors further passing through the passivation layer 600 and the first interlayer dielectric layer 301 in the first and second openings and electrically connected to the bottom metal layer 201, and a plurality of second electrical connectors passing through the passivation layer 600 and the second interlayer dielectric layer 302 in the first opening and electrically connected to the middle metal layer 202. The first electrical connector includes a first pad 810, a plurality of first plugs 710 and a second plug 720, and the second electrical connector includes a second pad 820 and a plurality of third plugs 730. Specifically, the passivation layer 600 and the first interlayer dielectric layer 301 in the first opening and the second opening are etched to form a plurality of through holes (not shown in the figure) in the passivation layer 600 and the first interlayer dielectric layer 301, the surfaces of the bottom metal layers 201 are exposed by the plurality of through holes, and the through holes are filled with metal to form a first plug 710; etching the passivation layer 600 to form a plurality of through holes (not shown) in the passivation layer 600, the plurality of through holes exposing the surface of the top metal layer 203, and filling metal in the through holes to form second plugs 720; the passivation layer 600 and the second interlayer dielectric 302 in the first opening are etched to form a plurality of through holes (not shown) in the passivation layer 600 and the second interlayer dielectric 302, the plurality of through holes expose the surface of the middle metal layer 202, and the through holes are filled with metal to form the third plugs 730. In the present embodiment, the metal filled in the via hole includes one of tungsten, aluminum, or copper, but is not limited to the above metal. That is, the first plug 710 penetrates through the passivation layer 600 and the first interlayer dielectric layer 301 in the first opening and the second opening and is electrically connected to the bottom metal layer 201, the second plug 720 penetrates through the passivation layer 600 and is electrically connected to the top metal layer 203, and the third plug 730 penetrates through the passivation layer 600 and the second interlayer dielectric layer 302 in the first opening and is electrically connected to the middle metal layer 202.
Further, a first pad 810 and a second pad 820 are formed on the passivation layer 600, and the first pad 810 is electrically connected to the first plug 710 and the second plug 720 to form a first electrical connector; the second pad 820 is electrically connected to the third plug 730 to form a second electrical connection. In this embodiment, the material of the electrical connector includes any one of tungsten, aluminum, or copper, but is not limited to the above material.
In summary, in the metal capacitor structure and the method for manufacturing the same provided by the present invention, the capacitor structure includes a bottom metal layer, a first interlayer dielectric layer, a middle metal layer, a second interlayer dielectric layer, and a top metal layer stacked on a substrate in sequence; the first openings are positioned in the top metal layer and expose the surface of the second interlayer dielectric layer; the second openings penetrate through the second interlayer dielectric layer and the middle metal layer from the bottom of part of the first openings downwards until the surface of the first interlayer dielectric layer is exposed. In the invention, the capacitance value of the metal capacitor structure is determined by the relative first interlayer dielectric layer between the bottom metal layer and the middle metal layer and the relative second interlayer dielectric layer between the middle metal layer and the top metal layer, so that the capacitance value of the metal capacitor structure can be increased by adding one second interlayer dielectric layer; and the bottom metal layer, the middle metal layer and the top metal layer are directly formed by superposition, and then are led out and connected through the electric connecting piece, so that the thickness of the metal capacitor structure can be reduced.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (4)
1. A method for preparing a metal capacitor structure is characterized by comprising the following steps:
providing a substrate;
sequentially forming a bottom metal layer, a first interlayer dielectric layer, a middle metal layer, a second interlayer dielectric layer, a top metal layer and a patterned photoresist layer which are stacked from bottom to top on the substrate, wherein the patterned photoresist layer is provided with an opening;
etching the top metal layer by taking the patterned photoresist layer as a mask to form a first opening, wherein the transverse width of the first opening is greater than that of the opening, and the surface of the second interlayer dielectric layer is exposed by the first opening;
etching the second interlayer dielectric layer and the middle metal layer downwards along part of the first opening in sequence to form a second opening, wherein the second opening exposes the surface of the first interlayer dielectric layer; and the number of the first and second groups,
and removing the patterned photoresist layer.
2. The method of manufacturing a metal capacitor structure as claimed in claim 1, further comprising, after forming the second opening:
forming a passivation layer on the top metal layer and filling the first opening and the second opening; and the number of the first and second groups,
and forming a plurality of electric connecting pieces on the passivation layer, wherein one part of the electric connecting pieces penetrate through the passivation layer and are electrically connected with the top metal layer, and also penetrate through the passivation layer in the first opening and the second opening and the first interlayer dielectric layer and are electrically connected with the bottom metal layer, and the rest part of the electric connecting pieces penetrate through the passivation layer in the first opening and the second interlayer dielectric layer and are electrically connected with the middle metal layer.
3. The method of claim 1, wherein the top metal layer is etched using a wet etching process to form the first opening.
4. The method of claim 3, wherein the etchant used in the wet etching process comprises ammonia, hydrogen peroxide, and deionized water.
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| CN100419927C (en) * | 2003-12-03 | 2008-09-17 | 联华电子股份有限公司 | Metal-insulator-metal capacity structure and manucfacturing method thereof |
| CN1979867A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Semiconductor metal capacitor |
| KR100869751B1 (en) * | 2007-09-07 | 2008-11-21 | 주식회사 동부하이텍 | Semiconductor device and method of fabricating the same |
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