KR100955836B1 - Method for forming capacitor in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein the disclosed method for manufacturing a capacitor includes a first dielectric film, a second metal film, a second dielectric film, and a third dielectric film on a semiconductor substrate having a first metal film formed on a lower insulating film. Forming a metal film and an upper insulating film in sequence, first patterning the upper insulating film, the third metal film, the second dielectric film, and the second metal film, second patterning the upper insulating film and the third metal film; Forming an interlayer insulating film on the entire surface of the semiconductor substrate including the second patterned upper insulating film, and electrically connecting the first conductive plate and the second metal layer of the capacitor electrically connected to the first metal layer and the third metal layer in the interlayer insulating film. Forming a second conductive plate of the capacitor, wherein the capacitance can be maximized in the same area to minimize chip size, When patterning the stacked metal film and the dielectric film, since the lower metal film and the insulating film are patterned first, the upper metal film and the insulating film are patterned, so that there is an advantage that the possibility of misalignment may be eliminated during patterning.

MIM, Parallel Capacitors, Misaligned

Description

METHODS FOR FORMING CAPACITOR IN SEMICONDUCTOR DEVICE

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device capable of minimizing chip size by maximizing capacitance in the same area.

Currently, development and research of semiconductor devices for implementing high-capacity capacitors are underway in logic circuits requiring high-speed operation. In general, when the high-capacitance capacitor has a PIP (Polysilicon / Insulator / Polysilicon) structure, since the upper electrode and the lower electrode are used as conductive polysilicon, an oxidation reaction occurs at the interface between the upper and lower electrodes and the insulator film to form a natural oxide film. The disadvantage is that the size of the capacitance is reduced.

To solve this problem, the structure of the capacitor has been changed to MIM (Metal / Insulator / Metal) .The MIM capacitor has a small specific resistance and no parasitic capacitance due to depletion. Mainly used.

However, since the MIM capacitor implements a single layer capacitor composed of an upper electrode, an insulator film, and a lower electrode, even if the structure of the capacitor is changed from the PIP to the MIM structure, there is a limit in securing a high capacitance.

Accordingly, a parallel capacitor having a plurality of MIM structure capacitors in parallel connection state has been proposed.

The parallel capacitor according to the related art can secure a higher capacitance than a general MIM capacitor, but a capacitor having a new structure is required to further increase the capacitance.

In addition, when the stacked metal film and the insulating film (dielectric film) are patterned, the upper metal film and the insulating film are patterned first, and the lower metal film and the insulating film are patterned, thereby forming a photosensitive film pattern for patterning the lower metal film and the insulating film. In this case, there is a problem that misalignment may be caused in which the upper metal film and the insulating film are exposed.

The present invention has been proposed to solve such a problem, and misalignment occurs when patterning a capacitor and a stacked metal film and an insulating film (dielectric film) having a new structure capable of minimizing chip size by maximizing capacitance in the same area. A method of manufacturing a capacitor is not provided.

According to a first aspect of the present invention, a method of manufacturing a capacitor of a semiconductor device includes a first dielectric film, a second metal film, a second dielectric film, a third metal film, and an upper insulating film on a semiconductor substrate on which a first metal film is formed on a lower insulating film. Sequentially forming the first insulating film, first patterning the upper insulating film, the third metal film, the second dielectric film, and the second metal film, and second patterning the upper insulating film and the third metal film; Forming an interlayer insulating film on an entire surface of the semiconductor substrate including the second patterned upper insulating film, a first conductive plate of a capacitor electrically connected to the first metal layer and the third metal layer in the interlayer insulating film; Forming a second conductive plate of the capacitor electrically connected to the second metal layer.

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According to the present invention, it is possible to minimize the chip size by maximizing capacitance in the same area using current equipment and processes without considering equipment investment or setup of additional processes.

When the stacked metal film and the dielectric film are patterned, the lower metal film and the insulating film are patterned first, and then the upper metal film and the insulating film are patterned, thereby reducing the possibility of misalignment caused during patterning.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a cross-sectional view illustrating a structure of a semiconductor device capacitor according to the present invention.

Referring to FIG. 1, the capacitor of the present invention includes a first metal film 103 separated from the logic part metal film 102 by a lower insulating film 101, and a first dielectric formed on the first metal film 103. The film 104, the second metal film 105 formed on the first dielectric film 104, the second dielectric film 106 formed on the second metal film 105, and the second dielectric film 106. A third metal film 107 formed on the upper layer, an upper insulating film 108 formed on the third metal film 107, an interlayer insulating film 111 formed on the entire surface of the semiconductor substrate including the upper insulating film 108, The first conductive plate 117a of the capacitor formed in the interlayer insulating layer 111 and electrically connected to the first metal layer 103 and the third metal layer 107, and the second metal layer 105 formed in the interlayer insulating layer 111. And a second conductive plate 117b of the capacitor electrically connected to the.

Reference numeral 117c in the figure indicates a contact plug electrically connected to the logic metal layer 102.

The first dielectric film 104 and the second dielectric film 106 are the same thickness, and the upper insulating film 108 is the same thickness or thicker than the first dielectric film 104 and the second dielectric film 106. Preferably, the first dielectric film 104 and the second dielectric film 106 have a thickness in the range of 450-700 kHz.

According to the structure of the present invention, the capacitor by the first metal film 103 and the second metal film 105 and the capacitor by the second metal film 105 and the third metal film 107 are connected in parallel. It serves to increase the overall capacitance.

2A to 2F are cross-sectional views illustrating devices for manufacturing a capacitor of a semiconductor device according to the present invention. With reference to these cross-sectional views will be described in detail a capacitor manufacturing method according to the present invention.

As shown in FIG. 2A, the first dielectric film 104 and the second metal film (eg, the semiconductor layer 102 and the first metal film 103 are separated by the lower insulating film 101). 105, the second dielectric film 106, the third metal film 107, and the upper insulating film 108 are formed in this order. Then, the first photosensitive film pattern 109 is formed.

At this time, the first and second dielectric films 104 and 106 become the dielectric film of the MIM capacitor structure in a subsequent process, and the thinner as possible, the better the characteristics of the capacitor can be obtained. Preferably, the first and second dielectric films 104 and 106 are formed to a thickness within the range of 450 to 700 GPa and are formed to the same thickness.

The upper insulating film 108 uses a silicon nitride film (SiN) and is formed to have the same thickness or thicker than the first dielectric film 104 and the second dielectric film 106.

The first, second, and third metal films 103, 105, and 107 may be any one of aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), platinum (Pt), and tungsten (W). One metal may be used or an alloy of titanium / titanium nitride (Ti / TiN), titanium / aluminum / titanium nitride (Ti / Al / TiN), or tantalum / tantalum nitride (Ta / TaN) may be used. . Preferably, the first metal mesh 103 uses copper metal, and the second and third metal films 105 and 107 may include titanium, titanium / titanium nitride, titanium / aluminum / titanium nitride, tantalum, tantalum / Metal or alloy of any one of tantalum nitride is used.

In addition, the first and second dielectric films 104 and 106 may include an oxide nitride oxide (ONO) film, a nitride oxide (NO) film, a nitride oxide nitride (NON) film, a basr TiO ₃ (BST) film, and a PZT (Pb) film. Zr TiO ₃ ) film, tantalum pentoxide (Ta ₂ O ₅ ) film, silicon nitride film and the like can be used.

As shown in FIG. 2B, the upper insulating film 108, the third metal film 107, the second dielectric film 106, and the second metal film 105 are formed by using the first photoresist film pattern 109 as an etching mask. Etching and patterning are performed until the first dielectric film 104 is exposed. That is, the first dielectric film 104 is used as an etch stop film. After removing the first photoresist pattern 109, the second photoresist pattern 110 is formed. Here, the etching may be a dry etching or chemical dry etching (Chemical Dry Etch, CDE).

As shown in FIG. 2C, the upper insulating layer 108 and the third metal layer 107 are etched and patterned by using the second photoresist layer 110 as an etch mask until the second dielectric layer 106 is exposed. . In other words, the second dielectric film 106 is used as an etch stop film. Here, the etching may use dry etching or chemical dry etching.

After removing the second photoresist layer pattern 110, the interlayer insulation layer 111 is formed on the entire surface of the semiconductor substrate including the upper insulation layer 108, and then the surface thereof is planarized by chemical mechanical polishing or surface etching. Here, the interlayer insulating film 111 is preferably formed in a multilayer using an oxide film and a nitride film.

Next, the third photosensitive film pattern 113 is formed using a via forming mask.

As shown in FIG. 2D, the interlayer insulating film is formed such that the surface of the first dielectric film 104, the second dielectric film 106, and the upper insulating film 108 is partially exposed by using the third photoresist pattern 113 as an etching mask. Vias 111 are selectively etched to form vias, and the formed vias are buried in the sacrificial layer 114. The sacrificial layer 114 is formed by coating the photoresist so as to fill the via holes on the interlayer insulating layer 111 on which the via holes are formed, and then removing the photoresist on the interlayer insulating layer 111 by etching the entire surface.

Then, the fourth photosensitive film pattern 115 is formed using the contact forming mask.

As shown in FIG. 2E, the surface of the first metal film 103, the second metal film 105, and the third metal film 107 is partially exposed by using the fourth photosensitive film pattern 115 as a mask. The insulating layer 111, the sacrificial layer 114, the first dielectric layer 104, the second dielectric layer 106, and the upper insulating layer 108 are selectively etched to form contact holes 116. Then, the fourth photosensitive film pattern 115 is removed.

As shown in FIG. 2F, a conductive film such as a copper film or a tungsten film is embedded in the contact holes 116 to form metal wirings 117a and 117b serving as a contact plug. In this case, a contact plug 117c electrically connected to the logic unit metal film 102 is formed together. Here, the metal wires 117a and 117b are formed by depositing a conductive film on the entire upper surface of the interlayer insulating film 111 including the contact hole 116 and then planarizing the same through chemical mechanical polishing. Accordingly, the contact plug 117c is electrically connected to the logic portion metal film 102, and the metal wire 117a is electrically connected to the first metal film 103 and the third metal film 107, and the metal wire is 117b is electrically connected to the second metal film 105.

Here, the first metal film 103 and the third metal film 107 interconnected by the metal wire 117 serve as a top plate of the capacitor, and the second metal film 105 is a capacitor. It serves as the bottom conductive plate of the bottom. In addition, the capacitors of the first metal film 103 and the second metal film 105 and the capacitors of the second metal film 105 and the third metal film 107 are connected in parallel to increase the overall capacitance. do.

It has been described so far limited to one embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

1 is a cross-sectional view showing a structure of a semiconductor device capacitor according to the present invention;

2A to 2F are cross-sectional views illustrating devices for manufacturing a capacitor of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101: lower insulating film 102: logic portion metal film

103: first metal film 104: first dielectric film

105: second metal film 106: second dielectric film

107: third metal film 108: upper insulating film

109: first photosensitive film pattern 110: second photosensitive film pattern

111 interlayer insulating film 113 third photosensitive film pattern

114: sacrificial film 115: fourth photosensitive film pattern

116: contact hole 117a, 117b: metal wiring

117c: Contact Plug

Claims (9)

delete delete delete delete Sequentially forming a first dielectric film, a second metal film, a second dielectric film, a third metal film, and an upper insulating film on a semiconductor substrate on which a first metal film is formed on the lower insulating film; First patterning the upper insulating film, the third metal film, the second dielectric film, and the second metal film; Second patterning the upper insulating film and the third metal film; Forming an interlayer insulating film on an entire surface of the semiconductor substrate including the second patterned upper insulating film; Forming a first conductive plate of a capacitor electrically connected to the first metal layer and the third metal layer and a second conductive plate of the capacitor electrically connected to the second metal layer in the interlayer insulating film; Including; Forming the plate, Selectively removing the interlayer insulating layer so that the first dielectric layer, the second dielectric layer and the upper insulating layer are partially exposed to form vias, and then filling the vias with a sacrificial layer; Selectively removing the interlayer insulating film, the sacrificial film, the first dielectric film, the second dielectric film, and the upper insulating film to partially expose the first metal film, the second metal film, and the third metal film. Forming the field, Embedding a conductive layer in the contact holes to form metal wires serving as contact plugs to form the first and second conductive plates; Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 5, The filling of the sacrificial layer may include filling the vias with photoresist. Method for manufacturing capacitors in semiconductor devices. The method of claim 5, The forming of the first and second conductive plates may include forming contact plugs electrically connected to the logic part metal film. Method for manufacturing capacitors in semiconductor devices. delete delete

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