KR20040065608A - Capacitor of semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A capacitor of a semiconductor memory device and a fabricating method thereof are provided to reduce the manufacturing cost by using only one photo mask to form simultaneously a top metal line and a contact hole for a contact. CONSTITUTION: A first insulating layer(14) including a bottom electrode(40) and a first metal line(12) is formed on a semiconductor substrate. A first dielectric layer(42), a first plate electrode layer(44), a second dielectric layer(46), a second plate electrode layer(48), and an etch stopping layer(50) are laminated on the bottom electrode and the first insulating layer. The etch stopping layer and the second plate electrode layer pattern are etched by using a photo mask. A hard mask layer(52) is deposited on the second dielectric layer. The hard mask layer is partially etched. The second dielectric layer, the first plate electrode layer, and the first dielectric layer are etched by using the hard mask layer. A second insulating layer(54) is deposited on the bottom layer. A contact(56) is formed on the second plate electrode layer pattern, an opposite position to the bottom electrode, and a position close to a sidewall of the first plate electrode layer pattern. A second metal line(58) is formed on a contact forming region.

Description

Capacitor of semiconductor memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor memory device and a method of manufacturing the same. More specifically, a contact between a middle electrode formed between a double dielectric layer and a metal wiring for an upper electrode and a lower electrode is performed by a single photo-etch process. The present invention relates to a capacitor of a semiconductor memory device and a method of manufacturing the same.

In general, high integration of semiconductor memory devices requires a reduction in memory cell area, and thus a decrease in cell capacitance leads to a decrease in readability of the memory cells, making it difficult to increase the soft error rate and operate the device at low voltage. There is a problem in that the power is excessively consumed. Accordingly, highly integrated semiconductor memory devices require an increase in capacitance with respect to a unit area.

To this end, methods for increasing cell capacitance have been proposed to date, and mainly a cross-sectional image and a cylindrical structure, and methods of growing and forming HSG (hemispherical silicon grain) on these structures, etc. Various studies continue.

The growth of the above-described HSG is more than 1 gigabit (gigabit) integration, and due to the continuous decrease in the minimum line width, there is a lack of process margins, such as misalignment in the process and the gap between the capacitor electrode, bridges between capacitor electrodes of adjacent cells Cause. Such a bridge has a lot of difficulties in implementing a highly integrated memory device because it causes a pair of bit failures or multi bit failures. Therefore, at present, the present invention is directed to a method of improving the design rules of the laminated structure and the cylindrical structure.

Herein, the prior art configuration of a flat-type capacitor having a stacked structure used in the fields of analog, RF & Mixed Signal, and System-LSI will be described with reference to the accompanying drawings.

The flat type capacitor has a stacked structure according to the prior art configuration, and has a flat structure between the metal layers. Referring to FIG. 1, which shows an example configuration thereof, a manufacturing method is described below. (10) The first insulating film 14 is filled between the pad and the first metal wiring 12 to form a lower layer having a flattened top. The first dielectric layer 16, the top electrode 18, and the etch stopping layer (ESL) layer (not shown) are sequentially deposited on the lower layer thus formed, and the first dielectric layer ( 16) Patterning a region to be used as a capacitor among the layer, the upper electrode 18 layer, and the ESL layer. Subsequently, a process of depositing and covering the second insulating film 20 over the lower layer including the patterned portions of the first dielectric layer 16, the upper electrode 18, and the ESL layer and forming the upper surface of the first metal layer to flatten the first metal On the second insulating layer 20 corresponding to the pattern forming region of the wiring 12 and the upper electrode 18 layer and the upper portion of the lower electrode 10, each via hole Via using a photomask is etched at the same time. . In this case, the contact hole corresponding to the pattern formation region of the upper electrode 18 layer is formed by the ESL layer having the etching selectivity with respect to the material used as the second insulating film 20. At the same time as forming the contact hole corresponding to 12) it can be formed.

Meanwhile, another structure of the flat type capacitor having the stacked structure according to the related art is, as shown in FIG. 2, by filling the lower electrode 10 and the first metal wiring 12 and the first insulating layer 14 therebetween. A first dielectric layer 26, a middle electrode 28 layer, a second dielectric layer 30 layer, an upper electrode 32 layer, and an ESL layer (not shown) are formed on the lower layer having a flat top surface. Are deposited sequentially. Among these, the region to be used as a capacitor for the ESL layer and the upper electrode 32 layer is first patterned, and then the capacitor for the second dielectric layer 30, the intermediate electrode 28 layer, and the first dielectric layer 26 layer is used. The region to be used is patterned so as to form a step shape with respect to the above-described portion of the upper electrode 32.

Subsequently, a process of depositing and covering the second insulating film 20 on the upper portion and forming the upper surface of the second insulating layer 20 is flat, and then the pattern formation region and the lower electrode 10 of the first metal wiring 12 and the upper electrode 32 layer are described. Each contact hole using a photomask is etched simultaneously on the second insulating film 20 corresponding to the upper portion of the predetermined portion, and then the second insulating film corresponding to the predetermined portion of the intermediate electrode 28 layer described above ( 20) etching contact holes using another photomask. At this time, the contact hole corresponding to the pattern formation region of the upper electrode 32 layer has a lower selectivity as the ESL layer formed on the upper electrode 32 has an etching selectivity compared to the material used as the second insulating film 20. (10) Simultaneously with the formation of the contact hole corresponding to the portion and the first metal wiring 12, the formation thereof may be performed.

However, as described above, contact hole formation corresponding to the intermediate electrode 28 layer not only secures space for the upper electrode 32 to be formed, but also requires a range of self-forming regions, and By forming a step with respect to the etching selectivity differentiation is difficult. In addition, a separate photomask is required to form the contact hole for the intermediate electrode 28, and the cost is increased according to a separate etching process and a manufacturing requirement of the photomask.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned requirements and problems according to the prior art, by using one photomask for an upper electrode and a lower electrode and a flat intermediate electrode that is spaced apart by a dielectric film therebetween. A capacitor and a method for manufacturing the semiconductor memory device for reducing the number of photomasks and the number of labor associated with the above, and to reduce the cost and work time by allowing the formation of the upper metal wiring and contact holes for the contact at the same time will be.

1 is a cross-sectional view schematically showing a capacitor configuration of a semiconductor memory device according to the prior art.

2 is a cross-sectional view schematically showing a capacitor configuration of a semiconductor memory device having another structure according to the prior art.

3 is a cross-sectional view schematically illustrating a capacitor configuration of a semiconductor memory device according to an embodiment of the present invention.

4A to 4F are cross-sectional views illustrating a method of manufacturing a capacitor of the semiconductor memory device shown in FIG. 3.

Explanation of symbols on the main parts of the drawings

10, 40: lower electrode 12: first metal wiring

14: first insulating film 16, 26, 42: first dielectric film

18, 28, 44: first plate electrode film 20, 54: second insulating film

22, 34, 34a, 56: contacts 24, 36, 58: second metal wiring

30, 46: second dielectric film 32, 48: second plate electrode film

50: etchstopping layer 52: hardmask layer

A capacitor of a semiconductor memory device according to the present invention for achieving the above object, by sequentially depositing a first dielectric film, a first plate electrode film, and a second dielectric film on the first insulating film on which the lower electrode is formed to form a step shape with the lower electrode. An intermediate electrode pattern formed; An upper electrode pattern on which a second plate electrode film patterned to form a step shape on the middle electrode pattern is covered with a hard mask and an etch stop layer; A second insulating film covering the first insulating film including the intermediate electrode pattern and the upper electrode pattern; And a second metal wiring formed on the second insulating film, wherein the first plate electrode film forming the intermediate electrode pattern is connected to the second metal wiring by a contact penetrating through the second insulating film in contact with a side thereof. The lower electrode and the second plate electrode film may be connected to contacts corresponding to the second metal wiring on the upper side, respectively.

On the other hand, the capacitor manufacturing method of a semiconductor memory device according to the present invention for achieving the above object comprises the steps of: forming a first insulating film having a lower electrode and a first metal wiring formed on a semiconductor substrate; Sequentially stacking a first dielectric film, a first plate electrode film, a second dielectric film, a second plate electrode film, and an etch stopper layer on the lower electrode and the first insulating film; Etching to form a pattern of the etch stopping layer and the second plate electrode film using a photomask; Depositing and forming a hard mask layer over the second dielectric layer including the etch stopping layer and the second plate electrode layer pattern; Etching the hard mask layer so that a part of the hard mask layer covers the second plate electrode film pattern together with the etch stopping layer pattern; Etching the second dielectric film, the first plate electrode film, and the first dielectric film by using the hard mask layer; After depositing a second insulating film on the lower layer, a contact is applied from the upper portion to the position of the second plate electrode film pattern region, the position opposite to the lower electrode, and the position contacting the sidewall of the first plate electrode film pattern, respectively. Forming; And forming a second metal wiring on the contact forming portion.

Hereinafter, a capacitor and a method of manufacturing the semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a capacitor cell region constituting a semiconductor memory device according to an embodiment of the present invention, and FIGS. 4A to 4F are steps for explaining a capacitor manufacturing process of a semiconductor memory device according to an embodiment of the present invention. As cross-sectional views shown in order, the same reference numerals are given to the same parts as in the prior art, and detailed description thereof will be omitted.

First, a capacitor manufacturing process of a semiconductor memory device according to the present invention will be described. As shown in FIG. 4A, a first metal wire formed by a damascene method and a lower electrode 40 forming a lower electrode on a semiconductor substrate ( A first insulating film 14 having 12 formed thereon is formed. Subsequently, the first dielectric film 42, the first plate electrode film 44, and the second dielectric film 46 are sequentially formed as a film for mesa for the intermediate electrode on the top surface of the first insulating film 14 being flat. Then, the second plate electrode film 48 and the etch stopping layer 50 are sequentially stacked and formed on the film for the mesa for the upper electrode.

Subsequently, as shown in FIG. 4B, the photomask is positioned in a predetermined region with respect to the above-described etch stopping layer 50, and the remaining outer portions are etched to the extent that the second dielectric layer 46 is exposed. The etch stopping layer 50 and the second plate electrode layer 48 for forming the upper electrode of the capacitor form a mesa shape on the second dielectric layer 46. In addition, a hard mask layer 52 is laminated to a predetermined thickness on the second dielectric layer 46 including the upper electrode pattern obtained through the above-described process, and then etched back on the entire surface of the hard mask layer 52. etch-back). At this time, the hard mask layer 52 subjected to the etch back process remains as a shape surrounding the side of the second plate electrode film 48, as shown in FIG. 4C. It exists in a state covered by the remaining portions of the chipping layer 50 and the hard mask layer 52.

Thereafter, the second dielectric layer 46, the first plate electrode layer 44, and the first dielectric layer 42 are etched using the hard mask layer 52 and the etch-stopping layer 50 as a mask, thereby forming a mesa shape. The second insulating film 54 is deposited on the lower layer including the remaining portions, and the process of planarizing the upper portion of the second insulating film 54 is performed. Following this process, the photomask is used from the top of the second insulating film 54 to the sidewalls of the second plate electrode film 48 pattern region and the portion of the first plate electrode film 44 pattern facing the lower electrode 40. The contact 56 is formed in the contact position, and the process includes forming the second metal wiring 58 with respect to the contact 56 forming portion.

Here, the above-described first metal wiring 12 is made of a damascene method, and the material of the hard mask layer 52 has an etching selectivity compared to the second insulating film 54. When the insulating film 54 is made of silicon dioxide (SiO 2), the hard mask layer 52 can be used as silicon nitride (SiN).

The first metal wiring 12, the second metal wiring 58, the first plate electrode film 44, and the second plate electrode film 48 are each doped poly-Si (Doped Poly-Si), Titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), aluminum (Al), copper (Cu), ruthenium (RU), platinum (Pt), iridium (Ir) may be selected as a material combining any one or more, and these are chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and electricity, respectively. It can be formed by any one of the plating method (Electroplating). In addition, the formation temperature of the first metal wiring 12, the second metal wiring 58, the first plate electrode film 44 and the second plate electrode film 48 may be formed in a range of 25 to 500 ° C. Do. In addition, the first plate electrode film 44 and the second plate electrode film 48 described above may be formed of aluminum (Al) and ruthenium (Ru), which are materials having a good etching selectivity and low resistance with respect to the hard mask layer 52. ), And one of titanium nitride (TiN). In addition, it is preferable to use Si 3 N 4 in the above-described etch stop layer 50 having the etching selectivity with respect to the material of the second insulating film 54 made of silicon dioxide (SiO 2).

On the other hand, the contact 56 in contact with the side wall of the pattern of the first plate electrode film 44 described above has a horizontal cross-sectional shape having a rectangular shape so as to widen the contact area with respect to the side wall, and the length of the rectangular cross section in order to widen the contact area. It is effective to form the shape in which the lateral side portion is in contact with the side wall of the first plate electrode film 44. In addition, the first dielectric layer 42 and the second dielectric layer 46 may be formed of a material combining any one or more of SiO 2, Si 3 N 4, Ta 2 O 5, Al 2 O 3, HfO 2, ZrO 2, BST, PZT, and ST. It is preferable to select and use a lower level of etching selectivity than the layer 50 and the hard mask layer 52. In contrast, the etch-stopping layer 50 and the hard mask layer 52 are formed of SiN, and the first dielectric layer 42 and the second dielectric layer 46 may be a combination of any one or more of SiO 2 or Ta 2 O 5. will be. The thickness of the film deposited on the hard mask layer 52 is formed to be 300 to 1500 ∼, and the etch-stopping layer 50 is formed by etching the second insulating film 54 in the process of forming a contact hole for the contact 56. While the second plate electrode film 48 is formed to have a thickness that does not penetrate. The contact 56 formed on the lower electrode 10 is formed to have a gap enough to prevent a leakage current from the side wall of the first plate electrode film 44, and the pattern formation of the first plate electrode film 44 is formed in a first manner. The contact 56, which is in contact with the sidewall of the first plate electrode film 44, may be formed to have a gap with respect to the lower electrode 40 to prevent leakage current.

In addition, referring to the structure of the capacitor formed by the above process and conditions, as shown in FIG. 3, the contact 56 formed on the lower electrode 40 and the second plate electrode film 48 is formed on the upper second metal. The first dielectric layer 42, the first plate electrode layer 44, and the second dielectric layer 46 are electrically connected to each other by the wiring 58 and formed on the first insulating layer 14 on which the lower electrode 40 is formed. It is sequentially deposited to form the intermediate electrode pattern of the mesa structure for the electrode forming a step shape with the lower electrode 40. The second plate electrode film 48 patterned to form a step shape again on the intermediate electrode pattern formed as described above forms an upper electrode in a state covered with the hard mask layer 52 and the etch-stopping layer 50. In addition, the above-described intermediate electrode pattern and the upper electrode pattern are in a state covered by the second insulating film 54 on the first insulating film 14. The first plate electrode film 48 constituting the intermediate electrode pattern with respect to the second metal wiring 58 formed on the second insulating film 54 has a second metal wiring ( 58 is connected, and the lower electrode 40 and the second plate electrode film 48 are connected to contacts 56 corresponding to the other second metal wires 58 on the upper side, respectively.

Therefore, as described above, according to the present invention, the upper and lower electrodes and the flat metal intermediate electrodes that are spaced by the dielectric film, respectively, are formed between the upper metal wiring and the contact hole for contact using one photomask. At the same time, the number of photomasks and the number of labors thereof are reduced, thereby reducing the cost and working time.

Although the present invention has been described in detail only with respect to specific embodiments, it will be apparent to those skilled in the art that modifications and variations can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.

Claims (17)

Forming a first insulating film having a lower electrode and a first metal wiring formed on the semiconductor substrate; Sequentially stacking a first dielectric film, a first plate electrode film, a second dielectric film, a second plate electrode film, and an etch stopper layer on the lower electrode and the first insulating film; Etching to form a pattern of the etch stopping layer and the second plate electrode film using a photomask; Depositing and forming a hard mask layer over the second dielectric layer including the etch stopping layer and the second plate electrode layer pattern; Etching the hard mask layer so that a part of the hard mask layer covers the second plate electrode film pattern together with the etch stopping layer pattern; Etching the second dielectric film, the first plate electrode film, and the first dielectric film by using the hard mask layer; After depositing a second insulating film on the lower layer, a contact is applied from the upper portion to the position of the second plate electrode film pattern region, the position opposite to the lower electrode, and the position contacting the sidewall of the first plate electrode film pattern, respectively. Forming; And And forming a second metal wiring on the contact forming portion. The method of claim 1, And the first metal wiring is formed by a damascene method. The method of claim 1, The material of the hard mask is (SiN), the method of manufacturing a capacitor of the semiconductor memory device. The method of claim 1, The first metal wiring, the second metal wiring, the first plate electrode film, and the second plate electrode film are doped poly-Si, titanium (Ti), tantalum (Ta), tungsten (W), and nitride, respectively. Material combining any one or more of titanium (TiN), tantalum nitride (TaN), tungsten nitride (WN), aluminum (Al), copper (Cu), ruthenium (RU), platinum (Pt), and iridium (Ir) Capacitor manufacturing method of the semiconductor memory device, characterized in that consisting of. The method of claim 1, The first metal wiring, the second metal wiring, the first plate electrode film, and the second plate electrode film may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or electroplating. A method of manufacturing a capacitor of the semiconductor memory device, characterized in that it is made by any one of (Electroplating). The method of claim 1, The method of claim 1, wherein the first metal wiring, the second metal wiring, the first plate electrode film, and the second plate electrode film are formed at a temperature in a range of 25 ° C. to 500 ° C. 6. The method according to claim 3 or 3, The first plate electrode film and the second plate electrode film may combine any one or more of a material having a good etching selectivity with respect to the hard mask and a material having low resistance, such as aluminum (Al), ruthenium (Ru), and titanium nitride (TiN). The capacitor manufacturing method of the semiconductor memory device, characterized in that consisting of one material. The method of claim 1, And the second insulating film is SiO 2 and the etch stop layer is Si 3 N 4. The method of claim 1, The contact of the first plate electrode film pattern is in contact with the side wall of the first plate electrode film, the horizontal cross-sectional shape is formed in a rectangular shape so as to widen the contact area with respect to the side of the first plate electrode film pattern, the capacitor manufacturing method of the semiconductor memory device. The method of claim 1, And the first dielectric layer and the second dielectric layer are formed of a combination of any one or more of SiO 2, Si 3 N 4, Ta 2 O 5, Al 2 O 3, HfO 2, ZrO 2, BST, PZT, and ST. The method of claim 1, The thickness of the film deposited on the hard mask layer has a thickness of 300 to 1500Å, the capacitor manufacturing method of the semiconductor memory device. The method of claim 1, And the etch-stopping layer is formed to a thickness such that it does not penetrate the second plate electrode layer while the second insulating layer is etched during the formation of the contact hole for the contact. The method of claim 1, And wherein the etch-stopping layer and the hard mask layer are formed of SiN, and the first dielectric layer and the second dielectric layer use one or more of SiO 2 or Ta 2 O 5 in combination. The method of claim 1, And forming contacts at the lower electrodes at intervals that prevent leakage current from sidewalls of the first plate electrode film. The method of claim 1, The pattern formation of the first plate electrode film is a capacitor manufacturing method of the semiconductor memory device, characterized in that the contact in contact with the side wall of the first plate electrode film is formed at intervals to prevent the leakage current to the lower electrode. And the contact formed on the lower electrode and the second plate electrode film is connected to the upper second metal wiring. An intermediate electrode pattern forming a stepped shape with the lower electrode by sequentially depositing a first dielectric layer, a first plate electrode layer, and a second dielectric layer on the first insulating layer on which the lower electrode is formed; An upper electrode pattern on which a second plate electrode film patterned to form a step shape on the middle electrode pattern is covered with a hard mask and an etch stop layer; A second insulating film covering the first insulating film including the intermediate electrode pattern and the upper electrode pattern; And a second metal wiring formed on the second insulating film, The first plate electrode film forming the intermediate electrode pattern is connected to the second metal wiring by a contact penetrating through the second insulating film in contact with a side thereof, and the lower electrode and the second plate electrode film are formed on the other second metal of the upper part. A capacitor of a semiconductor memory device, characterized in that it is made by connecting to the corresponding contacts respectively.