CN112786595A

CN112786595A - Semiconductor memory device

Info

Publication number: CN112786595A
Application number: CN202010801948.2A
Authority: CN
Inventors: 赵基熙; 姜俊求; 李炫锡; 安相赫
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2019-11-01
Filing date: 2020-08-11
Publication date: 2021-05-11
Also published as: US11342329B2; US20220216209A1; US20210134803A1; KR20210053378A

Abstract

A semiconductor memory device is provided that includes a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom electrode and the top electrode, and an interfacial layer between the top electrode and the dielectric layer, the interfacial layer including a metal oxide and an additional component at grain boundaries of the interfacial layer.

Description

Semiconductor memory device

Korean patent application No. 10-2019-0138567, filed in the korean intellectual property office on 1/11/2019 and entitled "semiconductor memory device and method of manufacturing the same," is hereby incorporated by reference in its entirety.

Technical Field

The present disclosure relates to a semiconductor, and more particularly, to a semiconductor memory device and a method of manufacturing the same.

Background

Semiconductor devices are beneficial in the electronics industry due to their small size, versatility, and/or low manufacturing cost. In particular, with the remarkable development of the electronics industry, semiconductor devices are being highly integrated. For example, for high integration of semiconductor devices, the line width of patterns of semiconductor devices is being reduced.

Disclosure of Invention

According to some example embodiments, a semiconductor memory device may include a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom electrode and the top electrode, and an interfacial layer between the top electrode and the dielectric layer, the interfacial layer including a metal oxide and an additional component at grain boundaries of the interfacial layer.

According to some example embodiments, a semiconductor memory device may include a capacitor having a bottom electrode, a dielectric layer on the bottom electrode, a top electrode on the dielectric layer, and an upper interface layer between the dielectric layer and the top electrode. The upper interface layer may include a metal oxide and an additional component contained in the metal oxide. The additional component may have a maximum amount of about 5 at%.

According to some example embodiments, a semiconductor memory device may include a capacitor connected to a transistor on a substrate. The capacitor may include a plurality of bottom electrodes supported by a support pattern connected to sidewalls of the bottom electrodes adjacent to the support pattern, a top electrode on the bottom electrode, a dielectric layer between the top electrode and the bottom electrode, the dielectric layer extending along a surface of the bottom electrode, and an upper interface layer between the dielectric layer and the top electrode. The upper interface layer may include a metal oxide and an additional component that can be present at grain boundaries in the upper interface layer. The metal oxide may include titanium oxide (TiO)_x). The additional component may include aluminum (Al), silicon (Si), or a combination thereof.

According to some example embodiments, a method of manufacturing a semiconductor memory apparatus may include: forming a capacitor bottom electrode on a substrate; forming a capacitor dielectric layer on the capacitor bottom electrode; forming an upper interfacial layer on the capacitor dielectric layer; and forming a top electrode on the upper interfacial layer. The upper interfacial layer may include a metal oxide and an additional component doped into the metal oxide. The additional component may be capable of being present at grain boundaries of the metal oxide.

According to some example embodiments, a method of manufacturing a semiconductor memory apparatus may include: providing a substrate on which a plurality of bottom electrodes connected to each other by a support pattern are formed; forming a dielectric layer on the bottom electrode, the dielectric layer continuously extending along a surface of the bottom electrode and a surface of the support pattern; forming an upper interface layer on the dielectric layer to extend continuously along the bottom electrode and the support pattern; and forming a top electrode overlying the bottom electrode on the upper interfacial layer. The upper interface layer may include titanium oxide and an additional component that can be present at grain boundaries of the titanium oxide. The additional component may have a maximum amount of about 5 at%.

Drawings

Fig. 1A illustrates a cross-sectional view of a capacitor according to some example embodiments.

Fig. 1B illustrates a cross-sectional view of a method of forming an interfacial layer included in a capacitor, according to some example embodiments.

Fig. 1C illustrates a cross-sectional view of a method of forming an interfacial layer included in a capacitor, according to some example embodiments.

Fig. 1D illustrates a cross-sectional view of a capacitor according to some example embodiments.

Fig. 2A illustrates a plan view showing a semiconductor memory device including a capacitor according to some example embodiments.

FIG. 2B shows a cross-sectional view along line A1-A2 and line B1-B2 of FIG. 2A.

FIG. 2C shows a cross-sectional view along line A1-A2 and line B1-B2 of FIG. 2A.

Fig. 3A through 3R illustrate cross-sectional views along lines a1-a2 and B1-B2 of fig. 2A, the cross-sectional views illustrating stages in a method of manufacturing a semiconductor memory device including a capacitor according to some example embodiments.

Fig. 4A through 4C illustrate cross-sectional views along lines a1-a2 and B1-B2 of fig. 2A, the cross-sectional views illustrating stages in a method of manufacturing a semiconductor memory device including a capacitor according to some example embodiments.

Detailed Description

Fig. 1A illustrates a cross-sectional view of a capacitor according to some example embodiments. Fig. 1B illustrates a cross-sectional view of a method of forming an interfacial layer included in a capacitor, according to some example embodiments. Fig. 1C illustrates a cross-sectional view of another method of forming an interfacial layer included in a capacitor, according to some example embodiments. Fig. 1D illustrates a cross-sectional view of a capacitor according to some example embodiments.

Referring to fig. 1A, a capacitor 1 may include a bottom electrode 10, a dielectric layer 30 on the bottom electrode 10, a top electrode 50 opposite the bottom electrode 10 across the dielectric layer 30, and an interfacial layer 40 between the top electrode 50 and the dielectric layer 30. The bottom electrode 10 and the top electrode 50 may independently include one or more of an impurity-doped polysilicon layer, an impurity-doped silicon germanium layer, a metal nitride layer (e.g., a titanium nitride layer or a hafnium nitride layer), and a metal layer including a metal such as tungsten, copper, or aluminum. The dielectric layer 30 may include an oxide layer of, for example, hafnium (Hf), niobium (Nb), titanium (Ti), tantalum (Ta), zirconium (Zr), chromium (Cr), cobalt (Co), iridium (Ir), molybdenum (Mo), osmium (Os), rhenium (Re), rhodium (Rh), ruthenium (Ru), tungsten (W), vanadium (V), or any combination thereof.

The interfacial layer 40 may comprise a metal oxide and may also include additional components, such as a metal or semiconductor component. Interfacial layer 40 may have semiconductor properties. For example, interfacial layer 40 may include titanium oxide (e.g., TiO)_x) As a metal oxide, and further includes aluminum (Al), silicon (Si), or a combination thereof as an additional component. For example, the interfacial layer 40 may have AlTiO₂Or SiTiO₂The composition of (1).

The additional component of interfacial layer 40 may have an amount of about 5 at% or less based on the total amount of interfacial layer 40. The additional component may be present at the path along which the charge moves (e.g., grain boundaries) and may serve to prevent the charge from traveling along the grain boundaries of the interfacial layer 40. For this reason, the dielectric layer 30 can maintain its dielectric constant, the capacitor 1 can suppress its current leakage, and as a result, the capacitor 1 can have a high capacitance. In addition, the additional component may reinforce the grain boundaries of the interfacial layer 40, and thus may be able to significantly reduce or prevent damage to the dielectric layer 30 in a subsequent process.

The interface layer 40 may have a bulk structure or a single-layer structure. For example, the additional component may have a uniform concentration in the interfacial layer 40. In another example, the additional component may have a non-uniform concentration in interfacial layer 40. For example, when the additional component includes aluminum (Al), the aluminum may have a concentration that gradually decreases in a direction oriented from the top electrode 50 toward the dielectric layer 30.

Interfacial layer 40 may be formed as follows. The following formation is merely an example, and the present disclosure is not limited thereto.

For example, referring to fig. 1B, the interfacial layer 40 may be formed as a single layer including particles of a metal oxide and an additional constituent element. For example, the base layer 40a may be disposed on the dielectric layer 30 formed by depositing a metal oxide. A metal oxide (e.g., TiO) deposited by a deposition process (e.g., Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD)) may be deposited on the dielectric layer 30₂) To form the base layer 40 a. Next, an oxide (e.g., aluminum oxide (e.g., Al)) having an additional component may be deposited by a deposition process (e.g., Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD))₂O₃) Deposited on the base layer 40a to form an additional layer 40 b. For example, as shown in fig. 1B, the additional layer 40B may cover the entire exposed surface of the base layer 40a, e.g., to improve coverage of grain boundaries along the entire base layer 40 a. For example, during deposition of the additional layer 40b, additional components (e.g., aluminum (Al)) may diffuse into the base layer 40a, e.g., through the base layer 40a toward the dielectric layer 30. In another example, the annealing process may be separately performed to diffuse the additional component into the base layer 40 a.

Thus, the final interfacial layer 40 may be formed as a bulk structure having a concentration gradient with or without additional components present therein. For example, the final interface layer 40 may include a matrix layer 40a having an additional layer 40B in which particles are dispersed in a uniform or non-uniform distribution, e.g., the two separate layers 40a and 40B in fig. 1B are merely schematic representations of separate deposition operations and not the final interface layer 40.

In another example, aluminum (Al) may be mixed with a metal oxide (e.g., TiO)₂) While deposited on dielectric layer 30 to form a base layer 40 a. Thus, the process may form an interfacial layer 40 (i.e., a base layer 40a doped with aluminum (Al)) on the dielectric layer 30 without an additional layer 40 b.

Referring to fig. 1C, the interface layer 40 may have a multi-layer structure or a stacked structure in which at least one first layer 41 and at least one second layer 42 are alternately and repeatedly deposited on the dielectric layer 30. First layer 41 and second layer 42 may have different compositions from each other or the same or similar compositions.

In some embodiments, first layer 41 may be formed by depositing a metal oxide (e.g., TiO)₂) Second layer 42 may be formed by depositing, for example, an aluminum-containing material (e.g., Al)₂O₃AlN, AlC, or any combination thereof). For example, the lowermost first layer 41 may be adjacent to or in contact with the dielectric layer 30 and the uppermost second layer 42 may be adjacent to or in contact with the top electrode 50. In another example, the lowermost first layer 41 and the uppermost first layer 41 may be adjacent to or in contact with the dielectric layer 30 and the top electrode 50, respectively. In yet another example, the lowermost second layer 42 and the uppermost second layer 42 may be adjacent to or in contact with the dielectric layer 30 and the top electrode 50, respectively. In yet another example, the lowermost second layer 42 may be adjacent to or in contact with the dielectric layer 30 and the uppermost first layer 41 may be adjacent to or in contact with the top electrode 50. In some embodiments, first layer 41 and second layer 42 may be formed by depositing titanium aluminum oxide (e.g., TiAlO). For example, each of first layer 41 and second layer 42 may be deposited by a deposition process, e.g., first layer 41 and second layer 42 may completely cover each other.

Referring to fig. 1D, the capacitor 1 may further include an interfacial layer 20 (hereinafter, referred to as a lower interfacial layer) between the dielectric layer 30 and the bottom electrode 10 in addition to the interfacial layer 40 (hereinafter, referred to as an upper interfacial layer) between the top electrode 50 and the dielectric layer 30. Lower interface layer 20 may be formed by the same or similar method used to form upper interface layer 40.

Lower interface layer 20 may have the same or similar structure as upper interface layer 40. For example, the lower interface layer 20 may include a metal oxide (e.g., TiO)_x) And also includes additional components such as a metal component (e.g., aluminum (Al)) or a semiconductor component (e.g., silicon (Si)). The additional component may have an amount of about 5 at% or less of the total amount of the lower interface layer 20, and may prevent charges from moving through grain boundaries of the lower interface layer 20, for example, since the grain boundaries of the lower interface layer 20 impart crystallinity to the dielectric layer 30 to improve the dielectric constant and to completely separate between the dielectric layer 30 and the bottom electrode 10.

For example, lower interface layer 20 may be formed the same as or similar to interface layer 40 discussed with reference to fig. 1B, thereby having a bulk structure. The additional component may have a constant or gradually decreasing or increasing concentration in the direction oriented from the dielectric layer 30 towards the bottom electrode 10. For example, in each of the upper and lower interface layers 40, 20, the additional component may have a concentration that gradually decreases in a downward direction from the top electrode 50 toward the bottom electrode 10, e.g., according to a diffusion profile of the additional component that is thermally controlled during the deposition or annealing process. In another example, the additional component may have a concentration that gradually decreases in the downward direction in upper interface layer 40 and gradually increases in the downward direction in lower interface layer 20.

In another example, the lower interface layer 20 may be formed the same as or similar to the interface layer 40 discussed with reference to fig. 1C, thereby having a laminated structure. The description with reference to fig. 1C may apply equally or similarly to the lower interface layer 20. Thus, upper interface layer 40 and lower interface layer 20 may have the same structure or mirror image, e.g., symmetry, with respect to dielectric layer 30.

Fig. 2A illustrates a plan view of a semiconductor memory device including a capacitor according to some example embodiments. Fig. 2B illustrates a cross-sectional view along lines a1-a2 and B1-B2 of fig. 2A, according to some example embodiments. Fig. 2C illustrates a cross-sectional view along lines a1-a2 and B1-B2 of fig. 2A, according to some other example embodiments.

Referring to fig. 2A and 2B, a substrate 301 may be provided therein with a device isolation pattern 302 defining an active portion ACT. The substrate 301 may be a semiconductor substrate. Each active portion ACT may have an isolation shape, for example, an island shape. Each of the active portions ACT may have a strip shape elongated in the third direction D3 when viewed in a plan view. The active portion ACT may correspond to a portion of the substrate 301 surrounded by the device isolation pattern 302 when viewed in a plan view. The substrate 301 may include a semiconductor material. The active portions ACT may be arranged parallel to each other in the third direction D3, and one of the active portions ACT may have an end adjacent to a central portion of an adjacent one of the active portions ACT.

The word line WL may extend across the active portion ACT. The word lines WL may be disposed in the corresponding grooves GR formed on the device isolation pattern 302 and the active portion ACT. The word lines WL may be parallel to the first direction D1 crossing the third direction D3. The word lines WL may include a conductive material. A gate dielectric layer 307 may be disposed between the word line WL and the inner surface of the groove GR. The gate dielectric layer 307 may comprise, for example, one or more of thermal oxide, silicon nitride, silicon oxynitride, and high-k dielectric. Each of the word lines WL may have a curved bottom surface.

The first impurity region 312a may be disposed in a center of each active portion ACT between a pair of word lines WL (right side of fig. 2B), and a pair of second impurity regions 312B may be disposed in opposite edge portions of each active portion ACT (left side of fig. 2B). The first impurity region 312a and the second impurity region 312b may be doped with, for example, N-type impurities. The first impurity region 312a may correspond to a common drain region, and the second impurity region 312b may correspond to a source region. Each word line WL and its adjacent first and

second impurity regions

312a and 312b may constitute a transistor.

The word lines WL may have their top surfaces lower than the top surface of the active ACT, for example, the distance between the bottom surface of the substrate 301 and the top surfaces of the word lines WL may be smaller than the distance between the bottom surface of the substrate 301 and the top surface of the active ACT. The word line cover pattern 310 may be disposed on each word line WL (e.g., a top surface of the word line WL). The word line capping patterns 310 may have their linear shapes extending along the longitudinal direction of the word lines WL, and may cover the top surfaces of the word lines WL. The word line capping pattern 310 may be formed of, for example, a silicon nitride layer.

An interlayer dielectric pattern 305 may be disposed on the substrate 301. The interlayer dielectric pattern 305 may be formed of a single layer or a multi-layer structure including, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The interlayer dielectric pattern 305 may be formed to have an island shape spaced apart from each other when viewed in a plan view. The interlayer dielectric pattern 305 may cover both ends of two adjacent active portions ACT.

The substrate 301, the device isolation pattern 302, and the upper portion of the word line capping pattern 310 may be partially recessed to provide the first recess R1. The first recess R1 may have a net shape when viewed in a plan view. The bit line BL may be disposed on the interlayer dielectric pattern 305. The bit lines BL may extend across the word line capping pattern 310 and the word lines WL.

As disclosed in fig. 2A, the bit line BL may extend in a second direction D2 crossing the first direction D1 and the third direction D3. Each of the bit lines BL may include a polysilicon pattern 330, an ohmic pattern 331, and a metal-containing pattern 332, which are sequentially stacked.

The polysilicon pattern 330 may include, for example, impurity-doped polysilicon or impurity-undoped polysilicon. The ohmic pattern 331 may include a metal silicide. The metal-containing pattern 332 may include one or more of a metal (e.g., tungsten, titanium, or tantalum) and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride). The bit line overlay patterns 337 may be disposed on the corresponding bit lines BL. The bit line overlay pattern 337 may include a dielectric material, for example, silicon nitride.

The bit line contact DC may be disposed in the first recess R1 intersecting the bit line BL. The bit line contact DC may include, for example, impurity-doped polysilicon or impurity-undoped polysilicon. The bit line contact DC may be electrically coupled to the first impurity region 312a, and may electrically connect the first impurity region 312a to the bit line BL.

The buried dielectric pattern 341 may be disposed in a portion of the first recess R1, the portion not occupied by the bit line contact DC. The buried dielectric pattern 341 may have a single layer or a multi-layer structure including, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

As shown in fig. 2A, a plurality of storage node contacts BC may be disposed between a pair of adjacent bit lines BL. The plurality of storage node contacts BC may be spaced apart from each other. The storage node contact BC may include, for example, impurity-doped polysilicon or impurity-undoped polysilicon. The storage node contacts BC may have their concave top surfaces.

Between the bit line BL and the storage node contact BC, there may be bit line spacers including a first spacer 321 and a second spacer 325 spaced apart from each other on both sides of the air gap AG. The first spacer 321 may cover sidewalls of the bit line BL and sidewalls of the bit line cover pattern 337. The second spacer 325 may be adjacent to the storage node contact BC. The first and

second spacers

321 and 325 may include the same material. For example, the first and

second spacers

321 and 325 may include silicon nitride.

The second spacer 325 may have a bottom surface lower than that of the first spacer 321, for example, a distance between the bottom surface of the substrate 301 and the bottom surface of the second spacer 325 may be smaller than a distance between the bottom surface of the substrate 301 and the bottom surface of the first spacer 321. The second spacer 325 may have a top end having a level lower than that of the top end of the first spacer 321, for example, a distance between the bottom surface of the substrate 301 and the top surface of the second spacer 325 may be smaller than a distance between the bottom surface of the substrate 301 and the top surface of the first spacer 321. Accordingly, it may be possible to increase a margin for forming the bonding pad LP, which will be discussed below, thereby preventing disconnection between the bonding pad LP and the storage node contact BC. The first spacer 321 may extend to cover the sidewall of the bit line contact DC and the sidewall and bottom surface of the first recess R1.

The storage node ohmic layer 309 may be disposed on the storage node contact BC. The storage node ohmic layer 309 may include, for example, a metal silicide. The storage node ohmic layer 309, the first spacer 321, the second spacer 325, and the bit line overlay pattern 337 may be covered by the diffusion break pattern 311 a. The diffusion interruption pattern 311a may include a metal nitride, for example, titanium nitride or tantalum nitride. The bonding pad LP may be disposed on the diffusion interruption pattern 311 a. The bonding pad LP may include a metal-containing material, for example, tungsten. The bonding pad LP may have an upper portion covering the top surface of the bit line overlay pattern 337 and have a width greater than that of the storage node contact BC (e.g., in a top view in fig. 2A).

As shown in fig. 2A, the center of the bonding pad LP may be offset from the center of the storage node contact BC along the first direction D1. A portion of the bit line BL may vertically overlap the bonding pad LP. One upper sidewall of the bit line cover pattern 337 may overlap the bonding pad LP and may be covered by the third spacer 327. The second recess R2 may be formed on the other upper sidewall of the bit line cover pattern 337, for example, the bit line cover pattern 337 may be located between the second recess R2 and the third spacer 327 in the first direction D1 (left side of fig. 2A).

The first overlay patterns 358a may be disposed between adjacent bonding pads LP. The first cover pattern 358a may have a linear shape, and may have an interior filled with the second cover pattern 360 a. The first and

second cover patterns

358a and 360a may independently include, for example, a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a porous layer. The first overlay pattern 358a may have a porosity greater than that of the second overlay pattern 360 a.

The air gap AG between the first and

second spacers

321 and 325 may extend into the space between the bonding pads LP. The air gap AG may expose a bottom surface of the first cover pattern 358 a. The air gap AG may extend toward the diffusion breaking pattern 311 a. For example, the diffusion break pattern 311a may be recessed between the bonding pad LP and the bit line overlay pattern 337.

The bottom electrodes BE may BE disposed on the corresponding bonding pads LP. The bottom electrode BE may include one or more of a metal nitride layer (e.g., an impurity-doped polysilicon layer or a titanium nitride layer) and a metal layer (e.g., a tungsten layer, an aluminum layer, or a copper layer). The bottom electrode BE may have a cylindrical shape, a hollow cylindrical shape, or a cup shape. The support patterns 374a may BE disposed between adjacent bottom electrodes BE, supporting the bottom electrodes BE. The support pattern 374a may include a dielectric material, for example, silicon nitride, silicon oxide, or silicon oxynitride.

Between the bottom electrodes BE, the first and

second cover patterns

358a and 360a may BE covered by an etch stop layer 370. Etch stop layer 370 may comprise a dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride. The dielectric layer DL may cover a surface of each of the bottom electrode BE, the support pattern 374a, and the etch stop layer 370. The dielectric layer DL may be covered by the top electrode TE. The interface layer IFt may be disposed between the dielectric layer DL and the top electrode TE. The top electrode TE may include, for example, one or more of an impurity-doped polysilicon layer, an impurity-doped silicon germanium layer, a metal nitride layer such as a titanium nitride layer, and a metal layer including tungsten, aluminum, or copper. The capacitor CAP may BE composed of a bottom electrode BE, a dielectric layer DL, an interface layer IFt, and a top electrode TE. Accordingly, the semiconductor memory device 1000 including the capacitor CAP may be provided.

The bottom electrode BE, dielectric layer DL, interface layer IFt, and top electrode TE of the capacitor CAP may correspond to the bottom electrode 10, dielectric layer 30, interface layer 40, and top electrode 50 of fig. 1A, respectively. The explanations of the interface layer 40 discussed with reference to fig. 1A to 1C apply equally or similarly to the interface layer IFt in fig. 2B. For example, the interfacial layer IFt may include a metal oxide (e.g., TiO)_x) And also includes an additional metal component (e.g., aluminum (Al)) or a semiconductor component (e.g., silicon (Si)). The additional component may have an amount of about 5 at% or less of the total amount of the interface layer IFt. The interface layer IFt may have a bulk structure in which the additional component has a uniform or non-uniform concentration. Alternatively, the interface layer IFt may have a laminated structure having a stacked structure of a plurality of layers of the same composition or different compositions.

In another example, as shown in fig. 2C, an interfacial layer IFb may also BE disposed between the bottom electrode BE and the dielectric layer DL. Interface layer IFb may correspond to interface layer 20 of fig. 1D. The description of interface layer 20 in fig. 1D applies equally or similarly to interface layer IFb.

Referring to fig. 3A, a device isolation pattern 302 may be formed in a substrate 301, thereby defining an active portion ACT. For example, a trench TR may be formed in the substrate 301, and the trench TR may be filled with a dielectric material to form the device isolation pattern 302. The active portion ACT and the device isolation pattern 302 may be etched to form a groove GR. Each of the grooves GR may have a curved bottom surface. The substrate 301 may be a semiconductor substrate, for example, a silicon wafer.

Word lines WL may be formed in the corresponding grooves GR. A pair of word lines WL may extend across the active portion ACT. Before forming the word lines WL, a gate dielectric layer 307 may be formed on the inner surface of each of the grooves GR. The gate dielectric layer 307 may be formed by a thermal oxidation process, a chemical vapor deposition process, and/or an atomic layer deposition process. The groove GR may be filled with a conductive layer deposited on the substrate 301, and then an etch-back process or a chemical mechanical polishing process may be performed to form the word line WL in the groove GR. The word lines WL may be recessed to have their top surfaces lower than the top surface of the active portion ACT. The groove GR may be filled with a dielectric layer (e.g., a silicon nitride layer) formed on the substrate 301, and then the dielectric layer may be planarized to form a word line capping pattern 310 on the corresponding word line WL.

The word line capping pattern 310 and the device isolation pattern 302 may be used as a mask to implant impurities into the active portion ACT. Therefore, the first impurity region 312a and the second impurity region 312b can be formed in the active portion ACT. The first impurity region 312a and the second impurity region 312b may have their conductivity types different from that of the substrate 301. For example, when the substrate 301 has P-type conductivity, each of the first impurity region 312a and the second impurity region 312b may have N-type conductivity.

Referring to fig. 3B, an interlayer dielectric pattern 305 and a polysilicon mask pattern 330a may be formed on the substrate 301. For example, a dielectric layer and a first polysilicon layer may be sequentially formed on the substrate 301. The first polysilicon layer may be patterned to form a polysilicon mask pattern 330 a. The polysilicon mask pattern 330a may be used as an etch mask to etch the dielectric layer, the device isolation pattern 302, the substrate 301, and the word line capping pattern 310 to form the first recesses R1 and the interlayer dielectric pattern 305. The interlayer dielectric pattern 305 may have a plurality of island shapes spaced apart from each other. The plurality of first recesses R1 may have a net shape, for example, a matrix pattern, when viewed in a plan view. The first recess R1 may expose the first impurity region 312 a.

Referring to fig. 3C, a second polysilicon layer 329 may be formed on the substrate 301 so as to fill the first recess R1. Then, the second polysilicon layer 329 may be subjected to a planarization process to remove the second polysilicon layer 329 on the polysilicon mask pattern 330a and expose the polysilicon mask pattern 330 a.

An ohmic layer 331a, a metal containing layer 332a, and a capping layer 337a may be sequentially formed on the polysilicon mask pattern 330a and the second polysilicon layer 329. The ohmic layer 331a may be formed of a metal silicide (e.g., cobalt silicide). A metal layer may be deposited on the polysilicon mask pattern 330a and the second polysilicon layer 329 and then an annealing process may be performed to form the ohmic layer 331 a. The annealing process may react the metal layer with the polysilicon mask pattern 330a and the second polysilicon layer 329, thereby forming a metal silicide. The unreacted metal layer may be removed.

A first mask pattern 339 defining a planar shape of a bit line BL to be discussed below may be formed on the capping layer 337 a. The first mask pattern 339 may extend in a second direction D2 shown in fig. 2A.

Referring to fig. 3D, an etching process in which the first mask pattern 339 is used as an etch mask may be performed to sequentially etch the capping layer 337a, the metal-containing layer 332a, the ohmic layer 331a, the polysilicon mask pattern 330a, and the second polysilicon layer 329 to form the bit line BL, the bit line contact DC, and the bit line capping pattern 337. The bit line BL may include a polysilicon pattern 330, an ohmic pattern 331, and a metal-containing pattern 332. The etching process may partially expose the top surface of the interlayer dielectric pattern 305, and may also partially expose the inner sidewalls and the bottom surface of the first recess R1. The first mask pattern 339 may be removed after the bit line BL and the bit line contact DC are formed.

Referring to fig. 3E, a first spacer layer may be conformally formed on the substrate 301. The first spacer layer may conformally cover the bottom surface and the inner sidewalls of the first recess R1. The first spacer layer may be, for example, a silicon nitride layer. The first recess R1 may be filled with a dielectric layer (e.g., a silicon nitride layer) formed on the substrate 301, and then the dielectric layer may be anisotropically etched to leave the buried dielectric pattern 341 in the first recess R1. When the anisotropic etching process is performed, the first spacer layer may also be etched to form the first spacers 321.

A sacrificial spacer layer may be conformally formed on the substrate 301, and then an anisotropic etching process may be performed to form a sacrificial spacer 323 covering sidewalls of the first spacer 321. The sacrificial spacer 323 may include a material having an etch selectivity with respect to the first spacer 321. The sacrificial spacer 323 may be formed of, for example, a silicon oxide layer.

The second spacer 325 may be formed to cover the sidewall of the sacrificial spacer 323. The second spacers 325 may be formed of, for example, a silicon nitride layer. The second impurity region 312b may be exposed after the sacrificial spacer 323 or the second spacer 325 is formed.

Referring to fig. 3F, the space between the plurality of bit lines BL may be filled with a polysilicon layer formed on the substrate 301, and then the polysilicon layer may be etched to form an initial storage node contact 350 and expose upper portions of the first spacer 321, the sacrificial spacer 323, and the second spacer 325. The upper portions of the sacrificial spacer 323 and the second spacer 325 may be removed such that the top surfaces of the sacrificial spacer 323 and the second spacer 325 are substantially coplanar, e.g., along a plane that is inclined relative to the bottom surface of the substrate 301, and their tips are at the same or similar level as the level of the top surface of the initial storage node contact 350. Accordingly, the first spacer 321 may be exposed at an upper portion thereof.

This process may increase a process margin for forming the bonding pad LP, which will be discussed below. When the upper portions of the sacrificial spacer 323 and the second spacer 325 are removed, the upper portion of the first spacer 321 may also be partially removed such that the first spacer 321 has a remaining upper portion having a small width along the first direction D1, for example, a portion extending along sidewalls of the bit line capping pattern 337 above the sacrificial spacer 323 and the second spacer 325.

Referring to fig. 3G, a third spacer layer may be conformally formed on the substrate 301 and then anisotropically etched to form a third spacer 327 covering sidewalls of the exposed upper portion of the first spacer 321. A third spacer 327 may cover the exposed top end of the sacrificial spacer 323. The initial storage node contact 350 may be etched to expose an upper portion of the second spacer 325 and also form a storage node contact BC. The third spacer 327 may reinforce a damaged upper portion of the first spacer 321 (e.g., cover the damaged upper portion of the first spacer 321 in a reinforcing pattern) and may cover the sacrificial spacer 323, thereby serving to prevent the bit line BL from being damaged, e.g., deteriorated, by an etchant for etching the storage node contact BC and a cleaning solution used in a subsequent cleaning process. Therefore, the bit line BL can be protected from damage.

The storage node ohmic layer 309 may be formed on the storage node contact BC, and the diffusion break layer 311 may be conformally formed on the substrate 301. A bonding pad layer 352 may be formed on the substrate 301, and the bonding pad layer 352 may fill a space between the bit line cover patterns 337. Bond pad layer 352 may be, for example, a tungsten layer. A second mask pattern 340 may be formed on the bonding pad layer 352. The second mask pattern 340 may be formed of, for example, an Amorphous Carbon Layer (ACL). The second mask pattern 340 may define the position of the bonding pad LP, which will be discussed below. The second mask pattern 340 may be formed to vertically overlap the storage node contact BC.

Referring to fig. 3H, an anisotropic etching process in which the second mask pattern 340 is used as an etching mask may be performed to remove a portion of the bonding pad layer 352. Accordingly, the bonding pad LP may be formed, and the opening 354 may be formed to expose the diffusion interruption layer 311.

Referring to fig. 3I, an isotropic etching process in which the diffusion break layer 311 exposed to the opening 354 is patterned may be performed to form diffusion break patterns 311a separated from each other and simultaneously expose portions of the top surfaces of the third spacers 327 and the bit line cover patterns 337. The diffusion interruption pattern 311a may be over-etched to partially expose the bottom surface of the bonding pad LP according to the progress degree of the isotropic etching process.

Referring to fig. 3J, an anisotropic etching process may be performed to remove the portion of the bit line cover pattern 337 exposed to the opening 354 and also remove the third spacer 327, with the result that the sacrificial spacer 323 may be exposed. In this case, the second recess R2 may be formed on the bit line overlay pattern 337. Thereafter, the second mask pattern 340 may be removed.

Referring to fig. 3K, an isotropic etching process in which the sacrificial spacer 323 is removed may be performed to form an air gap AG between the first and

second spacers

321 and 325. After that, the thermal decomposition layer 356 may be formed to fill the opening 354 and the second recess R2. A thermal decomposition layer 356 may also be formed on the bonding pad LP. The thermal decomposition layer 356 may close the upper portion of the air gap AG.

Referring to fig. 3L, a first annealing process may be performed to thermally decompose and remove an upper portion of the thermal decomposition layer 356. Partially removing the thermal decomposition layer 356 may expose the top surface and the upper sidewall of the bonding pad LP, and may form thermal decomposition patterns 356a spaced apart from each other. A first capping layer 358 may be conformally formed on the thermal decomposition pattern 356a and the bonding pad LP.

Referring to fig. 3M, a second annealing process may be performed to thermally decompose the thermal decomposition pattern 356 a. The thermal decomposition pattern 356a that has been thermally decomposed may be degassed by the first cover layer 358. Accordingly, the air gap AG may be expanded from a space between the first and

second spacers

321 and 325 into a space between the bonding pads LP. A second cladding layer 360 may be formed on the first cladding layer 358.

Referring to fig. 3N, an etch back process or a chemical mechanical polishing process in which the first and second capping layers 358 and 360 are planarized may be performed to form first and

second capping patterns

358a and 360a confined between the bonding pads LP. The planarization may remove portions of the first and second overcoat layers 358 and 360 from the bonding pad LP, and thus the bonding pad LP may be exposed.

An etch stop layer 370 may be formed on the bonding pad LP, the first cover pattern 358a, and the second cover pattern 360 a. A first molding layer 372, a support layer 374, and a second molding layer 376 may be formed on the etch stop layer 370. The etch stop layer 370 and the support layer 374 may be formed of, for example, a silicon nitride layer. The first and second molding layers 372 and 376 may be formed of a material having an etch selectivity with respect to the support layer 374. For example, the first and second molding layers 372 and 376 may be formed of a silicon oxide layer.

Referring to fig. 3O, the second molding layer 376, the support layer 374, the first molding layer 372, and the etch stop layer 370 may be sequentially patterned to form electrode holes EH exposing the bonding pads LP. A conductive layer may BE formed to fill the electrode hole EH, and then an etch-back process or a chemical mechanical polishing process may BE performed to remove the conductive layer on the second molding layer 376 and also form the bottom electrode BE in the electrode hole EH. A third mask pattern 378 may be formed on the second molding layer 376. The third mask pattern 378 may have a plurality of openings 378 h. The opening 378h may expose the top surface of the adjacent bottom electrodes BE and also expose the second molding layer 376 between the adjacent bottom electrodes BE.

Referring to fig. 3P, an anisotropic etching process in which the third mask pattern 378 is used as an etching mask may be performed to remove the second molding layer 376 exposed to the opening 378h and also remove the support layer 374 under the second molding layer 376. Accordingly, the support pattern 374a may be formed, and the first molding layer 372 under the opening 378h may be exposed.

Referring to fig. 3Q, the third mask pattern 378 may be removed to expose the second molding layer 376. An isotropic etching process in which the first and second molding layers 372 and 376 are all removed may BE performed to expose surfaces of the bottom electrode BE, the support pattern 374a, and the etch stop layer 370.

Referring to fig. 3R, a dielectric layer DL may BE formed on an exposed surface of the bottom electrode BE. In this case, the dielectric layer DL may also be formed on the exposed surfaces of the support patterns 374a and the etch stop layer 370. The interface layer IFt may be formed on the dielectric layer DL. The interface layer IFt may correspond to the interface layer 40 discussed with reference to fig. 1A to 1C.

FIGS. 1A to 1The description of the interface layer 40 in 1C applies equally or similarly to the interface layer IFt. For example, the interfacial layer IFt may include a metal oxide (e.g., TiO)_x) And also includes an additional metal component (e.g., aluminum (Al)) or a semiconductor component (e.g., silicon (Si)). The additional component may have an amount of about 5 at% or less based on the total amount of the interface layer IFt.

The interface layer IFt may have a bulk structure in which the additional component has a uniform or non-uniform concentration. Alternatively, the interface layer IFt may have a laminated structure including a stacked structure of a plurality of layers having the same composition or different compositions.

Referring back to fig. 2B, a top electrode TE may BE formed on the interface layer IFt, covering the bottom electrode BE. Accordingly, the semiconductor memory device 1000 may BE fabricated with a capacitor CAP having a bottom electrode BE, a top electrode TE, a dielectric layer DL between the bottom electrode BE and the top electrode TE, and an interface layer IFt between the top electrode TE and the dielectric layer DL.

The capacitor CAP may correspond to the capacitor 1 of fig. 1A. The description of the capacitor 1 in fig. 1A to 1C applies equally or similarly to the capacitor CAP. For example, as discussed above with reference to fig. 1A, charge can be prevented from moving across the grain boundaries of the interface layer IFt, and thus the capacitor 1 can have a high capacitance.

Referring to fig. 4A, the surface of the bottom electrode BE may BE exposed through the processes discussed in fig. 3A to 3Q. An interfacial layer IFb may BE formed on the exposed surface of the bottom electrode BE. In this case, the interface layer IFb may also be formed on the exposed surface of the support pattern 374a and the exposed surface of the etch stop layer 370. When the interface layer IFb is formed, the component of the interface layer IFb can diffuse into the bottom electrode BE. Thus, a portion of bottom electrode BE may become interface layer IFb. In another example, the deposition conditions may BE controlled such that the interface layer IFb is deposited on the bottom electrode BE at a relatively high rate and the interface layer IFb is deposited on the support pattern 374a and the etch stop layer 370 at a relatively low rate.

Interfacial layer IFb may have a non-uniform thickness due to differences in diffusion rate or deposition rate. For example, the interface layer IFb may have a first thickness T1 on the bottom electrode BE, a second thickness T2 on the support pattern 374a, and a third thickness T3 on the etch stop layer 370. The second thickness T2 may be less than the first thickness T1, and the third thickness T3 may be less than the first thickness T1 and the same as or similar to the second thickness T2.

Interface layer IFb may correspond to interface layer 20 discussed above with reference to fig. 1D. The description of interface layer 20 of fig. 1D applies equally or similarly to interface layer IFb. For example, the interfacial layer IFb may include a metal oxide (e.g., TiO)_x) And also includes an additional metal component (e.g., aluminum (Al)) or a semiconductor component (e.g., silicon (Si)). The additional component may have an amount of about 5 at% or less based on the total amount of the interfacial layer IFb, and may prevent charge from moving across the grain boundaries of the interfacial layer IFb. Interface layer IFb may have a bulk structure in which the additional component has a uniform or non-uniform concentration. Alternatively, the interface layer IFb may have a laminated structure in which a plurality of layers having the same composition or different compositions are stacked.

Referring to fig. 4B, an etch process may be performed to remove a portion of interfacial layer IFb. When the interface layer IFb has a semiconductor property, adjacent bottom electrodes BE may BE electrically connected to each other. Accordingly, the interface layer IFb may be partially removed on the support patterns 374a and the etch stop layer 370, for example, the interface layer IFb may include discontinuous portions separated by the support patterns 374 a. In some embodiments, the etching process may be performed without an etch mask.

As described above, since the interface layer IFb has a relatively large thickness (e.g., T1) on the bottom electrode BE and a relatively small thickness (e.g., T2 and T3) on the support pattern 374a and the etch stop layer 370, the interface layer IFb may remain on the bottom electrode BE even if the etching process is performed without an etching mask.

Referring to fig. 4C, a dielectric layer DL may be formed on the interface layer IFb, and an interface layer IFt may be formed on the dielectric layer DL. The dielectric layer DL may cover the interface layer IFb, the support pattern 374a, and the etch stop layer 370. The dielectric layer DL corresponds to the dielectric layer 30 of fig. 1A. The description of the dielectric layer 30 of fig. 1A applies equally or similarly to the dielectric layer DL. The dielectric layer DL may include an oxide layer of hafnium (Hf), niobium (Nb), titanium (Ti), tantalum (Ta), zirconium (Zr), chromium (Cr), cobalt (Co), iridium (Ir), molybdenum (Mo), osmium (Os), rhenium (Re), rhodium (Rh), ruthenium (Ru), tungsten (W), vanadium (V), or any combination thereof.

The interface layer IFt corresponds to the interface layer 40 discussed with reference to fig. 1A to 1C. The description of the interface layer 40 in fig. 1A to 1C applies equally or similarly to the interface layer IFt. For example, the interfacial layer IFt may include a metal oxide (e.g., TiO)_x) And also includes an additional metal component (e.g., aluminum (Al)) or a semiconductor component (e.g., silicon (Si)). The additional component may have an amount of about 5 at% or less based on the total amount of the interface layer IFt, and may prevent charges from moving through grain boundaries of the interface layer IFt. The interface layer IFt may have a bulk structure in which the additional component has a uniform or non-uniform concentration. Alternatively, the interface layer IFt may have a laminated structure in which a plurality of layers having the same composition or different compositions are stacked.

Referring back to fig. 2C, a top electrode TE may BE formed on the interface layer IFt, covering the bottom electrode BE. Accordingly, the semiconductor memory device 1000 may BE fabricated with a capacitor CAP including a bottom electrode BE, a top electrode TE, a dielectric layer DL between the bottom electrode BE and the top electrode TE, an interface layer IFb between the bottom electrode BE and the dielectric layer DL, and an interface layer IFt between the top electrode TE and the dielectric layer DL.

By way of summary and review, as the design rules of semiconductor memory devices, such as Dynamic Random Access Memories (DRAMs), decrease, the surface of the capacitor may decrease, thereby resulting in a decreased capacitance. Therefore, even if the semiconductor memory device is highly integrated, the capacitor needs to have an improved structure to reliably obtain high capacitance.

Accordingly, example embodiments provide a semiconductor memory device having increased reliability and a method of manufacturing the same. Example embodiments also provide a semiconductor memory device having a high capacitance and a method of manufacturing the same.

That is, example embodiments provide a semiconductor memory device having a capacitor with a dielectric layer having an interface thereon, the interface including a metal oxide (e.g., TiO) doped with an additional component (e.g., aluminum)₂) To reinforce the interface (e.g. TiO)₂) Grain boundaries, thereby improving the barrier/leakage characteristics of the interface. Accordingly, damage to the dielectric layer is substantially minimized or prevented in subsequent processes, thereby maintaining a high capacitance of the capacitor and substantially minimizing or preventing leakage in the dielectric layer.

Example embodiments have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, as will be apparent to those of ordinary skill in the art upon submission of the present application, unless specifically stated otherwise. It will therefore be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising:

a capacitor, comprising: a bottom electrode and a top electrode; a dielectric layer between the bottom electrode and the top electrode; and a first interfacial layer between the top electrode and the dielectric layer, the first interfacial layer comprising a first metal oxide and a first additive component located at grain boundaries of the first interfacial layer.

2. The semiconductor memory device of claim 1, wherein the first metal oxide comprises titanium oxide and the first additive composition comprises aluminum, silicon, or a combination thereof.

3. The semiconductor memory device according to claim 1, wherein the first additive composition has a uniform or non-uniform concentration in the first interface layer.

4. The semiconductor memory device according to claim 1, wherein in the first interface layer, the first additional component has a concentration gradually decreasing in a direction oriented from the top electrode toward the dielectric layer.

5. The semiconductor memory device according to claim 1, wherein the first additional component has an amount of 5 at% or less based on a total amount of the first interface layer.

6. The semiconductor memory device according to claim 1, wherein the first interface layer has a stacked structure of first layers and second layers which are alternately stacked, the first layers including the first metal oxide, and the second layers including the first additional component.

7. The semiconductor memory device of claim 6, wherein one of the first layers in the stacked structure is adjacent to the dielectric layer and one of the second layers in the stacked structure is adjacent to the top electrode.

8. The semiconductor memory device according to any one of claims 1 to 5, wherein the capacitor further comprises a second interface layer located between the bottom electrode and the dielectric layer, the second interface layer comprising a second metal oxide and a second additional component located at grain boundaries of the second interface layer.

9. The semiconductor memory device according to claim 8, wherein:

in the first interface layer, the first additional component has a concentration that decreases in a direction oriented from the top electrode towards the bottom electrode, and

in the second interface layer, the second additional component has a concentration that decreases in a direction oriented from the top electrode toward the bottom electrode.

10. The semiconductor memory device according to claim 8, wherein:

in the second interface layer, the second additional component has a concentration that increases in a direction oriented from the top electrode toward the bottom electrode.

11. The semiconductor memory device according to claim 8, wherein the second interface layer and the first interface layer are symmetrical with respect to the dielectric layer.

12. A semiconductor memory device, the semiconductor memory device comprising:

a capacitor, comprising: a bottom electrode; a dielectric layer on the bottom electrode; a top electrode on the dielectric layer; and an upper interface layer between the dielectric layer and the top electrode, the upper interface layer including a first metal oxide and a first additional component contained in the first metal oxide, the first additional component having a maximum amount of 5 at% based on a total amount of the upper interface layer.

13. The semiconductor memory device according to claim 12, wherein the first metal oxide comprises titanium oxide and the first additive composition comprises aluminum.

14. The semiconductor memory device according to any one of claims 12 to 13, wherein:

the capacitor further includes a lower interface layer between the bottom electrode and the dielectric layer, and

the lower interface layer includes a second metal oxide and a second additional component contained in the second metal oxide, the second additional component being located at a grain boundary of the lower interface layer and having a maximum amount of 5 at% based on a total amount of the lower interface layer.

15. The semiconductor memory device according to claim 14, wherein:

in the upper interface layer, the first additional component has a concentration that decreases in a direction oriented from the top electrode towards the bottom electrode, and

in the lower interface layer, the second additional component has a concentration that decreases or increases in a direction oriented from the top electrode towards the bottom electrode.

16. The semiconductor memory device according to claim 14, wherein:

the upper interface layer has a laminated structure including first layers and second layers alternately stacked, the first layers including a first metal oxide, the second layers including a first additional component, and

the lower interface layer has a laminated structure including first layers and second layers alternately stacked, the first layers including a second metal oxide, and the second layers including a second additive component.

17. A semiconductor memory device, the semiconductor memory device comprising:

a capacitor on the substrate, the capacitor comprising: a bottom electrode, the support pattern connecting sidewalls of adjacent ones of the bottom electrodes; a top electrode on the bottom electrode; a dielectric layer; a dielectric layer located between the top electrode and the bottom electrode, the dielectric layer extending along a surface of the bottom electrode; and an upper interface layer between the dielectric layer and the top electrode, the upper interface layer comprising titanium oxide and a first additive component located at grain boundaries of the upper interface layer, the first additive component comprising aluminum, silicon, or a combination thereof; and

and a transistor connected to the capacitor.

18. The semiconductor memory device according to claim 17, wherein the first additional component has a maximum amount of 5 at% based on a total amount of the upper interface layer.

19. The semiconductor memory device of claim 17, wherein the upper interface layer extends continuously over the bottom electrode and continuously along the top electrode.

20. The semiconductor memory device according to any one of claims 17 to 19, wherein the capacitor further comprises a lower interface layer between the dielectric layer and each bottom electrode,

wherein the lower interface layer comprises additional titanium oxide and a second additional component located at grain boundaries of the lower interface layer, the second additional component comprising a maximum of 5 at% of aluminum, silicon, or a combination thereof, based on the total amount of the lower interface layer.