US20230017348A1 - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
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- US20230017348A1 US20230017348A1 US17/932,817 US202217932817A US2023017348A1 US 20230017348 A1 US20230017348 A1 US 20230017348A1 US 202217932817 A US202217932817 A US 202217932817A US 2023017348 A1 US2023017348 A1 US 2023017348A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 24
- 239000010936 titanium Substances 0.000 claims description 24
- 229910044991 metal oxide Inorganic materials 0.000 claims description 18
- 150000004706 metal oxides Chemical class 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 13
- 229910052719 titanium Inorganic materials 0.000 claims description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium(II) oxide Chemical compound [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims 3
- 229910052746 lanthanum Inorganic materials 0.000 claims 3
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims 3
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 claims 3
- 239000003990 capacitor Substances 0.000 abstract description 19
- 239000010410 layer Substances 0.000 description 164
- 229910052751 metal Inorganic materials 0.000 description 88
- 239000002184 metal Substances 0.000 description 88
- 150000004767 nitrides Chemical class 0.000 description 21
- 238000003860 storage Methods 0.000 description 14
- 230000000052 comparative effect Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- 229910002938 (Ba,Sr)TiO3 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H01L27/10805—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
Abstract
A semiconductor memory device includes a capacitor on a substrate. The capacitor includes a first electrode, a second electrode on the first electrode, and a dielectric layer between the first electrode and the second electrode. The second electrode includes a first layer, a second layer, and a third layer. The first layer is adjacent to the dielectric layer, and the third layer is spaced apart from the first layer with the second layer interposed therebetween. A concentration of nickel in the third layer is higher than a concentration of nickel in the first layer.
Description
- This application is a continuation of U.S. patent application Ser. No. 17/029,238, filed Sep. 23, 2020, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0018102, filed Feb. 14, 2020, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.
- Embodiments of the inventive concepts relate to a semiconductor memory device.
- Semiconductor devices are widely used in an electronic industry because of their small sizes, multi-functional characteristics, and/or low manufacturing costs. However, semiconductor devices have become more highly integrated with the development of the electronic industry. Widths of patterns included in semiconductor devices have been reduced to increase the integration density of semiconductor devices. In particular, reduction of leakage current of a capacitor may be required to increase the integration density of a semiconductor memory device such as DRAM.
- Embodiments of the inventive concepts may provide a semiconductor memory device with improved reliability.
- In some embodiments, a semiconductor memory device may include a capacitor on a substrate. The capacitor may include a first electrode, a second electrode on the first electrode, the second electrode including a first layer, a second, layer, and a third layer, and a dielectric layer between the first electrode and the second electrode. The first layer may be adjacent to the dielectric layer, and the third layer may be spaced apart from the first layer with the second layer interposed therebetween. A concentration of nickel in the third layer may be higher than a concentration of nickel in the first layer.
- In some embodiments, a semiconductor memory device may include a capacitor on a substrate. The capacitor may include a first electrode, a second electrode on the first electrode, the second electrode including a first layer including an A-metal and nitrogen, a second layer, and a third layer including a B-metal, and a dielectric layer between the first electrode and the second electrode. The first layer may be adjacent to the dielectric layer, and the third layer may be spaced apart from the first layer with the second layer interposed therebetween. A work function of the B-metal may be greater than a work function of a nitride of the A-metal.
- In some embodiments, a semiconductor memory device may include a substrate, transistors on the substrate, lower electrodes on the transistors, a support pattern in physical contact with sidewalls of the lower electrodes, a dielectric layer on surfaces of the lower electrodes and a surface of the support pattern, and an upper electrode on the dielectric layer. Each of the lower electrodes may include an A-metal nitride. The upper electrode may include an A-metal, nitrogen, and a B-metal.
- The inventive concepts will become more apparent in view of the attached drawings and accompanying detailed description.
-
FIG. 1 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments of the inventive concept. -
FIGS. 2 and 3 are cross-sectional views illustrating a method of manufacturing the semiconductor memory device ofFIG. 1 according to some embodiments of the inventive concept. -
FIG. 4 is a graph showing leakage current amounts of semiconductor memory devices according to some embodiments of the inventive concept. -
FIG. 5 is a graph showing a capacitance and a leakage current according to a thickness and a material of an upper electrode according to some embodiments of the inventive concept. -
FIG. 6 is a plan view illustrating a semiconductor memory device according to some embodiments of the inventive concepts. -
FIG. 7 is a cross-sectional view taken along lines A-A′ and B-B′ ofFIG. 6 . -
FIG. 8 is an enlarged view of a portion CC′ ofFIG. 7 . - Hereinafter, embodiments of the inventive concepts will be described in more detail with reference to the accompanying drawings.
-
FIG. 1 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments of the inventive concept. - Referring to
FIG. 1 , asemiconductor memory device 1000 according to some embodiments may include a first electrode BE, a second electrode UE, a dielectric layer DL, and a metal oxide layer MO, which are disposed or arranged on asubstrate 100. The second electrode UE may be disposed or arranged on the first electrode BE. The dielectric layer DL may be disposed or arranged between the first electrode BE and the second electrode UE. The metal oxide layer MO may be disposed or arranged between the dielectric layer DL and the second electrode UE. The first electrode BE, the second electrode UE, the dielectric layer DL and the metal oxide layer MO in combination may constitute a capacitor. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. - The
substrate 100 may be a single-crystalline silicon substrate or a silicon-on-insulator (SOI) substrate. Even though not shown in the drawings, an interlayer insulating layer, a transistor, a contact plug and an interconnection line may be disposed or arranged between thesubstrate 100 and the first electrode BE. - The first electrode BE may be referred to as a lower electrode. The first electrode BE may include a poly-silicon layer doped with dopants, a silicon-germanium layer doped with dopants, a metal nitride layer (e.g., a titanium nitride layer), and/or a metal layer (e.g., tungsten, copper, or aluminum). As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. For example, the first electrode BE may be a layer formed of titanium nitride.
- The dielectric layer DL may include silicon oxide, a metal oxide (e.g., hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and/or titanium oxide), and/or a dielectric material having a perovskite structure (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and/or PLZT).
- The metal oxide layer MO may include a metal oxide, for example, titanium oxide (TiOx).
- The second electrode UE may be referred to as an upper electrode. A thickness TK of the second electrode UE may be about 500 Å or less. For example, the thickness TK of the second electrode UE may be about 100 Å. The second electrode UE may include an A-metal, nitrogen, and a B-metal.
- The second electrode UE may include a
first layer 31, asecond layer 32, and athird layer 33. Thefirst layer 31 may be disposed or arranged adjacent to the metal oxide layer MO. Thethird layer 33 may be disposed or arranged on thefirst layer 31 with thesecond layer 32 interposed therebetween. A top surface of thefirst layer 31 may be in physical contact with a bottom surface of thesecond layer 32. A top surface of thesecond layer 32 may be in physical contact with a bottom surface of thethird layer 33. - Concentrations of the A-metal and the nitrogen in the
first layer 31 may be highest in the second electrode UE. As used herein, the concentrations may be expressed as an atomic percent (at %). - The B-metal may not exist in the
first layer 31 or may have a concentration much lower than the concentration of the A-metal in thefirst layer 31. The concentration of the A-metal of thefirst layer 31 may be substantially constant throughout thefirst layer 31. - A concentration of the B-metal in the
third layer 33 may be highest in the second electrode UE. The A-metal and the nitrogen may not exist in thethird layer 33 or may have concentrations much lower than the concentration of the B-metal in thethird layer 33. The concentration of the B-metal of thethird layer 33 may be substantially constant throughout thethird layer 33. The concentration of the B-metal in thethird layer 33 may be about 100 at % per unit volume. - A thickness of the
third layer 33 may be greater than 0 Å and equal to or less than 50 Å. For example, the thickness of thethird layer 33 may be about 30 Å. In some embodiments, the thickness of thethird layer 33 may be adjusted differently from the above value. - The
second layer 32 may include the A-metal, the nitrogen, and the B-metal. A concentration of the A-metal in a portion of thesecond layer 32 close to thefirst layer 31 may be higher than a concentration of the A-metal in another portion of thesecond layer 32 close to thethird layer 33. A concentration of the B-metal in a portion of thesecond layer 32 close to thethird layer 33 may be higher than a concentration of the B-metal in another portion of thesecond layer 32 close to thefirst layer 31. - A concentration of the A-metal of the
second layer 32 may decrease from thefirst layer 31 toward thethird layer 33. A concentration of the B-metal of thesecond layer 32 may increase from thefirst layer 31 toward thethird layer 33. In other words, a concentration gradient of the A-metal of thesecond layer 32 and a concentration gradient of the B-metal of thesecond layer 32 may have different signs from each other. - The concentration of the A-metal in the
first layer 31 may be equal to or greater than the concentration of the A-metal in thesecond layer 32. The concentration of the A-metal in thefirst layer 31 may be greater than the concentration of the A-metal in thethird layer 33. The concentration of the B-metal in thethird layer 33 may be equal to or greater than the concentration of the B-metal in thesecond layer 32. The concentration of the B-metal in thethird layer 33 may be greater than the concentration of the B-metal in thefirst layer 31. - The B-metal may not exist at an interface between the second electrode UE and the metal oxide layer MO.
- The A-metal and the B-metal may include different metals from each other. The B-metal may be a metal of which a work function is greater than a work function of a nitride of the A-metal (i.e., a work function of an A-metal nitride). A difference between the work function of the B-metal and the work function of the A-metal nitride may be 0.5 eV or more.
- The work function is an energy value needed to remove an electron in a material from a Fermi level to a point in the vacuum and constitutes a property of the material. For example, the A-metal may be titanium, the A-metal nitride may be titanium nitride, and the B-metal may be nickel. A work function of the titanium nitride may range from about 4.30 eV to about 4.65 eV, and a work function of the nickel may range from about 5.04 eV to about 5.35 eV.
- Because the second electrode UE includes the B-metal having the relatively greater work function as compared with a case in which the second electrode UE is formed of only the A-metal nitride, an effective work function value of the second electrode UE may be increased. The effective work function may be a parameter determined (or adjusted) based on the kinds of materials of the second electrode UE, a shape of the second electrode UE, and/or a process of manufacturing the second electrode UE. The effective work function may be related to a leakage current in driving of the capacitor.
-
FIGS. 2 and 3 are cross-sectional views illustrating a method of manufacturing the semiconductor memory device ofFIG. 1 according to some embodiments of the inventive concepts. - Referring to
FIG. 2 , asubstrate 100 may be prepared. A first electrode BE may be formed on thesubstrate 100. The first electrode BE may be formed by, for example, an atomic layer deposition (ALD) method. - A dielectric layer DL and a metal oxide layer MO may be sequentially formed on the first electrode BE. The dielectric layer DL and the metal oxide layer MO may be formed by an ALD method.
- An
A-metal nitride layer 31 a may be formed on the metal oxide layer MO. For example, theA-metal nitride layer 31 a may be a titanium nitride layer. A thickness W1 of theA-metal nitride layer 31 a may be about 50 Å or less. For example, the thickness W1 of theA-metal nitride layer 31 a may be about 50 Å. TheA-metal nitride layer 31 a may be formed by an ALD method. - Referring to
FIG. 3 , a B-metal layer 33 a may be formed on theA-metal nitride layer 31 a. The B-metal layer 33 a may be, for example, a nickel layer. A thickness W2 of the B-metal layer 33 a may be about 50 Å or less. For example, the thickness W2 of the B-metal layer 33 a may be about 30 Å. The B-metal layer 33 a may be formed by an ALD method. - Referring again to
FIG. 1 , an annealing process may be performed. An A-metal and nitrogen in theA-metal nitride layer 31 a may be diffused toward the B-metal layer 33 a, and a B-metal in the B-metal layer 33 a may be diffused toward theA-metal nitride layer 31 a. - An intermediate layer including the A-metal, the nitrogen and the B-metal may be formed between the
A-metal nitride layer 31 a and the B-metal layer 33 a by the diffusion of the A-metal, the nitrogen, and the B-metal. TheA-metal nitride layer 31 a, the intermediate layer, and the B-metal layer 33 a after completion of the annealing process may correspond to afirst layer 31, asecond layer 32 and athird layer 33, respectively. Thus, a second electrode UE including thefirst layer 31, thesecond layer 32 and thethird layer 33 may be formed. - Techniques capable of reducing a thickness of an upper electrode of a capacitor are being studied to increase integration density of semiconductor memory devices. When the thickness of the upper electrode of the capacitor is varied in a range of several nanometers to hundreds nanometers, an effective work function of the upper electrode may likewise be varied. When the thickness of the upper electrode is reduced, a capacitance of the capacitor may be increased, but the effective work function may be reduced to cause an increase in leakage current of the capacitor.
- However, according to some embodiments of the inventive concept, a total thickness of the upper electrode may be reduced, and the effective work function of the upper electrode may be increased by depositing the nickel layer having a work function greater than that of titanium nitride on the titanium nitride layer and performing the annealing process. A capacitance of the capacitor according to some embodiments of the inventive concept may be increased by the reduction in the total thickness of the upper electrode, and the effective work function may also be increased to reduce a leakage current of the capacitor.
-
FIG. 4 is a graph showing leakage current amounts of semiconductor memory devices according to some embodiments of the inventive concept. In particular,FIG. 4 shows the amounts of leakage current measured when a driving voltage of 1V is applied to two different semiconductor memory devices. - An experimental example 1 is a semiconductor memory device including an upper electrode formed by forming a nickel layer on a titanium nitride layer and then performing an annealing process. A comparative example 1 is a semiconductor memory device including an upper electrode formed of only a titanium nitride layer. Leakage currents of the experimental example 1 and the comparative example 1 were measured. In
FIG. 4 , a horizontal axis represents an equivalent oxide thickness (EOT), and a vertical axis represents a measured amount of the leakage current. - Referring to
FIG. 4 , under the driving voltage, the amount of the leakage current of the comparative example 1 increases as the EOT decreases. The amount of the leakage current of the experimental example 1 is less than the amount of the leakage current of the comparative example 1 even though the EOT of the experimental example 1 is less than that of the EOT of the comparative example 1. -
FIG. 5 is a graph showing a capacitance and a leakage current according to a thickness and a material of an upper electrode of a capacitor according to some embodiments of the inventive concept. - Nickel (Ni) layers of 30 Å, 50 Å and 70 Å were deposited on titanium nitride (TiN) layers in experimental examples A1, A2 and A3, respectively. Platinum (Pt) layers of 30 Å, 50 Å and 70 Å were deposited on titanium nitride (TiN) layers in comparative examples B1, B2 and B3, respectively. Aluminum (Al) layers of 30 Å, 50 Å and 70 Å were deposited on titanium nitride (TiN) layers in comparative examples C1, C2 and C3, respectively. In a comparative example D, only titanium nitride (TiN) was used as a material of an upper electrode and a thickness of the upper electrode was varied in a range of 30 Å to 50 Å.
- Referring to
FIG. 5 , capacitances of the experimental examples A1 to A3 are greater than capacitances of the comparative examples B1 to B3, C1 to C3, and D. In addition, the amount of the leakage current of the experimental example A2 is less than those of other experimental examples and the comparative examples. - A detailed example of a semiconductor memory device including the upper electrode configured according to some embodiments of the inventive concept will be described hereinafter.
FIG. 6 is a plan view illustrating a semiconductor memory device according to some embodiments of the inventive concepts.FIG. 7 is a cross-sectional view taken along lines A-A′ and B-B′ ofFIG. 6 .FIG. 8 is an enlarged view of a portion CC′ ofFIG. 7 . - Referring to
FIGS. 6 and 7 , adevice isolation pattern 302 may be disposed in asubstrate 301 to define active portions ACT. Each of the active portions ACT may have an isolated shape when viewed in a plan view of the semiconductor memory device. Each of the active portions ACT may have a bar shape extending in a first direction X1 when viewed in a plan view of the semiconductor memory device. Each of the active portions ACT may correspond to a portion of thesubstrate 301, which is surrounded or bordered by thedevice isolation pattern 302 when viewed in a plan view of the semiconductor memory device. - The
substrate 301 may include a semiconductor material. The active portions ACT may be arranged in parallel to each other in the first direction X1, and an end portion of one active portion ACT may be disposed or arranged adjacent to a center of another active portion ACT neighboring the one active portion ACT. - Word lines WL may intersect the active portions ACT. The word lines WL may be disposed or arranged in grooves formed in the
device isolation pattern 302 and the active portions ACT. The word lines WL may be parallel to a second direction X2 intersecting the first direction X1. The word lines WL may be formed of a conductive material. Agate dielectric layer 307 may be disposed or arranged between each of the word lines WL and an inner surface of each of the grooves. Even though not shown in the drawings, bottoms of the grooves may be relatively deep in thedevice isolation pattern 302 and may be relatively shallow in the active portions ACT. Thegate dielectric layer 307 may include a thermal oxide, silicon nitride, silicon oxynitride, and/or a high-k dielectric material. Bottom surfaces of the word lines WL may be rounded. - A first
doped region 312 a may be disposed or arranged in each of the active portions ACT between a pair of the word lines WL, and a pair of seconddoped regions 312 b may be disposed or arranged in both edge regions of each of the active portions ACT, respectively. The first and seconddoped regions - The first
doped regions 312 a may correspond to a common drain region, and the seconddoped regions 312 b may correspond to source regions. Each of the word lines WL and the first and seconddoped regions - Top surfaces of the word lines WL may be lower than top surfaces of the active portions ACT in the cross-sectional view of
FIG. 7 . Wordline capping patterns 310 may be disposed or arranged on the word lines WL, respectively. The wordline capping patterns 310 may have line shapes extending in a longitudinal direction of the word lines WL and may be on and fully cover the top surfaces of the word lines WL. The wordline capping patterns 310 may be in and at least partially fill the grooves on the word lines WL. The wordline capping patterns 310 may be formed of, for example, silicon nitride. - An interlayer insulating
pattern 305 may be disposed or arranged on thesubstrate 301. The interlayerinsulating pattern 305 may be formed of a single or multi-layer structure including a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer. The interlayerinsulating pattern 305 may be on and at least partially cover end portions of two active portions ACT adjacent to each other. - Upper portions of the
substrate 301, thedevice isolation pattern 302, and the wordline capping pattern 310 may be partially recessed to form a first recess region R1. The first recess region R1 may have a mesh shape when viewed in a plan view. A sidewall of the first recess region R1 may be aligned with a sidewall of the interlayer insulatingpattern 305. - Bit lines BL may be disposed or arranged on the
interlayer insulating pattern 305. The bit lines BL may intersect the wordline capping patterns 310 and the word lines WL. As illustrated inFIG. 6 , the bit lines BL may be parallel to a third direction X3 intersecting the first and second directions X1 and X2. - Each of the bit lines BL may include a bit line poly-
silicon pattern 330, a bit lineohmic pattern 331, and a bit line metal-containingpattern 332, which are sequentially stacked. The bit line poly-silicon pattern 330 may include poly-silicon, which may or may not be doped with dopants. The bit lineohmic pattern 331 may include a metal silicide layer. The bit line metal-containingpattern 332 may include a metal (e.g., tungsten, titanium, and/or tantalum) and/or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride). A bitline capping pattern 337 may be disposed or arranged on each of the bit lines BL. The bitline capping patterns 337 may be formed of an insulating material, such as silicon nitride. - Bit line contacts DC may be disposed or arranged in the first recess region R1 intersecting the bit lines BL. The bit line contacts DC may include poly-silicon, which may or may not be doped with dopants. In the cross-sectional view taken along the line B-B′ of
FIG. 7 , a sidewall of the bit line contact DC may be in physical contact with a sidewall of the interlayer insulatingpattern 305. - In the plan view of
FIG. 6 , the sidewall of the bit line contact DC, which is in physical contact with the interlayer insulatingpattern 305, may be concave. The bit line contact DC may electrically connect the firstdoped region 312 a to the bit line BL. - A lower
filling insulation pattern 341 may be disposed or arranged in the first recess region R1, which does not include the bit line contact DC. The lowerfilling insulation pattern 341 may be formed of a single or multi-layer structure including a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer. - Storage node contacts BC may be disposed or arranged between a pair of the bit lines BL adjacent to each other. The storage node contacts BC may be spaced apart from each other. The storage node contacts BC may include poly-silicon, which may or may not be doped with dopants. Top surfaces of the storage node contacts BC may be concave. An insulating pattern (not shown) may be disposed or arranged between the storage node contacts BC between the bit lines BL.
- A bit line spacer SP may be disposed or arranged between the bit line BL and the storage node contact BC. The bit line spacer SP may include a
first sub-spacer 321 and asecond sub-spacer 325, which are spaced apart from each other by a gap region GP. The gap region GP may be referred to as an air gap region. Thefirst sub-spacer 321 may be on and at least partially cover a sidewall of the bit line BL and a sidewall of the bitline capping pattern 337. Thesecond sub-spacer 325 may be adjacent to the storage node contact BC. Thefirst sub-spacer 321 and thesecond sub-spacer 325 may include the same material. For example, thefirst sub-spacer 321 and thesecond sub-spacer 325 may include silicon nitride. - A bottom surface of the
second sub-spacer 325 may be lower than a bottom surface of thefirst sub-spacer 321 in the cross-sectional view ofFIG. 7 . A height of a top end of thesecond sub-spacer 325 may be lower than a height of a top end of thefirst sub-spacer 321 in the cross-sectional view ofFIG. 7 . Thus, a margin of forming a landing pad LP may be increased, and disconnection between the landing pad LP and the storage node contact BC may be prevented or the risk thereof reduced. - The
first sub-spacer 321 may extend to be on and at least partially cover a sidewall of the bit line contact DC and a sidewall and a bottom surface of the first recess region R1. Thefirst sub-spacer 321 may be disposed or arranged between the bit line contact DC and the lowerfilling insulation pattern 341, between the wordline capping pattern 310 and the lowerfilling insulation pattern 341, between thesubstrate 301 and the lowerfilling insulation pattern 341, and between thedevice isolation pattern 302 and the lowerfilling insulation pattern 341. - A storage
node ohmic layer 309 may be disposed or arranged on the storage node contact BC. The storagenode ohmic layer 309 may include a metal silicide. Adiffusion barrier pattern 311 a may conformally be on and at least partially cover the storagenode ohmic layer 309, the first andsecond sub-spacers line capping pattern 337. Thediffusion barrier pattern 311 a may include a metal nitride, such as titanium nitride or tantalum nitride. A landing pad LP may be disposed or arranged on thediffusion barrier pattern 311 a. The landing pad LP may be formed of a metal-containing material, such as tungsten. An upper portion of the landing pad LP may be on and at least partially cover a top surface of the bitline capping pattern 337 and may have a width greater than that of the storage node contact BC. A center of the landing pad LP may be offset from a center of the storage node contact BC in the second direction X2. A portion of the bit line BL may vertically overlap the landing pad LP in the cross-sectional view ofFIG. 7 . One upper sidewall of the bitline capping pattern 337 may overlap the landing pad LP and may be at least partially covered with athird sub-spacer 327. - A second recess region R2 may be formed at another upper sidewall of the bit
line capping pattern 337. - A
first capping pattern 358 a may be on and at least partially cover upper sidewalls of adjacent landing pads LP and may connect the adjacent landing pads LP to each other. Thefirst capping pattern 358 a may have a substantially uniform thickness. - The
first capping pattern 358 a may have a liner shape, and a space surrounded or bordered thereby may be at least partially filled with asecond capping pattern 360 a. Each of the first andsecond capping patterns first capping pattern 358 a may be greater than a porosity of thesecond capping pattern 360 a. Top surfaces of the first andsecond capping patterns - The gap region GP between the first and
second sub-spacers first capping pattern 358 a may be exposed by the gap region GP. The gap region GP may extend toward thediffusion barrier pattern 311 a. A sidewall of thediffusion barrier pattern 311 a may be recessed between the landing pad LP and the bitline capping pattern 337. The top surface of the bitline capping pattern 337 and a bottom surface of the landing pad LP may be partially exposed by the gap region GP. - Lower electrodes BE may be disposed or arranged on the landing pads LP, respectively. The lower electrode BE may include poly-silicon doped with dopants, a metal nitride (e.g., titanium nitride), and/or a metal (e.g., tungsten, aluminum, or copper). The lower electrode BE may have a solid cylinder shape or a hollow cylinder or cup shape. A
support pattern 374 a may be disposed between upper sidewalls of the lower electrodes BE adjacent to each other. Thesupport pattern 374 a may include an insulating material, such as silicon nitride, silicon oxide, and/or silicon oxynitride. Asupport hole 374 h may at least partially expose sidewalls of the lower electrodes BE adjacent to each other. - The top surfaces of the first and
second capping patterns etch stop layer 370 thereon and be at least partially covered by theetch stop layer 370. For example, theetch stop layer 370 may include an insulating material, such as silicon nitride, silicon oxide, and/or silicon oxynitride. A dielectric layer DL may be on and at least partially cover surfaces of the lower electrodes BE and a surface of thesupport pattern 374 a. - Referring to
FIGS. 7 and 8 , an upper electrode UE may be disposed or arranged on the dielectric layer DL. A metal oxide layer MO may be disposed between the dielectric layer DL and the upper electrode UE. The upper electrode UE ofFIGS. 7 and 8 may be the same as or similar to the upper electrode (second electrode UE) described with reference toFIG. 1 . - According to some embodiments of the inventive concepts, because the upper electrode of the capacitor includes nickel (Ni), the leakage current of the capacitor may be reduced and the capacitance of the capacitor may be increased. As a result, a semiconductor memory device with improved reliability may be realized.
- While the inventive concepts have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirits and scopes of the inventive concepts. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scopes of the inventive concepts are to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.
Claims (20)
1. A semiconductor device comprising:
a substrate;
a first electrode on the substrate;
a dielectric insulating film on the first electrode; and
a second electrode on the dielectric insulating film, the second electrode including a first layer,
wherein the first electrode is pillar-shaped and includes titanium nitride (TiN) and silicon (Si),
the dielectric insulating film includes hafnium (Hf), zirconium (Zr) and aluminum (Al), and
the first layer of the second electrode includes nickel (Ni).
2. The semiconductor device of claim 1 , wherein the dielectric insulating film includes at least one of silicon (Si), titanium (Ti), lanthanum (La), or tantalum (Ta).
3. The semiconductor device of claim 1 , wherein the dielectric insulating film includes silicon (Si).
4. The semiconductor device of claim 1 , wherein the dielectric insulating film includes titanium (Ti).
5. The semiconductor device of claim 1 , wherein the dielectric insulating film includes silicon (Si) and titanium (Ti).
6. The semiconductor device of claim 1 , wherein the second electrode includes a second layer between the dielectric insulating film and the first layer of the second electrode, and a third layer between the second layer of the second electrode and the first layer of the second electrode,
the second layer of the second electrode includes titanium nitride (TiN), and
the third layer of the second electrode includes nickel (Ni), titanium (Ti) and nitrogen (N).
7. The semiconductor device of claim 1 , further comprises a metal oxide film between the dielectric insulating film and the second electrode,
wherein the metal oxide film includes titanium oxide (TiO).
8. The semiconductor device of claim 1 , wherein the second electrode includes titanium nitride (TiN).
9. A semiconductor device comprising:
a substrate;
a first electrode on the substrate;
a dielectric insulating film on the first electrode;
a metal oxide film on the dielectric insulating film; and
a second electrode on the dielectric insulating film,
wherein the first electrode includes titanium nitride (TiN),
the dielectric insulating film includes hafnium (Hf), zirconium (Zr) and aluminum (Al), and
the second electrode includes a titanium nitride (TiN) layer and a nickel (Ni) layer.
10. The semiconductor device of claim 9 , wherein the first electrode is pillar-shaped and includes silicon (Si).
11. The semiconductor device of claim 9 , wherein the metal oxide film includes titanium oxide (TiO).
12. The semiconductor device of claim 9 , wherein the dielectric insulating film includes at least one of silicon (Si), titanium (Ti), lanthanum (La), or tantalum (Ta).
13. The semiconductor device of claim 9 , wherein the dielectric insulating film includes silicon (Si).
14. The semiconductor device of claim 9 , wherein the dielectric insulating film includes titanium (Ti).
15. The semiconductor device of claim 9 , wherein the dielectric insulating film includes silicon (Si) and titanium (Ti).
16. The semiconductor device of claim 9 , wherein the second electrode includes a layer between the titanium nitride (TiN) layer and the nickel (Ni) layer of the second electrode, and
the layer of the second electrode includes nickel (Ni), titanium (Ti) and nitrogen (N).
17. A semiconductor device comprising:
a substrate;
a first electrode on the substrate;
a dielectric insulating film on the first electrode;
a metal oxide film on the dielectric insulating film; and
a second electrode on the dielectric insulating film,
wherein the first electrode is pillar-shaped and includes titanium nitride (TiN), the dielectric insulating film includes hafnium (Hf), zirconium (Zr) and aluminum (Al),
the metal oxide film includes titanium oxide (TiO), and
the second electrode includes a titanium nitride (TiN) layer and a layer including at least one of nickel (Ni), titanium (Ti), or nitrogen (N).
18. The semiconductor device of claim 17 , wherein the first electrode includes silicon
19. The semiconductor device of claim 17 , wherein the dielectric insulating film includes at least one of silicon (Si), titanium (Ti), lanthanum (La), or tantalum (Ta).
20. The semiconductor device of claim 17 , wherein the dielectric insulating film includes silicon (Si) and titanium (Ti).
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