CN114093996A - Semiconductor light emitting device - Google Patents
Semiconductor light emitting device Download PDFInfo
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- CN114093996A CN114093996A CN202111383845.XA CN202111383845A CN114093996A CN 114093996 A CN114093996 A CN 114093996A CN 202111383845 A CN202111383845 A CN 202111383845A CN 114093996 A CN114093996 A CN 114093996A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
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Abstract
The invention relates to the field of light emitting diodes, and discloses a semiconductor light emitting device which comprises a substrate, an epitaxial layer, a first electrode layer, a first insulating layer and a second electrode layer which are sequentially arranged from bottom to top; the first electrode layer comprises at least one first P-type and second N-type electrode; the second electrode layer comprises at least one second P-type and second N-type electrode; the first and second P-type electrodes are electrically connected, and the first and second N-type electrodes are electrically connected; at least one inner concave part for reducing the area of the second electrode layer is arranged on the outer side surface of the second P-type electrode, which is close to the outer edge of the N-type semiconductor layer; the total area of the concave parts accounts for 5-20% of the area of the second electrode layer. This application is guaranteeing under the normal electric connection's of first and second P type electrode the condition, through set up interior concave part on the lateral surface that second P type electrode closes on N type semiconductor layer outer fringe, realizes reducing the area of second electrode layer, improves the reflectivity of chip to improve the whole luminance of chip.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor light-emitting device.
Background
A light emitting diode (LED for short) is a commonly used light emitting device, has the advantages of low voltage, low power consumption, small volume, long service life, and the like, and is widely used in the fields of illumination, display, and the like. LEDs are widely used as a new generation of light source in the fields of illumination, display, backlight, and optical communication. The flip chip has been more and more favored by the market as a product with higher light efficiency, and the flip chip has more process structures and complex process, so that the flip chip has higher requirements and challenges on reliability.
At present, the area of the design pattern of the second electrode layer PN-Metal layer of the LED high-luminous-efficiency chip is larger, and about 80% of the area of the first insulating layer is covered, as shown in figures 1 to 3, because the reflectivity of the second electrode layer is lower than that of the traditional support, the reflectivity of the chip is reduced due to the larger area of the second electrode layer, and the overall brightness of the chip is influenced.
In view of the above, the present invention is particularly proposed.
Disclosure of Invention
The purpose of the invention is as follows: in view of the problems in the prior art, the present invention provides a semiconductor light emitting device, wherein an inner concave portion is disposed on an outer side surface of a second P-type electrode adjacent to an outer edge of an N-type semiconductor layer under the condition of ensuring normal electrical connection between a first P-type electrode and the second P-type electrode, so as to reduce an area of the second electrode layer, improve a reflectivity of a chip, and improve an overall brightness of the chip.
The technical scheme is as follows: the invention provides a semiconductor light-emitting device which comprises a substrate, an epitaxial layer with a PN step, a first electrode layer, a first insulating layer and a second electrode layer, wherein the substrate, the epitaxial layer with the PN step, the first electrode layer, the first insulating layer and the second electrode layer are sequentially arranged from bottom to top; the first electrode layer comprises at least one first P-type electrode and at least one first N-type electrode; the second electrode layer comprises at least one second P-type electrode and at least one second N-type electrode; the first P-type electrode is electrically connected with the second P-type electrode through a first through hole formed in the first insulating layer, and the first N-type electrode is electrically connected with the second N-type electrode through a second through hole formed in the first insulating layer; the second P-type electrode is provided with an outer side surface which is connected with the upper surface and the lower surface and is close to the outer edge of the N-type semiconductor layer; the outer side surface is provided with at least one inner concave part for reducing the area of the second electrode layer; the total area of the concave parts accounts for 5-20% of the area of the second electrode layer.
Preferably, the inner recess is disposed between two adjacent first P-type electrodes.
Preferably, the length L1 of the concave part is less than the maximum distance L2 between two first P-type electrodes adjacent to the concave part. The design is so as to increase the length of the inner concave part as much as possible, shrink the area of the second electrode layer inwards and improve the reflectivity of the chip on the premise of not influencing the electrical connection of the first P-type electrode and the second P-type electrode, thereby improving the overall brightness of the chip.
Preferably, the width W of the inner recess is greater than or equal to the diameter d of the first P-electrode.
Preferably, if the light emitting element is a square as a whole, the outer side surface is a square outer side surface; the outer side surface of at least one side of the square outer side surfaces is provided with a continuous inner concave part; or, the outer side surfaces of at least two opposite sides of the outer side surfaces of the square are provided with continuous inner concave parts; or, of the outer side surfaces of the square, the outer side surfaces of the four sides are provided with the continuous concave parts. The arrangement of the inner concave part is to remove the second electrode layer between at least one pair of adjacent second P-type electrodes at the edge of the second electrode layer, so as to reduce the area of the second electrode layer by inner shrinkage, and achieve the purposes of improving the reflectivity of the chip and improving the overall brightness of the chip.
Preferably, each of the continuous concave portions is located between two of the first P-type electrodes. The concave parts are arranged between every two adjacent first P-type electrodes, so that the number of the concave parts can be increased to the maximum extent, the area of the second electrode layer is reduced, the reflectivity of the chip is improved to the maximum extent, and the overall brightness of the chip is improved; theoretically, the more the inner concave parts are arranged, the greater the force for reducing the area of the second electrode layer is, and the more obvious the effects of improving the reflectivity of the chip and improving the overall brightness of the chip are; however, in practical application, if the area of the inner concave portion is too large, that is, the area of the second electrode layer is too much reduced, the electrical connection effect between the second P-type electrode and the first P-type electrode is affected, and the area of the inner concave portion is smaller, the area of the second electrode layer is not significantly reduced, the reflectivity of the chip is improved, and the effect of improving the overall brightness of the chip is not significant, so that the area of the inner concave portion is controlled to occupy 5-15% of the area of the first insulating layer, which can ensure the electrical connection between the second P-type electrode and the first P-type electrode, and can achieve the effect of reducing the area of the inner concave second electrode layer, thereby achieving the purposes of improving the reflectivity of the chip and improving the overall brightness of the chip.
Further, the semiconductor light emitting device further includes a pad electrode layer on the second electrode layer, and the pad electrode layer includes a P-pad electrode electrically connected to the second P-type electrode and an N-pad electrode electrically connected to the second N-type electrode.
Further, the semiconductor light emitting device further includes a second insulating layer between the second electrode layer and the pad electrode layer to insulate the second P-type electrode from the second N-type electrode; the P-pad electrode is electrically connected with the second P-type electrode through a third through hole formed in the second insulating layer, and the N-pad electrode is electrically connected with the second N-type electrode through a fourth through hole formed in the second insulating layer.
Further, a support layer and a third insulating layer are further disposed between the second insulating layer and the pad electrode layer, the support layer is located between the second insulating layer and the third insulating layer, and the third insulating layer is located between the support layer and the pad electrode layer. In the conventional light emitting device structure, as shown in fig. 1, the second P-type electrode extends to a position below the N-pad electrode, and the two electrodes are separated from each other by the second insulating layer, thereby forming a region shown by a dashed square. When the second insulating layer is broken or cracked due to some reasons, the second P-type electrode and the N pad electrode can be communicated, so that electric leakage is caused, and the reliability of the conventional light-emitting element is reduced when the conventional light-emitting element is used; the supporting layer which is not connected with the second electrode layer and the pad electrode and the third insulating layer which is isolated from the pad electrode are added, so that the insulating effect of isolating the second electrode and the third electrode is achieved, the electric leakage phenomenon caused by fracture of the second insulating layer is avoided, and the reliability of the light-emitting element is improved. The supporting layer is preferably a metal layer or a metal oxide layer or a DBR reflecting layer, and the metal layer comprises a metal single layer of Cr, Ni, Ti, Pt and Au or a composite metal layer consisting of several metal single layers.
Further, the semiconductor light emitting device further comprises a current blocking layer and a current spreading layer which are positioned between the epitaxial layer and the first electrode layer, and the current spreading layer is positioned on the current blocking layer.
Has the beneficial effects that: this application is guaranteeing under the normal electric connection's of first P type electrode and second P type electrode the condition, through setting up interior concave part on the lateral surface that second P type electrode closes on N type semiconductor layer outer fringe to the area sum of injecing each interior concave part accounts for 5~20% of second electrode layer area, in order to realize obviously reducing the area of second electrode layer, improves the reflectivity of chip, thereby improves the whole luminance of chip.
Drawings
FIG. 1 is a schematic plan view of a flip-chip light emitting device in the prior art;
FIG. 2 is a schematic diagram of a flip-chip light emitting device in the prior art;
FIG. 3 is a plan view of a mask pattern of a second electrode layer in the prior art;
fig. 4 is a schematic plan view of a light-emitting element in embodiment 1;
fig. 5 is a schematic structural view of a light-emitting element in embodiment 1;
FIG. 6 is a plan view of a mask pattern of a second electrode layer in embodiment 1;
fig. 7 is a schematic structural view of a light-emitting element in embodiment 1;
fig. 8 is a schematic plan view of a light-emitting element in embodiment 2;
fig. 9 is a schematic structural view of a light-emitting element in embodiment 2;
FIG. 10 is a plan view of a mask pattern of the second electrode layer in embodiment 3;
reference numerals:
| 100-a substrate; | 210-N type semiconductor layer; | 211-PN step; |
| 220-multiple quantum well active layer; | a 230-P type semiconductor layer; | 300-a current blocking layer; |
| 400-current spreading layer; | 510-a first P-type electrode; | 511-a first via; |
| 520-a first N-type electrode; | 521-a second through hole; | 600-a first insulating layer; |
| 710-a second P-type electrode; | 720-a second N-type electrode; | 800-a second insulating layer; |
| 900-support layer; | 1000-a third insulating layer; | 1100-third via; |
| 1200-a fourth via; | 1310-P pad electrode； | 1320-N pad electrode; |
| 1410-an internal recess; | 711-lateral side. |
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
Embodiment 1:
as shown in fig. 4 and 5, the light emitting device provided in the embodiment of the present invention includes a substrate 100, an epitaxial layer, a current blocking layer 300, a current spreading layer 400, a first electrode layer, a first insulating layer 600, a second electrode layer, a second insulating layer 800, and a pad electrode layer, which are sequentially disposed from bottom to top; the first electrode layer includes at least one first P-type electrode 510 and at least one first N-type electrode 520; the second electrode layer includes at least one second P-type electrode 710 and at least one second N-type electrode 720; the pad electrode layer includes at least one P-type pad 1310 and at least one N-type pad 1320. The second P-type electrode 710 has an outer side 711 connected to the upper and lower surfaces thereof and adjacent to the outer edge of the N-type semiconductor layer 210.
As shown in fig. 6, in the present embodiment, when the entire light emitting element is square, the outer surface 711 of the second P-type electrode 710 is a square outer surface; in order to reduce the area of the second electrode layer with lower reflectivity, improve the reflectivity of the chip and further improve the overall brightness of the chip, the outer side surfaces 711 on a pair of opposite sides of the square outer side surfaces 711 of the second P-type electrode 710 are provided with continuous inner concave parts 1410; each successive inner recess 1410 is located between each two of the first P-type electrodes 510. That is, the concave portions 1410 are formed by removing the second electrode layer between two adjacent second P-type electrodes 710 on the outer side surfaces 711 of the second P-type electrodes 710, and the sum of the areas of the concave portions 1410 occupies 7.7% of the area of the second electrode layer.
In practical application, a square inner concave part 1410 can be formed, and the length L1 of the inner concave part 1410 is smaller than the maximum distance L2 between two adjacent first P-type electrodes 510; the width W of the inner recess 1410 is greater than or equal to the diameter d of the first P-electrode 510 (see fig. 7). The design is to increase the length of the inner concave portion 1410 as much as possible, and to shrink the area of the second electrode layer, so as to improve the reflectivity of the chip, thereby improving the overall brightness of the chip, on the premise of not affecting the electrical connection between the first P-type electrode 510 and the second P-type electrode 710.
Other structures of the light emitting element in this embodiment mode are provided as conventional light emitting elements. The method comprises the following specific steps:
the epitaxial layer is arranged on the surface of the substrate 100 and comprises an N-type semiconductor layer 210, a light emitting layer 220 and a P-type semiconductor layer 230 which are sequentially stacked on the surface of the substrate 100; the structure further comprises a PN step 211, wherein the upper step surface of the PN step 211 is a P-type semiconductor layer 230, the lower step surface is an N-type semiconductor layer 210, and the upper step surface and the lower step surface are connected to form the side surface of the PN step 211; an N-type semiconductor layer 210 formed on the substrate 100 to cover the substrate; a P-type semiconductor layer 230 formed to cover a region on the N-type semiconductor layer 210 other than the region for the N-electrode on the N-type semiconductor layer 210, for emitting light in cooperation with the N-type semiconductor layer 210; the current blocking layer 300 and the current spreading layer 400 are sequentially disposed on the surface of the P-type semiconductor layer 230;
the first electrode layer includes a first P-type electrode 510 formed on the P-type semiconductor layer 230 and a first N-type electrode 520 for an N-electrode region formed on the N-type semiconductor layer 210; the first P-type electrode 510 is connected to the current spreading layer 400; the first N-type electrode 520 is connected to the lower step surface of the PN step 211; the first P-type electrode 510 and the first N-type electrode 520 are isolated from each other; the first insulating layer 600 covers the first N-type electrode 520, the current spreading layer 400, the side of the PN step 211, the first P-type electrode 510, and the lower step surface between the first N-type electrode 520 and the side of the PN step 211; the first insulating layer 600 is used for insulating the first N electrode from the first P electrode, and a first via 511 penetrating the first P-type electrode 510 and a second via 521 penetrating the first N-type electrode 520 are disposed on the first insulating layer 600;
the second electrode layer comprises a second P-type electrode 710 and a second N-type electrode 720, and the second P-type electrode 710 and the second N-type electrode 720 are insulated and isolated from each other; the second P-type electrode 710 is connected to the first P-type electrode 510 through the first via 511; the second N-type electrode 720 is connected to the first N-type electrode 520 through the second via 521; the second insulating layer 800 is disposed on the surface of the second electrode layer;
the third through hole 1100 and the fourth through hole 1200 penetrate through the second insulating layer 800 and are respectively communicated with the second P-type electrode 710 and the second N-type electrode 720;
the pad electrode layer includes a P pad electrode 1310 and an N pad electrode 1320, the P pad electrode 1310 and the N pad electrode 1320 being isolated from each other; the P-pad electrode 1310 and the second P-type electrode 710 are electrically connected through the third via 1100, and the N-pad electrode 1320 and the second N-type electrode 720 are electrically connected through the fourth via 1200.
The substrate 100 may include, but is not limited to, a sapphire substrate, among others. In addition, a patterned substrate may also be selected.
The material of the N-type semiconductor layer 210 may be N-type doped gan, and the material of the P-type semiconductor layer 230 may be P-type doped gan, but the invention is not limited to these two semiconductor types.
Here, the light emitting layer 220 includes quantum wells and quantum barriers alternately stacked, but is not limited thereto. The light emitting layer 220 includes, but is not limited to, a red light emitting layer, a yellow light emitting layer, a green light emitting layer, or a blue light emitting layer. Quantum wells include, but are not limited to, InGaN quantum wells or AlInGaN quantum wells.
Wherein the current blocking layer 300 includes, but is not limited to, SiO2The thickness of the current blocking layer 300 is generally 1500-. .
The current spreading layer 400 occupies 70-90% of the area of the light emitting element, and includes but is not limited to one of ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO, and GZO. The thickness of the current spreading layer 400 is 100A-500A, for example, 100A, 150A, 200A, 300A, 500A. The current spreading layer 400 may be deposited by magnetron sputtering or evaporation.
The first through hole 511 and the second through hole 521 are separated from each other, and do not extend and intersect with each other; as shown in fig. 5, the third through hole 1100 and the fourth through hole 1200 are separated from each other without any extended intersection, thereby ensuring separation of the upper layer electrode and the lower layer hetero-electrode and cutting off a possible leakage path.
Wherein the first insulating layer 600 is a DBR reflective layer, which can be SiO deposited alternately2And Ti3O5And (4) forming. The thickness of the first insulating layer 600 is 2 μm to 6 μm, preferably 3.5 μm to 5.5 μm.
Wherein the second insulating layer 800 and/or the third insulating layer 1000 include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The thickness of the second insulating layer 800 and/or the third insulating layer 1000 is 5K A-15K A, for example 6K A, 8K A, 13K A, 15K A.
Among the pad electrode layers, the number of the P pad electrodes 1310 may be 1, 2 or more; the N pad electrodes 1320 may be 1, 2, or more. The pad electrode comprises a single metal layer of Cr, Ni, Ti, Pt and Au or a composite layer of several metals and/or alloys. The thickness of Al is 5K-20K A, the thickness of Pt is 0.5K-3K A, the thickness of Ti is 0.5-3K A, the thickness of Ni is 3K-12K A, and the thickness of Au is 1K-5K A. The pad electrodes are Bump electrodes including Sn components, i.e., the P pad electrode 1310 and the N pad electrode 1320 may be Bump electrodes, and the electrode components are Sn. The bump electrode can be made by printing, electroplating or evaporation. The height of the Bump electrode is more than or equal to 5 mu m, and the height of the solder paste is more than or equal to 20 mu m.
The embodiment of the invention also provides a preparation method of the light-emitting element, which specifically comprises the following steps:
s1, providing a substrate 100, and sequentially depositing an N-type semiconductor layer 210, a light emitting layer 220 and a P-type semiconductor layer 230 on the substrate 100 to form an epitaxial layer;
s2, forming a pattern of the MESA layer by using photoresist, carrying out ICP etching on the epitaxial layer by using the MESA layer as a mask, forming a PN step 211 by etching the depth of 10000-14000A, and removing the photoresist;
s3, depositing SiO on the epitaxial layer2Obtaining a current barrier layer 300 through photoetching, and removing the photoresist; the current blocking layer 300, which is positioned between the P-type semiconductor layer 230 and the current spreading layer 400, functions to assist current spreading,the thickness of the current blocking layer 300 is generally 1500-.
S4, depositing a current spreading layer 400 on the epitaxial layer, photoetching the current spreading layer 400 by using photoresist to form a required current spreading layer pattern layer, etching the current spreading layer 400 by using the current spreading layer pattern layer as a mask, removing the photoresist to leak out of the bottom current spreading layer 400, wherein the thickness of the current spreading layer 400 is 100-500A;
s5, photoetching is carried out firstly by using photoresist, a first electrode layer is manufactured by deposition, the first electrode layer comprises a first P-type electrode 510 and a first N-type electrode 520, the first P-type electrode 510 covers the superposed film layer of the current barrier layer 300 and the current expansion layer 400, then the photoresist is removed, the material of the first electrode layer is one or the combination of several metals such as Cr, Ni, Al, Ti, Au, Pt and the like, and the thickness of the first electrode layer can be 2-5 μm;
s6, depositing DBR Bragg reflection layers formed by alternately depositing SiO2 and Ti3O5, namely a first insulation layer 600, wherein the thickness of the first insulation layer 600 is generally 2-6 μm, and if the first insulation layer is too thin, the reflection effect is lacked, and if the first insulation layer is too thick, the etching time is too long, and the thickness of the whole first insulation layer 600 is 3-8 μm;
s7, performing photoetching on the first insulating layer 600 by using photoresist, forming a first insulating layer pattern on the photoresist, performing ICP etching, and performing photoetching on the upper parts of the first P-type electrode 510 and the first N-type electrode 520 to obtain a first through hole 511 and a second through hole 521 respectively;
s8, depositing a second electrode layer and then removing the photoresist; the second P-type electrode 710 is communicated with the first P-type electrode 510 through the first via 511, and the second N-type electrode 720 is communicated with the first N-type electrode 520 through the second via 521; the area of the second electrode layer is designed to be as small as possible under the condition that the first electrode layer is ensured to be normally connected. The material of the second electrode layer is one or a combination of several metals of Cr, Ni, Al, Ti, Au, Pt and the like, and the thickness of the second electrode layer can be 2-5 μm.
S9, a second insulating layer 800 is covered on the second P-type electrode 710 and the second N-type electrode 720. The second insulating layer 800 is formed by depositing an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride by PECVD, and the thickness of the second insulating layer 800 is 5000-.
S10, etching to obtain a third through hole 1100 and a fourth through hole 1200 which penetrate through the second insulating layer 800;
s11, preparing pad electrodes by yellow light and deposition, forming a P pad electrode 1310 and an N pad electrode 1320; the P-pad electrode 1310 is connected to the second P-type electrode 710 through a third via 1100, and the N-pad electrode 1320 is connected to the second N-type electrode 720 through a fourth via 1200; the pad electrode is one or a combination of several metals of Cr, Ni, Al, Ti, Au, and Pt, and the P pad electrode 1310 and the N pad electrode 1320 may have a thickness of 2-5 μm.
Embodiment 2:
this embodiment is a further improvement of embodiment 1, and the main improvement is that in embodiment 1, the second P-type electrode 710 extends to below the N-pad electrode 1320, and the two electrodes are isolated from each other by the second insulating layer 800, so as to form a region shown by a dashed square in fig. 4. When the second insulating layer 800 is broken or cracked due to some reasons, the second P-type electrode 710 and the N-pad electrode 1320 may be connected to each other, which may cause leakage current and decrease reliability of the conventional light emitting device. In this embodiment, a support layer 900 not connected to the second electrode layer and the pad electrode layer and a third insulating layer 1000 spaced apart from the pad electrode layer are added between the second insulating layer 800 and the pad electrode.
As shown in fig. 8 and 9, the support layer 900 is disposed between the second insulating layer 800 and the pad electrode layer; the third insulating layer 1000 completely covers the surface where the second insulating layer 800 and the support layer 900 are formed; the support layer 900 is insulated from the second electrode layer by the second insulating layer 800; and the support layer 900 is insulated and isolated from the pad electrode layer by the third insulating layer 1000. The support layer 900 includes a P region support layer and an N region support layer; the P region supporting layer covers the region of the second P type electrode 710, and plays a role of blocking the second P type electrode 710; the N-region support layer covers a region of the second N-type electrode 720, and functions to block the second N-type electrode 720. The third through hole 1100 and the fourth through hole 1200 simultaneously penetrate through the second insulating layer 800 and the third insulating layer 1000 and then respectively pass through the second P-type electrode 710 and the second N-type electrode 720.
The supporting layer 900 may be made of any material, and in order to ensure a better supporting effect and to be suitable for a mature chip manufacturing process, the material of the supporting layer 900 is preferably a metal layer, and the metal layer includes a metal monolayer of Cr, Ni, Ti, Pt, and Au or a composite metal layer composed of several metal monolayers. The material of the supporting layer 900 is preferably a metal oxide with good light guiding property, such as indium tin oxide, zinc oxide, and tin oxide. The material of the support layer 900 is preferably a DBR reflective layer having insulating properties, such as SiO2/TiO2A DBR reflective layer. The thickness of the supporting layer 900 is less than 2 micrometers, the area of the supporting layer 900 accounts for 50% -80% of the area of the light-emitting element, the electrode reflectivity is 60% -95%, and the angle of the metal electrode is required to be 30-75 degrees to ensure subsequent film covering.
In this embodiment, the supporting layer 900 and the third insulating layer 1000 are added, so that the P pad electrode 1310 and the N pad electrode 1320 of the pad electrode layer are not communicated with the supporting layer 900, and the supporting layer 900 is not communicated with the second electrode layer, and are insulated from each other, and the pad electrode layer is electrically communicated with the second electrode layer through a through hole penetrating through the second insulating layer 800 and the third insulating layer 1000. And the third insulating layer 1000 and the second insulating layer 800 are subjected to open-hole etching by the same photoetching, so that the supporting layer 900 is wrapped on insulating SiO from all sides2In the film, the supporting layer 900 is not connected with each layer of electrodes, so that the insulating and isolating effects of the opposite electrodes are achieved, the electric leakage of the light-emitting element caused by the breakage of the insulating layer is effectively avoided, and the reliability of the light-emitting element is improved.
The manufacturing method of the light emitting element in this embodiment is also substantially the same as that of embodiment 1, and the difference is that in S10, before the third through hole 1100 and the fourth through hole 1200 are obtained by etching the second insulating layer 800, the support layer 900 and the third insulating layer 1000 are further deposited in this order on the second insulating layer 800, and then the third through hole 1100 and the fourth through hole 1200 are obtained by etching the second insulating layer 800 and the third insulating layer 1000 at the same time in the region where the support layer 900 is not present above the second P-type electrode 710 and the second N-type electrode 720. The minimum distance between the third through hole 1100 and the fourth through hole 1200 and the edge of the support layer 900 is more than 5 μm, so that all the surfaces of the support layer 900 are completely wrapped in the second insulation layer 800 and the third insulation layer 1000, and the support layer 900 is isolated from the conductive communication with any metal electrode.
The reliability of the light-emitting element in this embodiment is significantly improved compared to that in embodiment 1 (test results are shown in table 1 below).
Otherwise, this embodiment is identical to embodiment 1, and will not be described herein.
Embodiment 3:
this embodiment is substantially the same as embodiment 1, and differs from embodiment 1 only in that, in this embodiment, the second electrode layer has continuous inner concave portions on four outer side surfaces out of four outer side surfaces of the second P-type electrode 710, and the sum of the areas of the inner concave portions 1410 occupies 12.5% of the area of the second electrode layer. As shown in fig. 10, the second electrode layer between two adjacent second p-type electrodes 710 at the edge position is removed as much as possible. The reflectance of the light-emitting element in this embodiment is further improved and the overall luminance is further improved as compared with embodiment 1 (see table 1 below for test results).
Otherwise, this embodiment is identical to embodiment 1, and will not be described herein.
Comparative example
The comparative example is different from embodiment 1 only in that, in the second electrode layer, any inner concave portions 1410 for reducing the area of the second electrode layer are not opened in the four outer side surfaces of the second P-type electrode 710, and the second electrode layer is illustrated in a mask plan view as shown in fig. 3.
By performing a comparative test on the light-emitting elements described in embodiments 1, 2, and 3 and the comparative example under the same test conditions at a test current of 65mA, the light-emitting elements provided in embodiments 1, 2, and 3 of the present invention exhibited luminance improvement of 0.2% and 0.3%, respectively, as compared with the comparative example. The number of impact cycles of the dead lamp was confirmed for each condition by testing the conditions of-45 ℃ to 125 ℃ for each 15min of cold-thermal shock, and it was found that the reliability of the light emitting elements described in embodiments 1, 2, and 3 and the comparative example was the highest, and thus the reliability was the highest for the light emitting element in embodiment 2.
TABLE 1
| Luminance (mw) | Reliability (cycle) | |
| Embodiment mode 1 | 168.1 | 3250 |
| Embodiment mode 2 | 168.2 | 4130 |
| Embodiment 3 | 168.7 | 3320 |
| Comparative example | 167.8 | 3278 |
The above embodiments are merely illustrative of the technical concepts and features of the present invention, and the purpose of the embodiments is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A semiconductor light-emitting device comprises a substrate (100), an epitaxial layer with a PN step, a first electrode layer, a first insulating layer (600) and a second electrode layer which are arranged in sequence from bottom to top; the first electrode layer comprises at least one first P-type electrode (510) and at least one first N-type electrode (520); the second electrode layer comprises at least one second P-type electrode (710) and at least one second N-type electrode (720); the first P-type electrode (510) is electrically connected with the second P-type electrode (710) through a first through hole (511) formed in the first insulating layer (600), and the first N-type electrode (520) is electrically connected with the second N-type electrode (720) through a second through hole (521) formed in the first insulating layer (600); it is characterized in that the preparation method is characterized in that,
the second P-type electrode (710) is provided with an outer side surface (711) which is connected with the upper surface and the lower surface of the second P-type electrode and is close to the outer edge of the N-type semiconductor layer (210); at least one inner concave part (1410) used for reducing the area of the second electrode layer is arranged on the outer side surface (711); the total area of the inner concave parts (1410) accounts for 5-20% of the area of the second electrode layer.
2. The semiconductor light emitting device according to claim 1, wherein the inner concave portion (1410) is disposed between two adjacent first P-type electrodes (510).
3. The semiconductor light-emitting device of claim 2, wherein the length L1 of the inner concave portion (1410) is smaller than the maximum spacing L2 between two first P-type electrodes (510) adjacent thereto;
and/or the width W of the inner recess (1410) is greater than or equal to the diameter d of the first P-type electrode (510).
4. The semiconductor light emitting device according to claim 1, wherein if the light emitting element as a whole has a square shape, the outer side surface (711) has a square outer side surface;
the outer side surface (711) of at least one side of the square outer side surfaces is provided with the continuous inner concave part (1410);
or, the outer side surface (711) of at least two opposite sides of the square outer side surface is provided with the continuous inner concave part (1410);
or, the outer side surfaces (711) on four sides of the square outer side surfaces are provided with the continuous inner concave parts (1410).
5. The semiconductor light emitting device according to claim 4, wherein each of the continuous concave portions (1410) is located between two of the first P-type electrodes (510).
6. The semiconductor light emitting device according to any one of claims 1 to 5, further comprising a pad electrode layer on the second electrode layer, the pad electrode layer comprising a P pad electrode (1310) electrically connected to the second P type electrode (710) and an N pad electrode (1320) electrically connected to the second N type electrode (720).
7. The semiconductor light emitting device according to claim 6, further comprising a second insulating layer (800) between the second electrode layer and the pad electrode layer to insulate the second P-type electrode (710) from the second N-type electrode (720);
the P-pad electrode (1310) is electrically connected to the second P-type electrode (710) through a third via (1100) formed in the second insulating layer (800), and the N-pad electrode (1320) is electrically connected to the second N-type electrode (720) through a fourth via (1200) formed in the second insulating layer (800).
8. A semiconductor light-emitting device according to claim 7, wherein a support layer (900) and a third insulating layer (1000) are further provided between the second insulating layer (800) and the pad electrode layer, the support layer (900) being located between the second insulating layer (800) and the third insulating layer (1000), and the third insulating layer (1000) being located between the support layer (900) and the pad electrode layer.
9. The semiconductor light emitting device of claim 8, wherein the support layer comprises a P-region support layer, an N-region support layer; the P region supporting layer covers the area of the second P type electrode (710); the N-region support layer covers the area of the second N-type electrode (720).
10. The semiconductor light emitting device according to any one of claims 1 to 5, further comprising a current blocking layer (300) and a current spreading layer (400) between the epitaxial layer and the first electrode layer, the current spreading layer (400) being located over the current blocking layer (300).
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