CN114080681A - 用于v-nand字线堆叠的衬里 - Google Patents

用于v-nand字线堆叠的衬里 Download PDF

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Publication number
CN114080681A
CN114080681A CN202080038529.6A CN202080038529A CN114080681A CN 114080681 A CN114080681 A CN 114080681A CN 202080038529 A CN202080038529 A CN 202080038529A CN 114080681 A CN114080681 A CN 114080681A
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China
Prior art keywords
nitride
layer
tungsten
titanium
memory
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Inventor
杰奎琳·S·阮奇
杨逸雄
巫勇
薇·V·唐
斯里尼瓦斯·甘迪科塔
林永景
卡拉·M·伯纳尔·拉莫斯
陈世忠
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Applied Materials Inc
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Applied Materials Inc
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Publication of CN114080681A publication Critical patent/CN114080681A/zh
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Abstract

讨论了形成存储器结构的方法。具体地，讨论了形成3D NAND器件的方法。一些实施方式形成具有金属氮化物阻挡层、α‑钨层和体金属材料的存储器结构。所述阻挡层包括TiXN或TaXN材料，其中X包括选自铝(Al)、硅(Si)、钨(W)、镧(La)、钇(Yt)、锶(Sr)或镁(Mg)中的一种或多种的金属。

Description

用于V-NAND字线堆叠的衬里
技术领域
本公开内容的实施方式涉及电子器件以及用于制造该电子器件的方法和设备的领域。更特别地，本公开内容的实施方式提供了在堆叠中具有金属氮化物膜和α-钨层的竖直NAND存储器器件。
背景技术
半导体技术已经迅速地发展，并且随着技术进步，器件尺寸已经缩小，以提供每单位空间的更快速的处理和存储。随着半导体技术进步，市场需要越来越小而每单位面积的结构越来越多的芯片。在小型化方面取得了许多进步的一类器件是存储器器件。随着对更高密度的需求的增加，3D NAND器件的典型方法是堆叠更多层。然而，附加层造成因增大的深宽比而越来越难蚀刻的更厚的堆叠。
目前，氮化钛(TiN)用作3D NAND器件的衬里。然而，为了维持F阻挡性能，氮化钛衬里的厚度需要为至少
Figure BDA0003371587580000011
随着存储器结构变得更密集和复杂，这种厚衬里减少了可用于钨填充的空间，从而不利地影响堆叠电阻率。
因此，需要降低堆叠电阻率，同时提供良好的阻挡性能。
发明内容
本公开内容的实施方式涉及一种存储器结构，所述存储器结构包括：硅材料和金属栅极的多个交替层，所述金属栅极包括共形阻挡层、共形α-钨(W)层和体钨层；和存储器孔沟道，所述存储器孔沟道穿过所述多个交替层形成并且具有沉积在所述存储器孔沟道的第一表面、第二表面、第三表面上的共形多晶硅材料层。
本公开内容的实施方式涉及一种形成存储器结构的方法。在一个或多个实施方式中，一种形成存储器结构的方法包括：沉积氮化物材料和氧化物材料的多个交替层；穿过所述多个交替层蚀刻存储器孔以形成所述交替层的第一暴露表面和第二暴露表面，所述存储器孔具有宽度；将共形多晶硅层沉积在所述存储器孔中；去除所述氮化物材料以形成开口并且暴露所述氧化物材料；将高K层共形地沉积在所述开口中；将阻挡层共形地沉积在所述开口中的所述高K层上，所述阻挡层包括TiXN或TaXN；将α-钨(W)层共形地沉积在所述阻挡层上；将金属材料沉积在所述α-钨(W)层上；和可选地，平面化所述存储器结构。
在一个或多个实施方式中，一种处理工具包括：中央传送站，所述中央传送站包括被配置为移动晶片的机器人；多个处理站，每个处理站连接到所述中央传送站并且提供与相邻处理站的处理区域分开的处理区域，所述多个处理站包括阻挡层沉积腔室和α-钨(W)沉积腔室；和控制器，所述控制器连接到所述中央传送站和所述多个处理站，所述控制器被配置为激活所述机器人以在所述处理站之间移动所述晶片和控制在所述处理站中的每一者中发生的工艺。
附图说明
为了可详细地理解本公开内容的上述特征，可参考实施方式来得到以上简要地概述的本公开内容的更特别的描述，实施方式中的一些示出在附图中。然而，需注意，附图仅仅示出了本公开内容的典型实施方式，并且因此不应当被视为对其范围的限制，并且本公开内容可允许其他等效实施方式。在附图中的各图中以示例而非限制的方式示出如本文所描述的实施方式，其中相同的附图标记指示类似的要素。
图1描绘了根据本文描述的一个或多个实施方式的制造存储器器件的方法的工艺流程图；
图2示出了根据本文描述的一个或多个实施方式的存储器器件的截面图；
图3示出了根据本文描述的一个或多个实施方式的存储器器件的截面图；
图4示出了根据本文描述的一个或多个实施方式的存储器器件的截面图；
图5示出了根据本文描述的一个或多个实施方式的存储器器件的截面图；
图6A示出了根据本文描述的一个或多个实施方式的存储器器件的放大截面图；
图6B示出了根据本文描述的一个或多个实施方式的存储器器件的放大截面图；
图6C示出了根据本文描述的一个或多个实施方式的存储器器件的放大截面图；
图7示出了根据本文描述的一个或多个实施方式的存储器器件的截面图；和
图8示出了根据一个或多个实施方式的群集工具。
具体实施方式
在描述本公开内容的若干示例性实施方式之前，将理解，本公开内容不限于以下描述中阐述的构造或工艺步骤的细节。本公开内容能够具有其他实施方式并且能够以各种方式实践或进行。
如本说明书和所附权利要求书所使用，术语“前驱物”、“反应物”、“反应气体”等可互换地使用，以便指称能够与基板表面反应的任何气体物质。
如本文所使用的“基板”是指任何基板或在制造工艺期间在其上执行膜处理的基板上形成的材料表面。例如，其上可执行处理的基板表面包括如下材料，诸如硅、氧化硅、应变硅、绝缘体上硅(SOI)、碳掺杂的氧化硅、非晶硅、掺杂的硅、锗、砷化镓、玻璃、蓝宝石和任何其他材料(诸如金属、金属氮化物、金属合金和其他导电材料)，这取决于应用。基板包括但不限于半导体晶片。基板可被暴露于预处理工艺以对基板表面进行抛光、蚀刻、还原、氧化、羟基化、退火和/或烘烤。除了直接地在基板本身的表面上进行膜处理之外，在本公开内容中，所公开的膜处理步骤中的任一者还可如以下更详细地公开的那样在形成在基板上的下面层上执行，并且术语“基板表面”旨在包括如上下文所指示的此类下面层。因此，例如，在膜/层或部分膜/层已经沉积到基板表面上时，新沉积的膜/层的暴露表面就变成了基板表面。
一个或多个实施方式有利地提供薄金属氮化物膜，该薄金属氮化物膜用作存储器结构中的阻挡层/衬里。阻挡层包括TiXN，并且与V-NAND存储器结构中的TiN衬里相比，提供改进的F阻挡性能。另外地，一个或多个实施方式的TiXN阻挡层具有小于标准TiN衬里的厚度，同时降低堆叠电阻率。
如本文所使用，术语“3D NAND”是指一种类型的电子(固态)非易失性计算机存储存储器，其中存储器单元以多个层堆叠。3D NAND存储器通常包括包含浮栅晶体管的多个存储器单元。传统上，3D NAND存储器单元包括以三个维度围绕位线布置的多个NAND存储器结构。
本文的公开内容使用诸如“竖直的”、“水平的”、“横向的”等术语。如本文所使用，“竖直的”是指从靠近基板延伸至远离基板的点或平面的平面。如在附图中所示，竖直平面从3D NAND器件的顶部(页面顶部)延伸到基板(页面底部)。类似地，“水平的”是指从基板的一侧延伸到另一侧的平面。如在附图中所示，水平平面从3D NAND器件的左侧(页面左侧)延伸到3D NAND器件的右侧(页面右侧)。因此，“横向的”应当理解为从左向右移动，反之亦然，即，水平地移动。本领域技术人员将认识到，方向描述是相对于3D NAND器件的取向的，并且不限于任何特定基板取向。
如本说明书和所附权利要求书所使用，术语“选择性地”是指以比另一第二表面更大的效果作用于第一表面的工艺。这种工艺将被描述为“选择性地”作用于第一表面而不是第二表面。在此方面所使用的术语“在……上方”并不暗示一个表面在另一个表面的顶部上的物理取向，而是表示一个表面相对于另一个表面在化学反应的热力学或动力学性质上的关系。例如，将钴膜选择性沉积到在介电表面上方的铜表面上是指钴膜沉积在铜表面上，而很少或没有钴膜沉积在介电表面上；或者，在铜表面上形成钴膜相对于在介电表面上形成钴膜在热力学或动力学上是有利的。
参考附图，本公开内容的一些实施方式涉及用于形成存储器结构或存储器器件(例如3D NAND器件)的方法。图1示出了根据一个或多个实施方式的制造存储器器件的方法的工艺流程图。本领域技术人员将认识到，方法10可包括所示的工艺中的任何或所有工艺。另外，对于一些部分，各个工艺的次序可不同。在不脱离本公开内容的情况下，方法10可从所列举的工艺中的任一者开始。在一个或多个实施方式中，制造存储器结构的方法10开始于操作15，其中沉积氮化物材料和氧化物材料的多个交替层以形成起始存储器堆叠。在操作20处，穿过多个交替层形成存储器孔。在操作25处，将多晶硅层沉积到存储器孔中。在操作30处，去除氮化物材料。在操作35处，沉积阻挡层。在操作40处，沉积α-钨(W)层。在操作45处，将金属材料沉积在α-钨(W)层上。在操作50处，可选地，平面化存储器结构。
图2示出了根据本公开内容的一些实施方式的示例性存储器结构100的截面图。在一个或多个实施方式中，氮化物材料106和氧化物材料104的多个交替层150沉积在基板102上。
在一个或多个实施方式中，氮化物材料106包括氮化硅。在一个或多个实施方式中，氧化物材料104包括氧化硅。在一个或多个实施方式中，氧化物材料104基本上由硅组成。本领域技术人员将理解，氮化物材料106和氧化物材料104中的每一者可以是化学计量或非化学计量材料。例如，术语“氧化硅”和“二氧化硅”都可用于描述具有任何合适的化学计量比的硅和氧原子的材料。对于本公开内容中列出的其他材料，例如氮化硅、氧氮化硅、氧化钨、氧化锆、氧化铝、氧化铪等，也是如此。
包括氮化物材料106和氧化物材料104的交替层150可通过本领域技术人员已知的任何合适的工艺沉积，包括但不限于原子层沉积、物理气相沉积或化学气相沉积。在一个或多个实施方式中，氮化物材料106和氧化物材料104中的每一者通过化学气相沉积来沉积。
如本文所使用的“原子层沉积”或“循环沉积”是指顺序地暴露两种或更多种反应性化合物以在基板表面上沉积材料层。基板或该基板的部分单独地暴露于被引入处理腔室的反应区中的两种或更多种反应化合物。在时域ALD工艺中，暴露于每种反应化合物以一定时间延迟分开，从而允许每种化合物粘附在基板表面上和/或与该基板表明反应并且然后从处理腔室净化。这些反应性化合物据说顺序地暴露于基板。在空间ALD工艺中，基板表面的不同部分或在基板表面上的材料同时地暴露于两种或更多种反应化合物，使得基板上的任何给定点基本上不同时地暴露于多于一种反应化合物。如本说明书和所附权利要求书所使用，在这方面所使用的术语“基本上”如本领域的技术人员将理解的那样表示存在基板的一小部分可能因扩散而被暴露于多种反应气体的可能性，并且表示同时暴露是不希望的。
在时域ALD工艺的一个方面中，将第一反应性气体(即，第一前驱物或化合物A，例如铝前驱物)脉冲到反应区中，接着的是第一时间延时。接着，将第二前驱物或化合物B(例如氧化剂)脉冲到反应区中，接着的是第二延时。在每个时间延迟期间，将净化气体(诸如氩)引入处理腔室中以净化反应区或以其他方式从反应区去除任何残余反应化合物或反应副产物。替代地，净化气体可在整个沉积工艺中持续地流动，使得在反应化合物的脉冲之间的时间延迟期间仅净化气体流。替代地脉冲反应化合物，直到在基板表面上形成所期望的膜或膜厚度。在任一场景中，脉冲化合物A、净化气体、化合物B和净化气体的ALD工艺是某种循环。循环可从化合物A或化合物B开始并继续该循环的相应次序，直到实现具有预确定的厚度的膜为止。
在空间ALD工艺的实施方式中，第一反应气体和第二反应气体(例如，氮气)同时地输送到反应区，但是被惰性气帘和/或真空帘分开。基板相对于气体输送设备移动，使得在基板上的任何给定点都暴露于第一反应气体和第二反应气体。
如本文所使用，“化学气相沉积”是指其中基板表面同时地或基本上同时地暴露于前驱物和/或共试剂的工艺。如本文所使用，“基本上同时地”是指共流或在其中前驱物的大部分的暴露重叠的情况。
由于成本效益和膜性质多功能性，等离子增强化学气相沉积(PECVD)被广泛地用于沉积薄膜。在PECVD工艺中，例如，将已经夹带在载气中的烃源，诸如气相烃或液相烃的蒸气，引入PECVD腔室中。等离子体引发的气体(典型地是氦)也被引入腔室中。然后在腔室中引发等离子体以产生激发的CH自由基。激发的CH自由基化学地结合到定位在腔室内的基板的表面，从而在该表面上形成期望的膜。可使用任何合适的薄膜沉积系统来实施本文参考PECVD工艺描述的实施方式。本文描述的任何设备描述是说明性的，并且不应被理解或解释为限制本文描述的实施方式的范围。
在一个或多个实施方式中，单独的交替层可形成为任何合适的厚度。在一个或多个实施方式中，每个氮化物材料层106的厚度近似相等。在一个或多个实施方式中，每个氧化物材料层104的厚度近似相等。在一个或多个实施方式中，每个硅层104的厚度近似相等。如在这方面所使用，近似相等的厚度在彼此的+/-5％以内。
在一个或多个实施方式中，氮化物材料层106的平均厚度近似等于氧化物材料层104的平均厚度。在一个或多个实施方式中，氮化物材料层106的平均厚度大于或小于氧化物材料层104的平均厚度。
在一个或多个实施方式中，氮化物材料层106的平均厚度在约10nm至约50nm的范围内，包括约15nm至约40nm、约17nm至约35nm或约20nm至约20nm。在一个或多个实施方式中，氮化物材料层106的平均厚度为约27nm。在一个或多个实施方式中，氧化物材料层104的平均厚度在约10nm至约50nm的范围内，包括约15nm至约40nm、约17nm至约35nm或约20nm至约20nm。在一个或多个实施方式中，氧化物材料层104的平均厚度为约25nm。在一个或多个实施方式中，硅层104的平均厚度在约1nm至约10nm的范围内，包括约2nm、约3nm、约4nm、约5nm、约6nm、约7nm、约8nm或约9nm。在一个或多个实施方式中，硅层104的平均厚度为约3nm。
参考图3，在沉积交替层150之后，穿过交替层150蚀刻存储器孔108。蚀刻存储器孔108形成交替层150的第一暴露表面110、第二暴露表面112和第三暴露表面114。存储器孔108具有宽度W。在一个或多个实施方式中，宽度W在存储器孔108的顶部109和底部111处近似相等。
如图4所示，在一个或多个实施方式中，在蚀刻存储器孔108之后，将多晶硅层116共形地沉积到存储器孔中。如本文所使用，术语“共形地沉积”是指多晶硅在存储器孔的第一暴露表面、第二暴露表面和第三暴露表面上形成薄层，但是不填充存储器孔。
如图5所示，在一个或多个实施方式中，虽然图中未示出，但是在沉积多晶硅之后，在交替层150的与存储器孔108相对的一侧上设有敞开的狭缝。在一个或多个实施方式中，使用硬掩模形成狭缝。在一个或多个实施方式中，使用反应离子蚀刻工艺来蚀刻狭缝。在一个或多个实施方式中，通过与用于蚀刻存储器孔108的工艺类似的工艺形成狭缝。
如图5所示，在形成狭缝之后，去除氮化物材料106，以暴露氧化物材料104来在存储器孔108的相对侧上形成开口117。氮化物材料106可通过任何合适的工艺去除。在一个或多个实施方式中，去除工艺对氧化物材料104上比对氮化物材料106选择性。
氮化物材料106可通过本领域技术人员已知的任何合适的技术来去除，包括但不限于选择性蚀刻。蚀刻氮化物材料106横向地去除氮化物材料106以形成开口117。
在一个或多个实施方式中，可控制去除的氮化物材料106的量。在一个或多个实施方式中，选择性地蚀刻氮化物材料106以去除预定深度D的氮化物材料106。如图5所示，在一个或多个实施方式中，从每个氮化物材料层106去除的深度D的材料近似相等。
在一个或多个实施方式中，可通过对氧化物材料104和硅层104选择性的任何合适的工艺来选择性地蚀刻氮化物材料106。在一个或多个实施方式中，可通过原子层蚀刻工艺选择性地蚀刻氮化物材料。
在一个或多个实施方式中，选择性地蚀刻氮化物材料106以去除与存储器孔108的宽度W成比例的深度D。在一个或多个实施方式中，深度D大于或等于W的约2％、大于或等于W的约5％、大于或等于W的约10％、或大于或等于约W的15％。在一个或多个实施方式中，深度D小于或等于W的约30％、小于或等于W的约25％、小于或等于W的约20％、小于或等于W的约15％，或小于或等于W的约10％。在一个或多个实施方式中，深度D在W的约2％至约30％的范围内，在W的约5％至约25％的范围内，或在W的约10％至约20％的范围内。
在一个或多个实施方式中，选择性地蚀刻氮化物材料106以去除预定深度D。在一个或多个实施方式中，深度D小于或等于约500nm，包括约450nm、约400nm、约350nmnm、约300nm、约250nm、约200nm。在一个或多个实施方式中，深度D为约100nm至约500nm。
在一个或多个实施方式中，选择性地蚀刻氮化物材料106以去除所有氮化物材料106。
图6A至图6C示出了区域118的放大图。参考图6A，在一个或多个实施方式中，共形高K材料层119或共形氧化铝(AlOx)层(未示出)中的一种或多种沉积在第一氧化物材料104上，接着将金属氮化物材料沉积在开口117中以在高k材料119的暴露表面上形成共形阻挡层120。在一个或多个实施方式中，金属氮化物材料具有分子式TiXN或TaXN，其中Ti为钛，Ta为钽，X为金属，并且N为氮化物。在一个或多个实施方式中，X选自铝(Al)、硅(Si)、钨(W)、镧(La)、钇(Yt)、锶(Sr)或镁(Mg)中的一种或多种。在一些实施方式中，金属氮化物具有式TaN(氮化钽)。因此，在一个或多个实施方式中，金属氮化物材料选自氮化钛铝(TiAlN)、氮化钛硅(TiSiN)、氮化钛钨(TiWN)、氮化钽(TaN)、氮化硅钽(TaSiN)、氮化钽铝(TaAlN)、氮化钽钨(TaWN)、氮化钽(TaN)、氮化钛镧(TiLaN)、氮化钛钇(TiYN)、氮化钛锶(TiSrN)或氮化钛镁(TiMgN)中的一种或多种。
在一个或多个实施方式中，X以约5％至约50％的量存在于阻挡层中，包括约5％、约10％、约20％、约25％、约30％、约35％、约40％、约45％和约50％原子百分比。在一个或多个实施方式中，X以约5％至约50％的量存在于阻挡层中，包括约5％、约10％、约20％、约25％、约30％、约35％、约40％、约45％和约50％原子百分比。
在一个或多个实施方式中，阻挡层120通过原子层沉积来沉积。在一个或多个实施方式中，原子层沉积工艺是空间原子层沉积工艺。在一个或多个实施方式中，共形阻挡层120是衬里。在一个或多个实施方式中，共形阻挡层120在约300℃至约700℃范围内的温度下沉积。
在一个或多个实施方式中，阻挡层120与氧化物材料104的暴露表面基本上共形。如本文所使用，“基本上共形”的层是指厚度在各处(例如，在侧壁的顶部、中部和底部上和在间隙的底部上)大致相同的层。基本上共形的层的厚度的变化小于或等于约5％、2％、1％或0.5％。在一个或多个实施方式中，共形阻挡层120具有在约
Figure BDA0003371587580000091
至约
Figure BDA0003371587580000092
或约
Figure BDA0003371587580000093
至约
Figure BDA0003371587580000094
的范围内的厚度。在一个或多个实施方式中，共形阻挡层120具有约
Figure BDA0003371587580000095
或约
Figure BDA0003371587580000096
或约
Figure BDA0003371587580000097
或约
Figure BDA0003371587580000098
或约
Figure BDA0003371587580000099
或约
Figure BDA00033715875800000910
或约
Figure BDA00033715875800000911
或约
Figure BDA00033715875800000912
或约
Figure BDA00033715875800000913
或约
Figure BDA00033715875800000914
的厚度。在一个或多个实施方式中，阻挡层120的厚度小于约
Figure BDA00033715875800000915
在其他实施方式中，阻挡层120具有小于约
Figure BDA00033715875800000916
的厚度。
如图6B所示，在沉积共形高K层119和共形阻挡层120之后，通过开口117在共形阻挡层120上共形沉积α-钨层122。在一个或多个实施方式中，通过以下操作来形成α-钨层122：将表面暴露于硅前驱物以形成具有一定厚度的非晶硅层；和在非晶硅层上形成金属层，该金属层包含钨，该金属层通过将非晶硅层顺序地暴露于金属前驱物和反应物来形成，该金属前驱物包含氯化钨(WClx)、氧氯化钨(WOxClx)、氟化钨(WFx)等中的一种或多种，并且反应物包含氢。在一个或多个实施方式中，硅前驱物包括聚硅烷。聚硅烷可选自乙硅烷、丙硅烷、丁硅烷、异丁硅烷、新戊硅烷、环戊硅烷、己硅烷或环己硅烷中的一种或多种。在一个或多个实施方式中，在形成金属层之前，将非晶硅层暴露于脱气环境以去除脱气物质。脱气环境可基本上由惰性气体组成，该惰性气体包括但不限于氩、氦或氮中的一种或多种。
在一些实施方式中，可通过使硅前驱物的分压最大化而同时使晶片温度最小化来实现非晶硅(a-Si)形成。合适的硅前驱物包括但不限于聚硅烷(SixH)。例如，聚硅烷包括乙硅烷(Si2H6)、丙硅烷(Si3H8)、丁硅烷(Si4H10)、异丁硅烷、新戊硅烷(Si5H12)、环戊硅烷(Si5H10)、六硅烷(C6H14)、环己硅烷(Si6H12)或一般是SxHy(其中x＝2或更多)以及它们的组合。例如，具有适中处理温度和高蒸气压力的乙硅烷可单独地或与其他物质组合地用作硅前驱物。
在一些实施方式中，硅前驱物基本上仅包括乙硅烷。如本说明书和所附权利要求书所使用，短语“基本上仅乙硅烷”是指至少95％的活性物质是乙硅烷。可包括任何量的其他气体，诸如载气和惰性气体。
非晶硅层的厚度可取决于例如基板表面以及后续的膜和工艺而变化。在一些实施方式中，非晶硅层具有在约
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至约
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的范围内的厚度。在一个或多个实施方式中，非晶硅层具有在约
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至约
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的范围内、或在约
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至约
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的范围内、或在约
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至约
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的范围内的厚度。在一些实施方式中，非晶硅层的厚度大于
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且小于或等于约
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或
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在非晶硅层上形成金属层。金属层可通过任何合适的技术形成，包括但不限于原子层沉积(ALD)、等离子体增强原子层沉积(PE-ALD)、化学气相沉积(CVD)、等离子体增强化学气相沉积(PE-CVD)和物理气相沉积(PVD)。
金属层可包括任何合适的金属。在一些实施方式中，金属层包括钨或钼中的一种或多种。在一些实施方式中，金属层基本上由钨组成。在一些实施方式中，金属层基本上由钼组成。如就这一点所使用，术语“基本上由……组成”意指金属层大于或等于指定组分的约80原子％、85原子％、90原子％或95原子％。例如，基本上由钨组成的金属层具有大于或等于例如约90原子％的钨的组成。
在一些实施方式中，金属层通过CVD沉积。金属前驱物和反应物可共流到处理腔室中以在基板上沉积层。允许前驱物和反应物在气相中反应。
在一些实施方式中，金属层通过ALD沉积。在时域ALD工艺中，金属前驱物流入到处理腔室中以与表面反应。净化掉腔室中的多余的前驱物和副产物并使反应物流入到腔室中。前驱物和反应物不会在同一时间上处于处理腔室中，因此气相反应最少或没有气相反应。在空间ALD工艺中，金属前驱物流入到处理腔室的第一区段中，并且反应物同时地流入到处理腔室的第二区段中。第一区段和第二区段被气帘隔开以阻止在前驱物与反应物之间发生气相反应。使基板在第一区段与第二区段之间移动，以使表面顺序地暴露于前驱物和反应物。在一些实施方式中，通过将非晶硅层顺序地暴露于金属前驱物和反应物来沉积金属层。
金属前驱物可以是可用于沉积金属膜的任何合适的前驱物。在一些实施方式中，金属前驱物包括选自钨、钼和以上项的组合的金属。在一个或多个实施方式中，金属前驱物包括WCl6、WOxClx、WFx、MoClx、MoOxClx、MoFx和MoCl6中的一种或多种。在一些实施方案中，金属前驱物是含氟前驱物。已知氟可蚀刻硅表面。本公开内容的一些实施方式有利地允许使用氟前驱物，因为非晶硅层可形成为足以确保前驱物不会去除整个a-Si膜的厚度。
反应物可以是能够与表面上形成的物质反应的任何合适的反应物。例如，如果WCl6用作前驱物，则表面上将存在-WClx物质。该反应物能够与-WClx物质反应以产生α钨(W)膜122。在一个或多个实施方式中，α-钨膜122具有在约
Figure BDA0003371587580000111
至约
Figure BDA0003371587580000112
的范围内的厚度，包括约
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约
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约
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约
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约
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约
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约
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约
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约
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约
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约
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约
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约
Figure BDA00033715875800001115
和约
Figure BDA00033715875800001116
在一个或多个实施方式中，α-钨层122在约300℃至约500℃的范围内的温度下沉积。
参考图6C，在共形地沉积α-钨膜122之后，通过开口117在α-钨(W)膜122上沉积金属材料124。在一个或多个实施方式中，金属材料124填充开口117。在一个或多个实施方式中，金属材料124包括体钨(W)。
在一个或多个实施方式中，与TiN相比，TiXN或TaXN膜(其中X是选自但不限于铝(Al)、硅(Si)、钨(W)、镧(La)、钇(Y)、锶(Sr)或镁(Mg)中的一种或多种的金属)已经用作用于VNAND应用中的体钨(W)生长的成核和F阻挡层。TiXN或TaXN阻挡层/衬里在约450℃至约500℃下沉积，其中厚度的范围为约
Figure BDA00033715875800001117
至约
Figure BDA00033715875800001118
然后，在约500℃下沉积α-钨(W)层，接着在约400℃至约500℃的温度下沉积厚度为约
Figure BDA00033715875800001119
至约
Figure BDA00033715875800001120
的体钨(W)。不希望受理论的束缚，与包含TiN衬里相比，TiXN或TaXN膜使堆叠电阻率降低至少15％。与TiN衬里相比，TiSiN膜使从体W到基板的F渗透量减小了10倍。另外，与标准TiN或TaN衬里相比，更薄的TiXN或TaXN阻挡层使VNAND存储器结构的钨(W)填充量更大，这可能使VNAND应用的整体电阻率降低。
参考图7，如本领域技术人员所理解，沉积高K层119、沉积阻挡层120、沉积α-钨层122以及通过用金属材料124填充开口117而产生的任何覆盖层可然后可选地被去除以形成栅极126。高K层119、阻挡层材料120、α-钨层122和金属材料124的覆盖层可通过本领域技术人员已知的任何技术去除，包括但不限于化学机械平面化或蚀刻。
参考图7，在一个或多个实施方式中，沉积金属栅极材料124以填充氧化物材料层104之间的开口117并形成栅极126。栅极126可以是本领域技术人员已知的任何合适的导电材料。在一个或多个实施方式中，栅极材料124包括钨(W)、铜(Cu)、钴(Co)、铝(Al)、钌(Ru)、铱(Ir)、钼(Mo)、铂(Pt)、钽(Ta)、钛(Ti)或铑(Rh)中的一种或多种。在一个或多个实施方式中，栅极材料124包括钨(W)。在一个或多个实施方式中，栅极材料124通过原子层沉积来沉积。
参考图7，一个或多个实施方式涉及存储器结构，该存储器结构包括：硅材料104和金属栅极126的多个交替层150，该金属栅极126包括共形阻挡层120、共形α-钨层122和体钨层124；和存储器孔沟道108，该存储器孔沟道穿过多个交替层150形成并且具有沉积在存储器孔沟道108的第一表面、第二表面、第三表面上的共形多晶硅材料层116。
一个或多个实施方式涉及3D NAND存储器，该3D NAND存储器包括一个或多个实施方式的多个NAND存储器结构，这些NAND存储器结构以三维配置围绕存储器孔沟道108布置。在一些实施方式中，3D NAND存储器单元包括在存储器孔沟道108中、与多晶硅材料116接触的位线。
本公开内容的附加实施方式涉及用于形成所描述的存储器器件和方法的处理工具900，如图8所示。虽然图8所示的处理工具是空间ALD处理工具，但是本领域技术人员将认识到，范围不限于空间ALD工具。
群集工具900包括具有多个侧面的至少一个中央传送站921、931。机器人925、935定位在中央传送站921、931内，并且被配置为将机器人叶片和晶片移动到多个侧面中的每一者。
群集工具900包括连接到中央传送站的多个处理腔室902、904、906、908、910、912、914、916和918，该处理腔室也称为处理站。各种处理腔室提供与相邻处理站隔离的单独处理区域。处理腔室可以是任何合适的腔室，包括但不限于预清洁腔室、缓冲腔室、传送空间、晶片定向器/脱气腔室、低温冷却腔室、沉积腔室、退火腔室、蚀刻腔室和阻挡氧化物材料沉积腔室。处理腔室和部件的特定布置可根据群集工具而变化，并且不应被视为限制本公开内容的范围。
在一个或多个实施方式中，群集工具900包括阻挡层沉积腔室和α-钨沉积腔室。一些实施方式的阻挡层沉积腔室和α-钨沉积腔室包括原子层沉积腔室、等离子体增强原子层沉积腔室、化学气相沉积腔室、等离子体增强化学气相沉积腔室、空间原子层沉积腔室或物理沉积腔室中的一种或多种。在一个或多个实施方式中，群集工具900包括连接到中央传送站的预清洁腔室。
在图8所示的实施方式中，工厂接口950连接到群集工具900的前部。工厂接口950包括在工厂接口950的前部951上的装载腔室954和卸载腔室956。虽然装载腔室954被示出在左侧并且卸载腔室956被示出在右侧，但是本领域技术人员将理解，这仅代表一种可能的配置。
装载腔室954和卸载腔室956的大小和形状可根据例如在群集工具900中处理的基板而变化。在所示的实施方式中，装载腔室954和卸载腔室956的大小设定为保持晶片盒，该晶片盒中定位有多个晶片。
机器人952在工厂接口950内并且可在装载腔室954与卸载腔室956之间移动。机器人952能够将晶片从装载腔室954中的盒通过工厂接口950传送到装载锁定腔室960。机器人952还能够将晶片从装载锁定腔室962通过工厂接口950传送到卸载腔室956中的盒。如本领域技术人员将理解，工厂接口950可具有多于一个机器人952。例如，工厂接口950可具有在装载腔室954与装载锁定腔室960之间传送晶片的第一机器人和在装载腔室962与卸载腔室956之间传送晶片的第二机器人。
所示的群集工具900具有第一区段920和第二区段930。第一区段920通过装载锁定腔室960、962连接到工厂接口950。第一区段920包括第一传送腔室921，该第一传送腔室中定位有至少一个机器人925。机器人925也称为机器人晶片运输机构。第一传送腔室921相对于装载锁定腔室960、962、处理腔室902、904、916、918和缓冲腔室922、924位于中心。一些实施方式的机器人925是能够一次独立地移动多于一个晶片的多臂机器人。在一个或多个实施方式中，第一传送腔室921包括多于一个机器人晶片运输机构。第一传送腔室921中的机器人925被配置为在第一传送腔室921周围的腔室之间移动晶片。单独晶片承载在位于第一机器人机构的远侧端部处的晶片运输叶片上。
在第一区段920中处理晶片之后，晶片可通过穿通腔室传递到第二区段930。例如，腔室922、924可以是单向或双向穿通腔室。穿通腔室922、924可用于例如在第二区段930中进行处理之前对晶片进行低温冷却，或者允许晶片在移动回到第一区段920之前进行冷却或后处理。
系统控制器990与第一机器人925、第二机器人935、第一多个处理腔室902、904、916、918和第二多个处理腔室906、908、910、912、914通信。系统控制器990可以是可控制处理腔室和机器人的任何合适的部件。例如，系统控制器990可以是包括中央处理单元、存储器、合适的电路和存储设备的计算机。
工艺一般可作为软件例程存储在系统控制器990的存储器中，该软件例程在由处理器执行时致使工艺腔室执行本公开内容的工艺。软件例程还可由远离由处理器控制的硬件定位的第二处理器(未示出)存储和/或执行。本公开内容的方法的一些或全部也可在硬件中执行。因此，工艺可在软件中实现并使用计算机系统来执行，可在硬件(例如，专用集成电路或其他类型的硬件实现方式)中实现，或者可作为软件和硬件的组合实现。软件例程在由处理器执行时将通用计算机变换成控制腔室操作以使得执行工艺的专用计算机(控制器)。
在本文中可使用空间相对术语诸如“下面”、“下方”、“下部”、“上方”、“上部”等以便于进行说明来描述对如图所示的一个元件或特征与另一个元件或特征的关系。应当理解，这些空间相对术语旨在涵盖在使用或操作中的装置的除如图所示的取向之外的不同取向。类似地，如果附图中的装置上下倒转，那么被描述为在其他元件“下方”或“下面”的元件就将被取向为在其他元件或特征“上方”。因此，示例性术语“下方”可涵盖在……上方或在……下方的取向两者。装置可以其他方式取向(旋转90度或以其他取向)并相应地解释本文使用的空间相对描述语。
除非本文另外指明或与上下文明显矛盾，否则在描述本文讨论的材料和方法的上下文中(尤其是在所附权利要求书的上下文中)使用术语“一个/一种(a/an)”和“该/所述(the)”以及类似指称将理解为涵盖单数和复数两者。除非本文另外指明，否则本文对值的范围的表述仅旨在用作单独地提及落在该范围内的每个单独值的简要方法，并且每个单独值结合在说明书中，如同本文单独地表述一样。本文中描述的所有方法可任何合适的顺序执行，除非本文另有指明或明显地与上下文矛盾。除非本文另外要求保护，否则本文提供的任何和所有示例或者示例性语言(例如，“诸如”)的使用仅旨在更好地说明材料和方法并且不对范围构成限制。在说明书中的语言不应理解为指示任何非要求保护的要素对所公开的材料和方法的实践是必要的。
在整个本说明书中对“一个实施方式”、“某些实施方式”、“一个或多个实施方式”或“实施方式”的提及意指结合实施方式描述的特定特征、结构、材料或特性被包括在本公开内容的至少一个实施方式中。因此，在整个本说明书的各处出现诸如“在一个或多个实施方式中”、“在某些实施方式中”、“在一个实施方式中”或“在实施方式中”的短语不一定是指本公开内容的同一个实施方式。在一个或多个实施方式中，特定特征、结构、材料或特性以任何合适的方式组合。
尽管已经参考特定实施方式来描述本文的公开内容，但是将理解，这些实施方式仅说明本公开内容的原理和应用。本领域的技术人员将清楚，在不脱离本公开内容的精神和范围的情况下，可对本公开内容的方法和设备做出各种修改和变化。因此，本公开内容旨在包括在所附权利要求书及其等效物的范围内的修改和变化。

Claims (20)

1.一种存储器结构，包括：
硅材料和金属栅极的多个交替层，所述金属栅极包括共形阻挡层、共形α-钨(W)层和体钨层；和
存储器孔沟道，所述存储器孔沟道穿过所述多个交替层形成并且具有沉积在所述存储器孔沟道的第一表面、第二表面、第三表面上的共形多晶硅材料层。
2.如权利要求1所述的存储器结构，其中所述阻挡层包括具有化学式TiXN或TaXN的金属氮化物。
3.如权利要求2所述的存储器结构，其中所述X选自铝(Al)、硅(Si)、钨(W)、镧(La)、钇(Yt)、锶(Sr)或镁(Mg)中的一种或多种。
4.如权利要求2所述的存储器结构，其中所述金属氮化物材料选自氮化钛铝(TiAlN)、氮化钛硅(TiSiN)、氮化钛钨(TiWN)、氮化钽(TaN)、氮化硅钽(TaSiN)、氮化钽铝(TaAlN)、氮化钽钨(TaWN)、氮化钽(TaN)、氮化钛镧(TiLaN)、氮化钛钇(TiYN)、氮化钛锶(TiSrN)或氮化钛镁(TiMgN)中的一种或多种。
5.如权利要求2所述的存储器结构，其中所述阻挡层具有在约
Figure FDA0003371587570000011
至约
Figure FDA0003371587570000012
的范围内的较小的厚度。
6.如权利要求4所述的存储器结构，其中X以约5％至约50％的量存在于所述阻挡层中。
7.如权利要求1所述的存储器结构，其中所述α-钨(W)层具有在约
Figure FDA0003371587570000013
至约
Figure FDA0003371587570000014
的范围内的厚度。
8.如权利要求1所述的存储器结构，其中所述金属栅极进一步包括高K层。
9.一种3D NAND存储器单元，包括多个如权利要求1所述的存储器结构，所述多个存储器结构以三维配置围绕所述存储器孔沟道布置。
10.如权利要求8所述的3D NAND存储器单元，进一步包括位线，所述位线在所述存储器孔沟道中，与所述共形多晶硅材料层接触。
11.一种形成存储器结构的方法，所述方法包括：
沉积氮化物材料和氧化物材料的多个交替层；
穿过所述多个交替层蚀刻存储器孔以形成所述交替层的第一暴露表面和第二暴露表面，所述存储器孔具有宽度；
将共形多晶硅层沉积在所述存储器孔中；
去除所述氮化物材料以形成开口并且暴露所述氧化物材料；
将高K层共形地沉积在所述开口中；
将阻挡层共形地沉积在所述开口中的所述高K层上，所述阻挡层包括TiXN或TaXN；
将α-钨(W)层共形地沉积在所述阻挡层上；
将金属材料沉积在所述α-钨(W)层上；和
可选地，平面化所述存储器结构。
12.如权利要求11所述的方法，其中所述X选自铝(Al)、硅(Si)、钨(W)、镧(La)、钇(Yt)、锶(Sr)或镁(Mg)中的一种或多种。
13.如权利要求11所述的方法，其中所述金属氮化物材料选自氮化钛铝(TiAlN)、氮化钛硅(TiSiN)、氮化钛钨(TiWN)、氮化钽(TaN)、氮化硅钽(TaSiN)、氮化钽铝(TaAlN)、氮化钽钨(TaWN)、氮化钽(TaN)、氮化钛镧(TiLaN)、氮化钛钇(TiYN)、氮化钛锶(TiSrN)或氮化钛镁(TiMgN)中的一种或多种。
14.如权利要求11所述的方法，其中所述阻挡层具有在约
Figure FDA0003371587570000021
至约
Figure FDA0003371587570000022
的范围内的厚度。
15.如权利要求12所述的方法，其中X以约5％至约50％的量存在于所述阻挡层中。
16.如权利要求11所述的方法，其中所述α-钨(W)层具有在约
Figure FDA0003371587570000023
至约
Figure FDA0003371587570000024
的范围内的厚度。
17.如权利要求11所述的方法，其中在约300℃至约700℃的范围内的温度下通过原子层沉积来沉积所述阻挡层。
18.如权利要求11所述的方法，其中在约300℃至约700℃的范围内的温度下沉积所述α-钨(W)层。
19.一种处理工具，包括：
中央传送站，所述中央传送站包括被配置为移动晶片的机器人；
多个处理站，每个处理站连接到所述中央传送站并且提供与相邻处理站的处理区域分开的处理区域，所述多个处理站包括阻挡层沉积腔室和α-钨(W)沉积腔室；和
控制器，所述控制器连接到所述中央传送站和所述多个处理站，所述控制器被配置为激活所述机器人以在所述处理站之间移动所述晶片和控制在所述处理站中的每一者中发生的工艺。
20.如权利要求19所述的处理工具，其中阻挡氧化物材料沉积腔室包括空间原子层沉积腔室。
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US20230005945A1 (en) 2023-01-05
JP2022533201A (ja) 2022-07-21
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