CN114068524A - Nonvolatile memory layout and nonvolatile memory - Google Patents
Nonvolatile memory layout and nonvolatile memory Download PDFInfo
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- CN114068524A CN114068524A CN202111424329.7A CN202111424329A CN114068524A CN 114068524 A CN114068524 A CN 114068524A CN 202111424329 A CN202111424329 A CN 202111424329A CN 114068524 A CN114068524 A CN 114068524A
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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Abstract
The invention provides a nonvolatile memory layout and a nonvolatile memory, wherein the nonvolatile memory layout comprises a control gate layout and a word line layout, the control gate layout comprises a plurality of control gate graph groups, and each control gate graph group comprises two control gate graphs. The grid pattern comprises a grid pattern which is in a straight bar shape and extends along the second direction and a protruding pattern which extends out of the middle position of the grid pattern, the protruding pattern protrudes out of the grid pattern in the first direction and is connected with the grid pattern into a whole, and two protruding patterns in each control grid pattern group are arranged in a back-to-back mode. The interval region between the two word line patterns is aligned with the raised pattern, namely the interval region between the word line patterns is close to the back of the raised pattern, so that the word line structure in the memory is spaced from the raised part of the control gate structure, and the short circuit between the raised part of the control gate structure and the word line can be avoided.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a nonvolatile memory layout and a nonvolatile memory.
Background
Flash memory (flash) is a safe and fast memory bank, and becomes the most main carrier of data and programs in embedded systems due to a series of advantages of small volume, large capacity, low cost, no loss of power-down data and the like. In recent years, with the rapid development of the intelligent electronic product market, the use of various MCUs (micro controller units) and socs (System-on-Chip) has been advanced to various aspects of daily life such as automotive electronics, industrial control, and medical products. In a conventional non-volatile memory (NORD flash), a connection structure for electrically connecting two control gates is generally in a zigzag shape, and as the NORD flash devices are miniaturized, the design rule of the devices becomes smaller and smaller, the connection structure of the conventional control gates is no longer applicable due to process limitations.
Disclosure of Invention
The invention aims to provide a nonvolatile memory layout and a nonvolatile memory so as to increase a process window of a connection structure in a control gate of the nonvolatile memory.
To achieve the above object, the present invention provides a nonvolatile memory layout, which includes: the control gate layout comprises a plurality of control gate graphic groups which are arranged in parallel along a first direction and extend along a second direction, the first direction is vertical to the second direction, each control gate graphic group comprises two control gate graphics which are in mirror symmetry, each gate graphic comprises a gate graphic which is in a straight bar shape and extends along the second direction and a protruding graphic which extends out of the middle position of the gate graphic, the protruding graphic protrudes out of the gate graphic in the first direction and is connected with the gate graphic into a whole, and the two protruding graphics in each control gate graphic group are arranged in an opposite way;
the word line territory, include along first direction parallel arrangement and along a plurality of word line figure groups that the second direction extends, every in the control gate figure group be provided with one between two control gate figures word line figure group, wherein, every word line figure group is including along two word line figures that are the straight bar shape that the second direction interval set up, the interval region between two word line figures is aimed at protruding figure.
Optionally, in the layout of the nonvolatile memory, each gate pattern includes a first gate pattern and a second gate pattern arranged in parallel, and the protrusion pattern is disposed between the first gate pattern and the second gate pattern and integrally connected to the first gate pattern and the second gate pattern.
Optionally, in the nonvolatile memory layout, the nonvolatile memory layout further includes a contact hole layout, the contact hole layout includes a plurality of contact hole pattern groups, one contact hole pattern group is provided in each control gate pattern group, wherein each contact hole pattern group includes two contact hole patterns, and the two contact hole patterns correspond to the two control gate patterns of the control gate pattern group respectively.
Optionally, in the nonvolatile memory layout, a projection of each contact hole pattern on the control gate layout is located in the protrusion pattern.
Optionally, in the non-volatile memory layout, the two contact hole patterns in each contact hole pattern group are arranged in a staggered manner in position.
Optionally, in the nonvolatile memory layout, the nonvolatile memory layout further includes an active region layout, the active region layout includes at least two active region patterns arranged in parallel along the second direction and extending along the first direction, and each word line pattern crosses all the active region patterns.
Optionally, in the non-volatile memory layout, each control gate pattern crosses all the active region patterns.
Based on the same inventive concept, the invention also provides a nonvolatile memory, wherein the nonvolatile memory layout is formed, and the nonvolatile memory comprises:
a semiconductor substrate;
the control gate structure groups are arranged in parallel along a first direction and extend along a second direction, the first direction is perpendicular to the second direction, each control gate structure group comprises two control gate structures in mirror symmetry, each control gate structure comprises a gate part in a straight strip shape and along the second direction and a bulge part extending from the middle position of the gate part, the bulge parts protrude out of the gate part in the first direction and are connected with the gate part into a whole, and the two bulge parts in each control gate pattern group are arranged in an opposite mode;
the control gate structure group comprises a plurality of control gate structures, a plurality of word line structure groups and a plurality of bulges, the plurality of word line structure groups are formed on the semiconductor substrate, the plurality of word line structure groups are arranged in parallel along the first direction and extend along the second direction, one word line structure group is formed between the two control gate structures of each control gate structure group, each word line structure group comprises two straight strip-shaped word line structures which are arranged along the second direction at intervals, and the interval openings between the two word line structures are aligned to the bulges.
Optionally, in the nonvolatile memory, each of the gate portions includes a first gate portion and a second gate portion arranged in parallel, and the protrusion portion is disposed between the first gate portion and the second gate portion and integrally connected to the first gate portion and the second gate portion.
Optionally, in the nonvolatile memory, the nonvolatile memory further includes: the touch structure group comprises a plurality of touch structure groups formed on the control gate structure groups, wherein one touch structure group is formed on each control gate structure group, each touch structure group comprises two touch structures, and the two touch structures correspond to the two control gate structures in the control gate structure group respectively.
Optionally, in the nonvolatile memory, each of the contact structures is located on and electrically connected to a bump of the corresponding control gate structure.
Optionally, in the nonvolatile memory, the two contact structures in each of the contact structure groups are arranged in a staggered manner.
In the nonvolatile memory layout and the nonvolatile memory provided by the invention, the nonvolatile memory layout comprises a control gate layout and a word line layout, the control gate layout comprises a plurality of control gate graphic groups, and each control gate graphic group comprises two control gate graphics in mirror symmetry. The grid pattern comprises a grid pattern which is in a straight strip shape and extends along the second direction and a protruding pattern which extends out of the middle position of the grid pattern, the protruding pattern protrudes out of the grid pattern in the first direction and is connected with the grid pattern into a whole, and two protruding patterns in each control grid pattern group are arranged in a back-to-back mode. The word line domain includes a plurality of word line figure groups, every be provided with one between two control gate figures in the control gate figure group word line figure group, wherein, every word line figure group is including along two word line figures that are the straight bar that the second direction interval set up, the interval region between two word line figures aligns protruding figure, the interval region between the word line figure is close to the back of protruding figure promptly, can make the word line structure in the memory and the bellying of control gate structure mutually separate like this, can avoid taking place the short circuit between the bellying of control gate structure and the word line to the process window of the bellying in the control gate structure has been increased. In addition, because two protruding parts in each control gate structure group are arranged back to back, compared with the prior art, the occupied area of a connecting structure (the protruding parts are used as the connecting structure) can be reduced.
Drawings
FIGS. 1-4 are schematic diagrams of non-volatile memory layouts according to embodiments of the present invention;
FIGS. 5-6 are schematic structural diagrams of a nonvolatile memory according to an embodiment of the present invention;
wherein the reference numerals are as follows:
110-control gate pattern group; 111. 112-control gate pattern; 1111. 1121-gate pattern; 1111a first grid electrode pattern; 1111 b-a second gate pattern; 1112. 1122-a raised pattern;
120-word line pattern groups; 121. 122-word line pattern;
130-contact hole pattern group; 131. 132-contact hole pattern;
140-active area pattern;
200-a semiconductor substrate; 201-shallow trench isolation structures; 202-an inter-gate dielectric layer;
210-control gate structure group; 211. 212-a control gate structure; 2111. 2121-gate portion; 2112. 2122-a boss; 2112-control gate structure; 2111a, 2111b, 2112a, 2112 b-gate portion;
220-set of word line structures; 220 a-spaced openings; 221. 222-word line architecture;
230-set of contact structures; 231. 232-contact structure.
Detailed Description
The non-volatile memory layout and the non-volatile memory proposed by the present invention are further described in detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
FIG. 1 is a schematic diagram of a non-volatile memory layout of an embodiment of the present invention. As shown in fig. 1, the nonvolatile memory layout includes a control gate layout, and the control gate layout is used to form a plurality of control gate structures of the nonvolatile memory. The control gate layout comprises a plurality of control gate pattern groups 110 which are arranged in parallel along a first direction Y and extend along a second direction X, the first direction Y is perpendicular to the second direction X, each control gate pattern group 110 comprises two control gate patterns 111 and two control gates 112 which are mirror symmetry, and the control gate patterns 111 and the control gate patterns 112 are mirror symmetry, so that the control gate pattern groups 110 are consistent in shape.
As shown in fig. 1, in the present embodiment, the control gate pattern 111 includes a gate pattern 1111 having a straight bar shape and extending along the second direction X, and a protrusion pattern 1112 protruding from a middle position of the gate pattern 1111. The control gate pattern 112 includes a gate pattern 1121 having a straight bar shape and extending along the second direction X, and a protrusion pattern 1122 protruding from a middle position of the gate pattern 1121. The gate patterns 111 and 112 are used to form a control gate structure in a nonvolatile memory, and the protrusion patterns 1112 and 1121 are used to form protrusions in the memory so as to electrically connect two gate portions.
Each of the protruding patterns 1122 protrudes from the gate pattern 1121 in the first direction Y and is connected with the gate pattern 1121 as a whole, that is, the control gate pattern 111 is in a shape of a Chinese character 'tu'; each of the protrusion patterns 1112 protrudes from the gate pattern 112 in the first direction and is connected with the gate pattern 1122 into a whole, that is, the control gate pattern 112 is in a shape of a convex, that is, a line segment of the gate pattern 1121 and a line segment of the gate pattern 1121 away from the protrusion patterns 1112 are flush. The protrusion patterns 1112 and the protrusion patterns 1122 in each control gate pattern group 110 are disposed opposite to each other, that is, the positions of the protrusion patterns 1112 and the protrusion patterns 1122 are located on a straight line parallel to the first direction Y, and the direction in which the protrusion patterns 1112 protrude from the gate patterns 1111 is opposite to the direction in which the protrusion patterns 1122 protrude from the gate patterns 1121.
Further, each of the gate patterns 1111 includes a first gate pattern 1111a and a second gate pattern 1111b arranged in parallel, and the protrusion pattern 1112 is disposed between the first gate pattern 1111a and the second gate pattern 1111b and integrally connected to the first gate pattern 1111a and the second gate pattern 1111 b. Each of the gate patterns 1121 includes a first gate pattern and a second gate pattern arranged in parallel, and the protrusion pattern 1122 is disposed between the first gate pattern and the second gate pattern and integrally connected to the first gate pattern and the second gate pattern. The first gate pattern 1111a and the second gate pattern 1111b are used to form gate portions (herein, referred to as control gates) of two adjacent memory arrays (cell arrays), the protrusion pattern 1122 is used to form protrusions, and the protrusions can serve as a connection structure for connecting the gate portions (herein, referred to as a first gate portion and a second gate portion in a device) of two adjacent memory arrays (cell arrays) and providing a region of a contact region (pickup up) for the device.
In this embodiment, as shown in fig. 2, the nonvolatile memory layout further includes a word line layout, the word line layout structure includes a plurality of word line pattern groups 120 arranged in parallel along the first direction Y and extending along the second direction X, and the word line pattern groups 120 are used to form word line structure groups in the nonvolatile memory. One of the word line pattern groups 120 is disposed between the two control gate patterns 111, 112 in each of the control gate pattern groups 110. Each of the word line pattern groups 120 includes two word line patterns 121, 122 spaced apart along the second direction X, and a spacing region a is provided between the word line patterns 121 and the word line patterns 122, and the spacing region a is aligned with the protrusion patterns 1112, 1122. Due to the spacing region A between the word line pattern 121 and the word line pattern 122, the process window of the convex part of the control gate structure is increased, and short circuit between the convex part of the control gate structure and the word line can be avoided. And the size of the bump of the control gate structure in an actual nonvolatile memory is reduced, thereby reducing the area occupied by the bump.
As shown in fig. 3, in this embodiment, the nonvolatile memory layout further includes a contact hole layout structure, the contact hole layout structure includes a plurality of contact hole pattern groups 130, one contact hole pattern group 130 is disposed in each control gate pattern group 110, each contact hole pattern group 130 includes two contact hole patterns 131 and 132, the contact hole pattern 131 corresponds to the control gate pattern 111, and the contact hole pattern 132 corresponds to the control gate pattern 112.
Wherein the contact hole patterns 131, 132 are used to define the location of contact structures in the memory. Preferably, the contact hole patterns 131 and 132 in each of the contact hole pattern groups 130 are staggered in position, so that the contact hole patterns 131 and 132 are prevented from being connected together, thereby preventing two adjacent contact structures in the nonvolatile memory from being connected together and further preventing short circuit.
As shown in fig. 4, the nonvolatile memory layout further includes an active region layout, the active region layout includes at least two active region patterns 140 arranged in parallel along the second direction X and extending along the first direction Y, and the active region patterns 140 are used to define the positions of active regions in the nonvolatile memory.
In this embodiment, each of the control gate patterns 111 and 112 crosses all of the active area patterns 140, and each of the word line patterns 121 and 122 crosses all of the active area patterns 140.
It should be noted that, in the layout structure, the patterns of each layer of the layout structure usually use the minimum design rule. For this reason, in the present embodiment, the minimum area of a single active region pattern 140 satisfies the DRC (design rule check) rule.
Based on the same inventive concept, the invention also provides a nonvolatile memory, which is formed by adopting the nonvolatile memory layout provided by the implementation.
Fig. 5 to 6 are schematic structural diagrams of the nonvolatile memory according to the embodiment of the present invention. As shown in fig. 5 and 6, the nonvolatile memory includes: a semiconductor substrate 200; a plurality of control gate structure groups 210 formed on the semiconductor substrate 200, wherein the plurality of control gate structure groups 210 are arranged in parallel along a first direction Y and extend along a second direction X, the first direction Y is perpendicular to the second direction X, and both the first direction Y and the second direction X are horizontal directions of the semiconductor substrate 200. Each control gate structure group 210 includes a control gate structure 211 and a control gate structure 212 which are mirror symmetric.
Each of the control gate structures 211 includes a gate portion 2111 in a straight bar shape extending along the second direction X, and a protrusion portion 2112 protruding from a middle position of the gate portion 2111, wherein the protrusion portion 2112 protrudes from the gate portion 2111 in the first direction Y and is integrally connected to the gate portion 2111. Each of the control gate structures 212 includes a gate portion 2121 having a straight strip shape and extending along the second direction X, and a protruding portion 2122 protruding from a middle position of the gate portion 2121, wherein the protruding portion 2122 protrudes from the gate portion 2121 in the first direction Y and is integrally connected to the gate portion 2121. The gate portions include a first gate portion 2112a and a second gate portion 2112b, the first gate portion 2112a and the second gate portion 2112b can be used as control gates of two adjacent memory arrays (cell array), and the protruding portions 2112 and 2122 are used for connecting the control gates of the two adjacent memory arrays (cell array) (i.e., the first gate portion 2112a and the second gate portion 2112b) to achieve electrical connection between the control gates of the two adjacent memory arrays (cell array) and provide a region of a contact region (pinckup) for the device.
The semiconductor substrate 200 is made of silicon; in other embodiments, the material of the semiconductor substrate 200 may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the protrusion 2112 and the protrusion 2122 in each control gate structure group 110 are disposed opposite to each other, so that the distance between the word line structure 221 and the word line structure 222 and the protrusions 2112 and 2122 can be increased, short circuit between the protrusion 2112 of the control gate structure and the word line structures 221 and 222 is avoided, and the process windows of the protrusion 2112 and the protrusion 2122 in the control gate structure are increased. In addition, the process window of the contact structures formed on the raised portions 2112 and 2122 can be increased, and short circuit between the contact structures and the word line structures can be avoided. In this embodiment, the control gate structures 211 and 212 may be made of doped polysilicon.
In addition, a floating gate layer, an inter-gate dielectric layer 102 and a shallow trench isolation structure 101 are further formed between the semiconductor substrate 200 and the plurality of control gate structure groups 210, and the shallow trench isolation structure 101 penetrates through the floating gate layer and the floating gate oxide layer. The inter-gate dielectric layer 102 includes a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top, and for better illustrating the non-volatile memory of this embodiment, the floating gate layer and the inter-gate dielectric layer are not described, and the floating gate layer is not shown. And, the protrusions 2112, 2122 are aligned with the shallow trench isolation structure 101.
As shown in fig. 5, the nonvolatile memory further includes a plurality of word line structure groups 220 formed on the semiconductor substrate 200, the word line structure groups 220 are arranged in parallel along the first direction Y and extend along the second direction X, wherein each word line structure group 220 includes two straight bar-shaped word line structures 221 and 222 arranged at intervals along the second direction X, a spacing region a is formed between the word line structure 221 and the word line structure 222, and the spacing region a between the word line structure 221 and the word line structure 222 is aligned with the protrusion 2112, that is, the spacing region between the word line structure 221 and the word line structure 222 is close to the back of the protrusion 2112, so that the distance between the contact structure formed on the protrusion and the word line structures 221 and 221 can be increased, and short circuit between the word line structures 221 and 222 and the contact structure can be avoided. The word line structures 221 and 222 in this embodiment are made of polysilicon.
In this embodiment, the nonvolatile memory further includes a plurality of contact structure groups 230 formed on the plurality of control gate structure groups 210, wherein one contact structure group 230 is formed on each control gate structure group 210, the contact structure group 230 includes two contact structures 231 and 232, the contact structures 231 and 232 correspond to the control gate structures 2111 and 2112, respectively, that is, the contact structure 231 corresponds to the control gate structure 2111, and the contact structure 232 corresponds to the control gate structure 2112. The contact structures 231 and 232 are made of metal, such as tungsten or copper.
Preferably, the contact structures 231 and 232 of each contact structure group 230 are arranged in a staggered manner, so as to avoid short circuit between the contact structures 231 and 232.
In addition, in this embodiment, the nonvolatile memory is a NORD flash memory.
In summary, in the nonvolatile memory layout and the nonvolatile memory provided by the invention, the nonvolatile memory layout comprises a control gate layout and a word line layout, the control gate layout comprises a plurality of control gate pattern groups, and each control gate pattern group comprises two control gate patterns in mirror symmetry. The grid pattern comprises a grid pattern which is in a straight strip shape and extends along the second direction and a protruding pattern which extends out of the middle position of the grid pattern, the protruding pattern protrudes out of the grid pattern in the first direction and is connected with the grid pattern into a whole, and two protruding patterns in each control grid pattern group are arranged in a back-to-back mode. The word line domain includes a plurality of word line figure groups, every be provided with one between two control gate figures in the control gate figure group word line figure group, wherein, every word line figure group is including along two the word line figures that are the straight bar that the second direction interval set up, the interval region between two word line figures is aimed at protruding figure, the interval region between the word line figure is close to the back of protruding figure promptly, so can make the word line structure in the memory and the bellying of control gate structure separate mutually, can avoid taking place the short circuit between the bellying of control gate structure and the word line from this.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (12)
1. A non-volatile memory layout, the non-volatile memory layout comprising:
the control gate layout comprises a plurality of control gate graphic groups which are arranged in parallel along a first direction and extend along a second direction, the first direction is vertical to the second direction, each control gate graphic group comprises two control gate graphics which are in mirror symmetry, each gate graphic comprises a gate graphic which is in a straight bar shape and extends along the second direction and a protruding graphic which extends out of the middle position of the gate graphic, the protruding graphic protrudes out of the gate graphic in the first direction and is connected with the gate graphic into a whole, and the two protruding graphics in each control gate graphic group are arranged in an opposite way;
the word line layout comprises a plurality of word line graphic groups which are arranged in parallel along the first direction and extend along the second direction, each word line graphic group is arranged between two control grid graphics in the control grid graphic group, each word line graphic group comprises two straight bar-shaped word line graphics which are arranged at intervals along the second direction, and the interval area between the two word line graphics aligns to each two protruding graphics in the control grid graphic group.
2. The non-volatile memory layout of claim 1, wherein each of the gate patterns comprises a first gate pattern and a second gate pattern arranged in parallel, and the protrusion pattern is disposed between and integrally connected to the first gate pattern and the second gate pattern.
3. The non-volatile memory layout of claim 1 or 2, further comprising a contact hole layout, the contact hole layout comprising a plurality of contact hole pattern groups, one of the contact hole pattern groups being provided in each of the control gate pattern groups, wherein each of the contact hole pattern groups comprises two contact hole patterns, the two contact hole patterns corresponding to two of the control gate patterns of the control gate pattern group, respectively.
4. The non-volatile memory layout of claim 3, wherein a projection of each of said contact hole patterns on said control gate layout is located within said bump pattern.
5. The non-volatile memory layout of claim 4, in which the two contact hole patterns in each of the contact hole pattern groups are arranged staggered in position.
6. The non-volatile memory layout of claim 5, further comprising an active area layout, the active area layout comprising at least two active area patterns arranged in parallel along the second direction and extending along the first direction, each of the word line patterns spanning all of the active area patterns.
7. The non-volatile memory layout of claim 6 wherein each said control gate pattern spans all of said active region patterns.
8. A non-volatile memory formed using a non-volatile memory layout as claimed in any one of claims 1 to 7, the non-volatile memory comprising:
a semiconductor substrate;
the control gate structure groups are arranged in parallel along a first direction and extend along a second direction, the first direction is perpendicular to the second direction, each control gate structure group comprises two control gate structures in mirror symmetry, each control gate structure comprises a gate part in a straight strip shape and extending along the second direction and a bulge part extending from the middle position of the gate part, the bulge parts protrude out of the gate part in the first direction and are connected with the gate part into a whole, and the two bulge parts in each control gate pattern group are arranged in an opposite mode;
the control gate structure group comprises a plurality of control gate structures, a plurality of word line structure groups and a plurality of bulges, the plurality of word line structure groups are formed on the semiconductor substrate, the plurality of word line structure groups are arranged in parallel along the first direction and extend along the second direction, one word line structure group is formed between the two control gate structures of each control gate structure group, each word line structure group comprises two straight strip-shaped word line structures which are arranged along the second direction at intervals, and the interval openings between the two word line structures are aligned to the bulges.
9. The nonvolatile memory according to claim 8, wherein each of the gate portions includes a first gate portion and a second gate portion arranged in parallel, and the protrusion portion is provided between and integrally connected to the first gate portion and the second gate portion.
10. The non-volatile memory as in claim 9, wherein the non-volatile memory further comprises: the control grid structure group comprises a plurality of control grid structure groups, wherein each control grid structure group is provided with one contact structure group, each contact structure group comprises two contact structures, and the two contact structures correspond to the two control grid structures in the control grid structure group respectively.
11. The non-volatile memory of claim 10, wherein each of the contact structures is located on and electrically connected to a bump of a respective corresponding controlled gate structure.
12. The non-volatile memory of claim 11, wherein the two contact structures in each of the contact structure groups are staggered in position.
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| TWI836587B (en) * | 2022-09-02 | 2024-03-21 | 華邦電子股份有限公司 | Non-volatile memory structure and method for forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI836587B (en) * | 2022-09-02 | 2024-03-21 | 華邦電子股份有限公司 | Non-volatile memory structure and method for forming the same |
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