JP3129422B2 - Split gate memory array having staggered floating gate rows and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention generally relates to non-volatile memory arrays (eg, EP
ROM), and more particularly, each cell is a fully insulated floating gate and memory that can be charged to a programmed state by injecting hot electrons through an insulator. A memory array having a plurality of memory cells having an asymmetric split gate configuration with an electrically accessible control gate that can be used to address cells. The present invention more particularly comprises
The present invention relates to a configuration and / or a method for improving the integration degree and / or manufacturing yield of such a memory array.

Prior Art Memory arrays with virtual grounding structures are known.
In such a structure, a plurality of elongated conductive semiconductor regions are integrally formed as bit lines in a semiconductor substrate, each of which has opposed first and second end portions. I have. Opposite end portions of each bit line function as a drain of the first split gate transistor and also function as a source of the second split gate transistor adjacent in the lateral direction. The configuration and operating characteristics of the split gate transistor were described on October 13, 1983 by the inventor E. Ha.
No. 4,409,723 issued to Rari.

While a virtual grounding structure integrates a large number of memory cells within a limited area of an integrated circuit chip and provides an effective configuration for manufacturing such chips in high volume, it has several advantages. Has limited conditions. It is an object of the present invention to provide a structural layout that allows a designer to overcome limitations on the degree of integration of a virtual ground structure. Understanding the interactions between the functional components of the virtual grounding structure and the manufacturing steps used to form them, why limitations on integration occur, and how the present invention addresses that It is easy to understand whether such restriction conditions are eliminated.

FIG. 1 is a schematic diagram illustrating a memory array 10 having a virtual ground configuration. Briefly, a memory array
10 is a relatively large number (j × k) of split gate transistors
In order to form a rectangular matrix by arranging Q ₁₁ , Q ₁₂ , Q _{13 ,.}
FIG. A number of bit lines BL ₁ , BL ₂ , BL ₃ ,..., BL _{k + 1} are formed in the substrate 15 by diffusion.
Note that k is an integer, and may be equal to, for example, a power of 2 such as 256, 512, 1024, or 2048. These bit lines are made of a conductive semiconductor material such as, for example, doped N-type silicon. Each bit line is extended and extends on the substrate in the longitudinal direction (y direction). A plurality of bit lines are repeated in the horizontal direction (x direction) over the surface of the substrate 15 at a predetermined first pitch _PBL . Each opposing portions of the left end and right end portions 11 and 12 are shown as D and S of the bit line BL ₂ to BL _k, respectively, it acts as a drain region and a source region of the transistor Q ₁₁ -Q _jk .

The array 10 further includes a number of conductive word lines WL ₁ , WL ₂ ,
..., is configured to have a WL _j, these word lines are provided repeatedly over the surface of the substrate 15 at a predetermined pitch P _WL in the y-direction. (J is an integer and can be, for example, equal to a multiple of 2 such as 256, 512, 1024 or 2048.) These word lines are preferably bit lines BL _{1 to} BL _{k + 1} And a highly doped polysilicon strip disposed to insulatively overlap both portions of the substrate surface between the bit lines. Word lines WL ₁ -WL _j are connected to bit lines BL ₁ -B
_{Lk + 1} extends orthogonally above, and row i (i is 1 ≦ i ≦
The control gate portion of the corresponding node N _Xi pair of transistors are present within the same row i relative to Q _i1 -Q _iq of each word line WL _i is X address unit 18 integer) in the range of j 14
And are interconnected. X address unit 18, selectively activating the individual one of the word lines WL ₁ -WL _j, at that time, during a read or a write (programming) period of the array, the memory array 10 Address a row of transistors (memory cells).

The degree of integration of array 10 is determined when the bit line and word line pitch values, _PBL and _PWL, are selected. The x × y substrate area A _cell to be assigned to each cell of the memory array 10 is fixed to the product P _{BL PWL} . As will be readily appreciated by those skilled in the art, this assigned cell area A _cell is a very important factor when manufacturing integrated circuit chips.
It determines how many dies can be integrated on each production wafer, determines the production yield of the production line, and allows the die of the preselected dimensions to be, for example, 1M.
Bits, 4M bits or higher (M = 1,
048,576) is determined whether it is possible to mass-produce a device having a relatively large memory capacity. These latter factors determine whether a particular design of an IC chip satisfies the industry's demand for increased memory capacity at a lower cost per bit. To meet industry requirements, minimize die area, maximize the number of memory cells on each die, and simultaneously ensure that electrical and mechanical requirements of pre-specified circuit designs are met. It is generally desirable to maximize the number of dies on each ware in an aspect.

The pitch value, _PBL and _PWL cannot be arbitrarily selected. These relate both to the functional design requirements of the integrated circuit and to the miniaturization capabilities of the available manufacturing processes.
For example, in the embodiment of FIG. 1, the bit lines BL ₁ -BL
_{k + 1} is the array 10 in a manner that ensures that the source and drain regions of the transistors in adjacent transistor rows have the specified source and drain voltage levels at the source and drain regions of these transistors. Must be designed to couple to the respective contact nodes N _{Y1 to} N _{Y (k + 1)} . These contact nodes connect the diffused bit lines BL ₁ -BL _{k + 1} of the substrate to the metal lines ML ₁ existing above the substrate.
ML _{k + 1} through vias or through conductors. These metal lines connect the bit line to Y
It is coupled to the address operation / write operation / detection operation unit 20. There is one-to-one correlation between the respective and diffusion forming bit lines of the metal wire, thus, the metal lines ML ₁ to ML _{k + 1} and the bit lines BL ₁ to BL _{k + 1} is preferably , With the same pitch _PBL over the surface of the substrate.

Unit 20 is also referred to as Y address unit 20,
It reduces the voltage at each of the contact nodes N _Y1 −N _{Y (k + 1)} to a low voltage V _L (eg, ground), an intermediate voltage V _I (eg, + 2V).
And a circuit for switchably setting to one of a plurality of preselected voltage levels having a high voltage V _H (eg, + 9V). The Y address unit 20 is operated such that the desired one of the transistors Q ₁₁ -Q _jk can be individually addressed for programming or writing or reading.

Bit lines BL ₁ -BL _{k + 1} are not perfect electrical conductors, but rather impurity doped (N ⁺ ) semiconductor regions, and the semiconductor material is typically metal lines ML ₁ -ML _{k + 1} Because it is higher than the metal material normally used to form
The segment of each bit line (using bit line BL _k as an example) has a non-negligible segment resistance
It can be characterized as having R _y1 , R _y2 , R _y3 , ..., R _yj . The resistance of each segment is proportional to its length and inversely proportional to its width. The total resistance separating the contact node N _Yk from the source region of the transistor Q _1k is (for simplicity, it is assumed here that Q _1k is the transistor electrically farthest from the contact node N _Yk assume) is dependent on the sum of the individual segments resistor R _y1 to R _yj of the bit line BL _k. Transistor Q
_The total resistance separating the _1k drain region D from the contact node _{NY (k + 1)} also depends on the sum of the segment resistances on the bit line BL _{k + 1} . Thus, when Y address unit 20 switches node N _Yk to low potential level _VL , node N _Yk acts as a virtual ground and
When switched to _{Y (k + 1)} of the intermediate or high level (V _I or V _H), the node N _{Y (k + 1)} is given a drain potential for enabling either the reading or writing of the transistor Q _1k, The voltage at the source region S of the transistor Q _1k may be much higher than the desired virtual ground level (when a pre-specified read or write current flows through the bit line, the segment resistance of the bit line BL _k is reduced. (Due to the voltage drop occurring across) and the voltage at the drain region D of the transistor Q _1k may be much lower than the desired drain level (the current through the segment resistance of the bit line BL _{k + 1} ). Due to flow).

Of course, as will be appreciated by those skilled in the art, a plurality of points along the length of each bit line to couple the bit line to the overlying metal line and minimize the resistance effect of the diffused bit line. It is common to provide a plurality of contact nodes (vertical vias, ie, through conductors).
As an example, a bit line BL _k typically has a number of contact nodes N _{1k to} N _mk (not shown) distributed along its length, where m is an integer much larger than two. , For example, m = 20. For simplicity, in Figure 1, merely along the length of the bit lines BL _k are shown one contact node N _Yk. As will be understood, in the case of a bit line having a plurality of contact nodes, the transistor region located approximately halfway between adjacent contact nodes of the bit line is usually located at the most distant position in the electrical sense. And therefore are subject to the increased bit line resistance.

Referring to the configuration shown in FIG. 1, all transistors, especially the transistor electrically farthest from the contact node of each bit line, i.e., _Q1k, must have the effective channel of each transistor for proper operation. width is the minimum effective width W _min or more necessary for conducting a predetermined minimum read and write current I _Rmin and I _Pmin, further bit line, the BL _k and BL _{k + 1} summed in the Y-direction Care must be taken to ensure that each of the resistance values is kept below the design maximum value R _Ymax . This means that the effective channel width of each transistor is at least the minimum width W
means that it must be controlled during manufacturing to ensure that it is the same width as _min , and the width and length dimensions of the segment resistors R _y1 , R _{y2 ,.} This means that the values must be controlled during the manufacturing process to ensure that the sum does not exceed the design maximum value R _Ymax .

This is where the selection of the pitch values _PBL and _PWL is problematic. As will be appreciated by those skilled in the art, precisely controlling the effective channel width of highly integrated transistors and the width of the segment resistors _Ry1 , _Ry2 , ..., _Ryj requires a large amount of integrated circuit chips. It is very difficult when manufacturing in production. Therefore, the designer of the integrated circuit, the bit line and word line pitch, i.e. P _BL and P _WL, value constraint of whether it is how to reduce that the are imposed.

The basis for these constraints can be better understood with reference to FIGS. 2A through 2C. FIG. 2A is a schematic plan view showing a portion of the memory array 10 of FIG. 1 after a lithographic design but before actual fabrication in an integrated circuit. FIG.
A part of the figure is schematically shown in an enlarged manner. FIG. 2C schematically shows a part of the device after manufacture. The description here will be mainly with reference to FIG. 2A. 2B and 2C,
The shape in the lithographic layout of FIG. 2A is distorted during manufacturing due to etch shrinkage, dopant diffusion, oxide growth, and other processing mechanisms;
It is sufficient to note that the shape shown in FIG. 2C then occurs.

In FIG. 2A, the first to third word lines WL ₁ -WL ₃ are shown crossing over the semiconductor (N ⁺ ) bit lines BL ₁ -BL _3, and a part of the words WL ₁ -WL ₃ and the oxidation Insulation layer 30 (Fig. 3)
Partially removing the, lightly doped substrate (P ^-) channel between the regions 15b, lightly doped substrate (P ^-) channel region 15c, and the respective transistors Q ₁₁ through Q
It exposes a rectangular matrix of floating gate FG ₁₁ to FG ₃₃ belong to _33. Floating gate FG
_11- FG ₃₃ is a thin gate oxide shown in FIGS. 3, 4 and 5 and shown in cross-section taken along lines 3-3, 4-4 and 5-5. It is insulated and supported above the bit line by the object layer 30a. Thicker field oxide portions FO ₁₁ to FO ₃₃ oxide insulating layer 30 is,
It is located between floating gates 4 and 5, as shown in FIGS. 2A to 2C. FIG. 2A is not necessarily drawn to the same scale. Bit line BL
Floating gate FG ₁₂ -FG _{33 2} and BL ₃ are shown spaced apart by relatively more distant from the corresponding source portion on each bit line BL ₁ and BL _2. This large spacing has been employed in FIG. 2A to avoid confusion. As best shown in FIG. 3, the distance L _p1
And L _p2 are usually about the same size (ie, L _p1 = 1.
3 microns and L _p2 = 1.1 microns).

Referring to the cross-sectional view of FIG. 3, a thin layer 30a or gate oxide, which is preferably composed of silicon dioxide, is used to connect the control gate portion 14 and floating gate portion 16 of each transistor to the semiconductor substrate 15 Top surface of the 15
A spacing close to a (less than about 500 °) is set, thus allowing each of the control gate and floating gate portions 14 and 16 to control electrical conduction through the channel region 15c of the substrate. . Channel area 15c
Are located between the edge portions S and D of the bit lines BL ₁ -BL _{k + 1} that are pre-selected to function as either the source region or the drain region of the split gate transistor. Referring briefly to FIG. 4, the bit line end further includes portions X that are not designated to function as either a source or a drain, and these portions X
Note that is referred to as the non-source / non-drain portion. Referring again to FIG. 3, the respective read and write currents I _R and I _P are, under certain conditions, within the channel region 15c of the selected transistor when the control gate 14 of the transistor is activated. It is possible to flow through the induced inversion layer.

Referring to FIG. 4, the thick field oxide portion FO of the oxide insulating layer 30 typically has a thickness of 1000 ° or more, and more typically, 5000 ° or more.
These field oxide portion FO in order to prohibit the leakage current I _x, as shown, is to be interposed between the non-source / non drain portion X of the adjacent bit line growth formation. This use of the field oxide portion is commonly referred to as oxidative separation.

Referring to FIG. 5 and also to FIGS. 2B and 2C, the field oxide portion FO tends to extend in the x and y directions by a distance that cannot be precisely controlled. And produce a so-called "bird beak" part. As an example, this bird beak extension is
It can be on the order of about 0.6 microns in a layout that follows a design rule of roughly 1.2 microns. This can have a substantial effect on the options available to the chip designer. When this bird's beak extension occurs, the left and right end portions 16a and 16b, respectively, of the floating gate 16 may be lifted from the substrate by a significant distance, i.e., more than 200-500 °, and thus these ends Parts 16a and 16b
This prevents a substantial inversion below the substrate 15 from being induced, even if it is desired to cause an inversion. Typically, a relatively small design consideration overlap DO (eg, 0.1 micron) is desired between the floating gate FG and the field oxide portion FO. Overlap DO to be considered on this design, misalignment i.e. not during the later-described poly (polysilicon) 1 patterning steps (this step defines the floating gate FG ₁₁ -FG ₃₃₎ and other patterning steps It is for security against alignment. y
Overlap DO considering misalignment in directions in design
Below, the thickness of the field oxide portion in the zone of the overlap DO prevents the mismatch from creating a condition that creates an undesirable conductive path between adjacent bit lines, and The desired conductive path is one that is activated by the mismatched word line and is not controlled by the floating gate. While protection against the problems induced by this mismatch is a beneficial aspect of the field oxide portion, it also has detrimental aspects.

Referring to FIGS. 2B and 2C, lateral growth of field oxide in the y-direction beyond the overlap DO considered in design (a phenomenon that is difficult to control with high accuracy)
It may reduce the effective channel width W _p of the transistor after production. When the effective width W _p of the transistor is reduced below the required minimum design value W _min, which is a function of the read current I _R (which floating gate under side of the effective channel width of the transistor, i.e. I _R = f (W _p )) _May decrease below the design minimum I _Rmin and then the array 10 may not operate as designed. To address such a case, the floating gate is typically set so that its overall y-dimension has F _yd = 2DO + W _d , which is necessary to actually generate the minimum read current I _{Rmin Is} significantly larger than the minimum effective width _Wmin . That is, even if the bird's beak expands in the worst case (for example, the
0.6 microns beyond the DO each side of), so that the effective channel width W _p after production is large enough to allow the flow of a minimum read current I _Rmin, the minimum effective width
Selected to be sufficiently larger than W _min . (For example,
For a preselected W _min of 1.7 microns, W _d = 1.7 + 2
(0.6) = chosen to be 2.9 microns wide. )as a result,
The word line pitch P _WL determined by the effective width W _d +2 the overlap DO considered in the design + the separation distance FS described later (ie, P _WL = W _d + 2DO + FS) is significantly larger than would otherwise be required. Is forced to become something. As an example, in the design of a so-called non-staggered virtual ground array with a word line pitch of 4.2 microns, a minimum effective width W _min of 1.7 microns is allocated and a bird's beak growth is allocated 1.2 microns. The floating gate separation distance FS consumes 1.3 microns and the overlap DO considered in design uses 0.2 microns. From the above, the precautionary measures taken for mask mismatch and bird's beak expansion require that the belonging area A _cell = P _WL P _BL of each memory cell be otherwise required, at least as far as the word line pitch P _{WL is} concerned. It is understood that this is made larger than some.

The assigned cell area A _cell = P _WL P _BL is the word line pitch P
If it is not possible to reduce by reducing _WL (eg, due to the precautionary measures described above), then the cell area can be reduced by selecting a smaller bit line pitch _PBL . Seems to be.
However, even in this case, it is still relevant to processes involving overgrowth of field oxide, excessive bit line resistance, mask mismatch, and electrical characteristics of the manufactured transistors that need to be considered. There is an interaction between the factors that do. With respect to these factors, it is useful to briefly consider how integrated circuits are manufactured in mass production form.

In one method of fabricating the memory array 10, a thick field oxide portion FO is formed on a flat surface of a single crystal silicon substrate using a first lithographic pattern or "mask".
Grow. After growing the field oxide, a first polysilicon layer (poly 1 layer) is formed on the substrate.
This poly 1 layer is patterned (eg, etched with a plasma) using a second lithographic mask to define a plurality of linearly arranged rows and floating gates FG ₁₁ -FG _jk comprising rows. . This floating gate pattern has the base x and y dimensions drawn by lithography, ie, F _xd and F _yd (FIG. 2B), but after etching, the shape of the floating gate is shown in FIG. 2C. As shown, smaller dimensions F _xp after fabrication
And tend to shrink to F _yp . Etch shrinkage is accentuated at the corners or corners of the depicted floating gate shape as compared to the flat side portions of the depicted floating gate shape and these corners or corners are rounded as they shrink. Note that there is a tendency. The present invention makes effective use of this phenomenon. This rounding at the corner occurs regardless of whether the floating gate pattern is defined by photolithographic masking or plasma etching or other patterning techniques.

After patterning of the floating gate, a photoresist layer is deposited and patterned by a third lithographic mask, through which windows for ion implantation are defined (see FIG. 7A). The photoresist pattern preferably includes a first window end (50a-1) with an injection window (eg, 50a in FIG. 7A) aligned midway between the ends of the floating gate in a single row. It is relatively aligned with the floating gate so as to have an opposing second window end (50a-2) spaced from the end of the floating gate in the single row.

Next, the bit lines BL ₁ -BL _{k + 1} are connected to the bit line defining ends (for example, E1 to E4 of FIG. 7A) of the floating gates (for example, FG _{1 to} FG ₄ ) and the photoresist (50). Using the part as a mask as a unit, ion implantation is performed in a self-aligned manner. After implanting the bit line dopants, the photoresist (50) is removed, an insulating layer is formed on the surface of the floating gate, and the implanted bit line dopants are diffused laterally, as shown in FIG. The shape of the bit line is enlarged below the end of the floating gate by a distance L _D determined by

In a later step, to form the word lines WL ₁ -WL _j by patterning and depositing a conductive material layer on the insulating layer covering the floating gate of this deposited layer was in the fourth mask. These word lines are preferably composed of highly doped polysilicon (poly 2 layer) as well as the floating gate (poly 1 layer).

Referring to FIGS. 2A to 2C, bit lines BL ₁ -BL _{k + 1
Are} the dimensions B _xd , B _xdo , B x in the x direction, as depicted in FIG.
_Although having _xdf , these bit lines are distorted in shape due to manufacturing factors such as etch shrinkage and lateral dopant diffusion, and as shown in FIG. _Has different dimensions B _xp , B _xpo , B _xpf . 2B and 2C, the field oxide portion FO expands from the depicted dimensions O _xd , O _yd in the x, y directions to larger dimensions O _xp , O _yp after fabrication due to lateral expansion. It should be noted that As a result, the field oxide FO has a width dimension B _xpo
And it affects both the effective channel width W _p after production of the transistor. Obviously, some features shown in FIG. 2A (ie, word lines, floating gates and oxide portions) have been omitted in FIGS. 2B and 2C. Thus, in these figures, changes in bit line, oxide and floating gate shapes can be better understood.

When the bit line pitch _PBL is selected, it must include at least the following two predetermined overlap lengths that determine the electrical characteristics of the transistor. That is, the two overlap lengths are predetermined channel lengths under the control of the floating gate.
L _p1 and L _p2 which is a predetermined channel length under the control of the control gate (word line). After these two overlap lengths, the selected bit line pitch P _BL is
It includes the dimension B _xdf affected by the floating gate of the bit line plus the expected side diffusion L _D of the bit line.
In a conventional non-staggered virtual ground configuration with a 4.2 micron bit line pitch, a 1.8 micron pitch is consumed by the delineation dimension B _xd and 1.3 microns is L _p1
It is consumed by, and 1.1 microns has been consumed by the L _p2. The values of L _p1 and L _p2 are fixed according to certain electrical characteristics desired for the split gate transistor. As will be understood from the detailed description below, B
The value of _xd is somewhat constrained by concerns about generating excessive bit line resistance. It also:
Partially restrained by concerns over excessive growth of the field oxide portion FO. Furthermore, the design standards for the metal wires ML impose some restrictions.

Exemplarily given pitch values above, i.e. P _BL = 4.2 microns and P _WL = 4.2 cells were assigned obtained for micron zone A _cell = P _BL P _WL was about 17.5 square microns. The above description seems to indicate that there is no way to further reduce cell area without sacrificing electrical performance and / or manufacturing yield. However, it will be apparent from the following description that the cell area can be further reduced without sacrificing electrical performance and manufacturing yield.

Objective The present invention has been made in view of the above points, and has been made in consideration of the above-mentioned drawbacks of the related art, and has been made in view of one of the problems of improving the degree of integration and / or improving the production yield and / or mass-producing. To provide a split gate memory array having features such as maintaining consistency in performance from one batch to the next (eg, the magnitude of the read current is uniform from one manufacturing batch to the next). With the goal.

According to the present invention, in an array having a plurality of rows of split gate transistors, the floating gates of the first row are shifted or "staggered" from the alignment state in the column direction with the floating gates of the adjacent second row. That is, the minimum distance between the first row of floating gates and the second row of floating gates is not the flat-to-flat correspondence between the flat portions of the respective floating gates. , Between the corners (i.e., corners) of the respective floating gates in the first and second rows. The third row floating gates adjacent to the first row preferably remain column aligned with the second row floating gates, so that the minimum distance between the first and third row floating gates is also Measured from the corner to the corner.

The first row of the staggered type is shifted along the arc-shaped path to bring the first row closer to the second row, and the floating gate of the first row is suppressed to contact the virtual design reference circle, and The minimum distance between the first floating gate row and the second floating gate row aligned in the column direction is such that such a distance is substantially greater than the pitch of the row (preferably 30 °). Above) can be arranged. If the source-to-drain orientation of the transistors in the first row is reversed relative to the source-to-drain orientation of the transistors in the second and third rows, the angle can be increased. Using this technique of increasing the angle by reversing the source-to-drain orientation, the inter-row pitch of the array is substantially less than the corner-to-corner distance measurement between the floating gates in the first and second rows. Can be made even smaller.

In one embodiment of the present invention, a plurality of spaced bit lines are integrally formed, and each bit line is longitudinally formed in a semiconductor substrate such that each bit line has a left side portion and a right side portion opposed in a lateral direction. Direction. The rows on the straight line of the floating gate are distributed across the substrate in spaced correspondence and passed above each bit line. Each floating gate has a bit line defining end portion that is used during manufacturing to define a corresponding end portion of the underlying bit line. After fabrication, each floating gate is positioned such that its bit line defining end portion overlaps either its left or right side of its corresponding bit line by an overlap distance determined by diffusion. Is done. Each floating gate further has an effective length determining end facing the bit line defining end. The effective length determining end of each floating gate is defined simultaneously with the bit line defining end, so that the distance between these two ends can be precisely set. The rows of floating gates are staggered with respect to each other, so that the bit line defining ends of the floating gates in the first row have bit lines for defining the left side of their respective bit lines. The bit line defining ends of the floating gates of the second row are used as part of the same bit line implant mask to define the right side of their respective bit lines. You.

When a split-gate transistor is formed, the floating gate of the transistor is disposed near the drain region of the transistor and separated from the source region, so that the transistor has a functionally asymmetric geometry. Thus, in one embodiment described above, the source-to-drain orientation in the first row of transistors is opposite to the source-to-drain orientation of the transistors in the second row of transistors. The opposing source-to-drain orientations of the rows are alternately arranged from one row to the next, so that the odd-numbered rows and the even-numbered rows each have opposing orientation relationships. This allows each bit line to sequentially and alternately act as a source and drain portion of a longitudinally adjacent transistor along each of its left and right ends, respectively. Have.

As a result of this row's opposing orientation, the minimum distance between floating gates in adjacent rows is measured from corner to corner rather than from flat to flat. As a result, the pitch between the transistor rows can be reduced as compared with the pitch between the transistor rows in the non-staggered layout. Cell area is reduced by reducing the pitch between rows, and the density of memory cells can be increased as a result. When the pitch between the transistor rows is reduced, the length of each bit line can be reduced, and the bit line resistance is reduced because the bit line resistance is proportional to the length. Furthermore, since the capacitance is proportional to the area, the capacitance between the bit line and the substrate can be reduced by reducing its length and consequently the area of the bit line to the substrate interface. Electrical performance benefits are obtained from both reduced bit line resistance and reduced capacitance between the bit line and the substrate.

An additional advantage of the staggered layout when floating gates are located on opposite sides of each bit line is the integrated device with more uniform electrical characteristics (eg, relatively consistent bit line resistance). Can be easily manufactured in a mass production system.
If there is a mismatch between the first mask used to define the floating gate pattern and the second mask (photoresist mask) used with the floating gate pattern to define the bit line geometry,
While such a mismatch may increase the resistance of the first bit line segment in the region of the first row by a significant amount, the same mismatch may cause an increase in the resistance of the second bit region in the second row region which is oriented oppositely. The resistance of the bit line segment is reduced by a corresponding amount. This simultaneous increase and decrease in segment resistance cancels each other, so that the total resistance of each bit line is substantially reduced by a slight mismatch between the first mask (floating gate) and the second mask (photoresist). No longer affected. As a result of being unaffected by this mismatch (further,
The electrical characteristics of integrated circuits manufactured in different manufacturing batches can be made more uniform, as a result of the reduced bit line lengths that occur when the word line pitch is reduced. And / or the production yield can be further improved.

Since the bit line resistance is unaffected by the mismatch, it is possible to reduce the depicted bit line width to smaller dimensions than previously possible. As the bit line width is reduced, the size of the PN junction formed at the bit line and substrate interface is reduced, and the bit line to substrate capacitance is reduced, thereby reducing the bit line discharge time requirements and the cell. It is possible to make the read time shorter or reduce the minimum level of read current required for a pre-specified cell read time. If the minimum read current level is reduced, the minimum effective channel width required to conduct such current is reduced (all other factors being unchanged). As a result, the word line pitch can be reduced, and at this time, the degree of integration can be further improved.

According to another aspect of the invention, the word line is depicted or set to be narrower than the floating gate at least at the portion of the word line where the word line crosses the floating gate. When the word line is made narrower in this manner, one word line is provided for the opposing non-drain / non-source portion of the adjacent bit line due to the mismatch between the word line mask and the floating gate mask. There is less risk of overlapping near the area of the substrate surface that fully links the non-drain / non-source portions of the bit lines of the same. The non-drain / non-source portion is a portion of a bit line that is not intended to function as a drain or a source of a memory cell transistor.
As a result, the likelihood of accidental inversion of the word line in the area to be linked in the event of a mismatch is reduced, the configuration is not affected by the mismatch, and the manufacturing yield is increased. It is possible.

According to yet another aspect of the invention, the thick oxide insulating layer (field oxide) that spans the floating gate of the previous design has been completely removed. Such removal is contrary to currently accepted practice. This is because it can create excessive leakage current paths between the non-source and non-drain portions of adjacent bit lines. However, the above-described configuration for obtaining more uniform bit line resistance allows a designer to reduce the bit line width. This allows the designer to increase the spacing between facing ends of adjacent bit lines (without having to increase the bit line pitch), while at the same time facing the bit line ends. The risk of generating excessive leakage current (punch-through current) between the non-drain / non-source portions of the semiconductor device.

Removing the field oxide can further increase the density of the memory array. Since the consideration for the dimensional inaccuracy caused by the bird's beak growth phenomenon has been removed, the floating gate width can be made smaller than previously possible. There is no longer any concern that excessive bird beak growth will reduce the effective channel width of the transistor to a value below the required minimum effective channel width. Thus, the floating gate does not need to be drawn or set to the width previously required to compensate for the bird's beak problem, thus reducing word line pitch and increasing the density of memory cells in the array. Is possible.

Further, the removal of field oxide in the area of the substrate forming the memory cell eliminates concerns about mismatch between the field oxide defining mask and the bit line defining mask. Such a mismatch has the potential to increase the bit line resistance beyond the set maximum. By removing the field oxide, the mismatch problem is also eliminated. Furthermore, it allows the substrate to have a substantially flatter surface topography.
Various lithographic constraints on non-planar lithography are eliminated, allowing the use of isoprene, a smaller design rule associated with co-planar lithography. As a result, the floating gate width can be described or set to a smaller value, and the memory cell can be miniaturized to be closer and have higher integration.

According to yet another aspect of the invention, the word lines are each configured to have alternating wide and narrow portions.
The likelihood of breakage in word lines, which may occur somewhere along the length due to the so-called "photoresist necking" phenomenon, is reduced, so that smaller design criteria can be used for word line widths It is. The wide portion of the first word line can be tiled with the narrow portion of an adjacent word line, thus minimizing the spacing between adjacent word lines, thus The effect of the "necking" phenomenon on the word line pitch is reduced.

EXAMPLES Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The following is a detailed description that is presently considered to be the best response for practicing the present invention. This explanation
It should be noted that what is to be regarded as illustrative, but not in a limiting sense. In particular, the exemplary design criterion values provided herein are not intended to limit the scope of the invention, which may use smaller design criterion values or other values. is there.

Referring to FIG. 6A, a non-staggered configuration (FIG. 2A)
That is, a floating gate having a non-shifted configuration is shown, in which case all the gates are arranged in straight columns C1, C2,
It is arranged in rows C1, and rows R1, R2, R3 on the straight line. Assuming that the floating gates FG ₂₁ , FG ₂₂ , FG _{23 in} row R2 have been shifted to the left according to the path indicated by A in FIG. Located outside, the advantages of the present invention are obtained. The minimum distance between the floating gates of rows R1 and R2 is no longer relative to the flat part (eg, FG ₁₃
Rather than measuring between the flat bottom side of the FG _{23 and} the flat top side of the FG ₂₃ , instead of measuring from corner to corner (eg, between the left bottom corner of the FG ₁₃ and the right top corner of the FG ₂₃ ) ) Measured. The design standard for the corner-to-corner spacing FS * is the spacing from flat to flat
It can be set smaller than the design criteria for FS (eg, it can be set to 0.95 microns instead of 1.10 microns). This is because, as described above, a phenomenon occurs in which a corner is rounded (FIG. 2C). Thus, the stagger, ie the pitch between the shifted second rows, measured in the y-direction.
P _WL * (R2 * here to distinguish it from that of FIG. 2A)
And FG * ₂₁ , FG * ₂₂ , FG * ₂₃ ) can be smaller than the previous pitch _PWL . However, this is only part of the advantage gained by shifting the second row R2 * out of column alignment with the first row R1.

The floating gates in row R2 * extend beyond point A1 to a second point A2, a virtual minimum design reference circle whose upper right corner (corner) has radius FS * (for simplicity, such a circle
Only one of the DRCs is shown and is shown around the lower left corner of FG ₁₃ ), and when moved in abutment, the corner-to-corner spacing vector FS * becomes The word line pitch _PWL is substantially angled relative to the y direction. This corner-to-corner spacing is preserved as long as the angle θ at which the vector FS * is rotated out of alignment with the vector FS from flat to flat remains in the range between 0 ° and 90 °. You. Preferably, the vector FS * is rotated by an angle θ over an angle substantially greater than 0 ° and substantially less than 90 °, for example between 15 ° and 75 °. The new pitch P _WL * is further reduced, so the reduction in word line pitch can be expressed as:

ΔP _WL = P _WL −P _WL * = FS−FS * + FS * (1−cos θ) The above equation appears that the minimum value of the word line pitch occurs at θ = 90 °. However, there are various restrictions that must be taken into account. First, θ is up to 90
Assuming that it is possible to increase arbitrarily to ゜, when the angle θ approaches 90 °, the interval between the floating gates changes from the corner-to-corner correspondence FS * to the flat-to-flat correspondence again. It is clear that the conversion to FS would eliminate the advantages of smaller corner-to-corner design criteria. More importantly, floating gates FG * ₂₁ , FG * ₂₂ , FG * ₂₃
There is a minimum spacing condition _Lp2min between the left side of the bit line and their left bit lines. (The bit lines are not shown in FIG. 6A for simplicity, and the field oxide is not shown.) The control gate in each transistor is close to the substrate surface when a poly 2 layer is deposited. The minimum spacing L _p2min required to form portion 14 and to ensure that control gate portion 14 has a minimum effective length is violated in practical designs before reaching the point θ = 90 ° I do. Such a violation is due to the _fact that using the right-to-left (drain to source) L _p2min
* It tends to occur at a relatively fast stage in vector rotation.

FIG. 6B shows how the restriction imposed on the rotation angle θ of row R2 * by the minimum spacing condition _Lp2min can be overcome. The drain-to-source orientation of row R2 * has been inverted by 180 ° and therefore the new L *
_p2min is measured from the right side of the gate in row R2 *, not the left side. The inverted L * _p2min dimension is not constrained to the left side of the floating gate by the bit line, and this allows for a larger rotation angle θ *. Typically, considering the effect of each angle θ * on the minimum bit line pitch _PBL that can be obtained as θ * increases, angles θ in the range of 25 ° to 45 °
* Is preferable, and a range around 30 ° to 35 ° is more preferable. P _BL can be defined to include the component of L _p1 + FS * sin θ *. FS * sinθ *
Increases as the angle θ * increases within the range of 0 ° to 90 °.

The use of inverted source / drain orientations in alternating rows has a significant effect. Bit line mismatch sensitivity is reduced. Referring to FIGS. 7A through 7D, it can be readily understood that the previous non-staggered layout of the floating gate formed a mismatch sensitivity, and with reference to FIGS. 8A through 8C, the staggered structure of the present invention. It is easy to see how the floating gate layout does not affect the mismatch.

7A, the photoresist mask 50 having the injection window 50a formed thereon is
From the mask 50 and the pattern 60
It is possible to visually understand the effect of the mismatch between The field oxide portion FO is not shown, thus simplifying the description. It can be considered that the floating gate pattern 60 can be shifted in the x direction relative to the photoresist mask 50. Of course, it will be readily understood from the foregoing description that the floating gate pattern 60 is directly deposited on the substrate 70 and the photoresist mask 50 is directly deposited on the floating gate pattern 60. The ends E1-E4 of the floating gates FG1-FG4 protrude into the area of the photoresist window 50a, so that they define the drain regions of the split-gate transistors to be formed later and connect these drain regions with the floating gates. It can be used to match. When the bit line forming dopant is projected through the photoresist window 50a and is injected into the substrate through the floating gate pattern 60, a comb-shaped injection image 71 is formed on the substrate 70. The shape of the bit line injection image 71 is, of course, self-aligned with the floating gate ends E1-E4, but more importantly, here, the width of the bit line injection image 71 is the narrowest part. At the end, it depends on how far the ends E1-E4 protrude into the area of the injection window 50a, and this controls the resistance of the bit line.

As shown in the plan views of FIGS. 7B and 7C, a single bit line region has a floating gate FG1-FG4
Can be considered to be formed by a plurality of vertical resistance segments R _1a , R _2a , R _3a , R _4a which respectively belong to the bit lines defining the ends E1 to E4 of It is. The resistance of any one segment is inversely proportional to the width of the bit line region at that point. Therefore, the bit line defining ends E1-E4 are further added to the photoresist window 50.
When the bit line image 71 is pinched by shifting the floating gate pattern 60 so as to project into the area of FIG. 7 (which occurs when the configuration of FIG. 7B is replaced with the configuration of FIG. 7C), the corresponding segment resistance Each increase in resistance. As will be appreciated, the resistance of a bit line segment increases rapidly to infinity as the width of the bit line segment approaches zero. So, for example,
Even with small shifts in the floating gate pattern on the order of 0.3 microns, the segment resistors R _1b , R _2b , R _3b , and R _4b in FIG. 7C should have significantly greater resistance than the resistors in FIG. 7B. it is, that it is, in particular, the resistance segment R _1a to R _4a is to say if it has a nominal width on the order of 0.5 microns or less (when there is no mismatch).

The total bit line resistance R _S = (R _1b + R _2b + R _3b + R _4b ) resulting from the bit line image shown in FIG. 7C is the cumulative value of the increase in resistance in each of the segments. Thus, the pinch effect of the bit line is arranged along the bit line when viewed from the point of view of the transistor (in the electrical sense, furthest from Q _{1k in} FIG. 1). Considering the general case of N floating gate (N transistors) bit lines disposed longitudinally between contact nodes, the added resistance change is typically reduced by the number of intermediate transistors. 7B, and is therefore proportional to the number of photoresist masks 50 and floating gate patterns 60 in FIG. 7B.
When the size of the bit line image 71 is reduced in the transition to the one shown in FIG. 7C, the increase in the resistance value increases as the number N increases. This increase in resistance is not only a function of the number N, it is also defined as a function of misalignment MM _x between the mask and the mask which may occur between the floating gate patterns 60 and the photoresist mask 50 Is possible.

The relationship between the mask misalignment MM _x and all the bit line resistance R _S is plotted on the 7D FIG. If the mask mismatch is zero, the added bit line resistance R _S is equal to the nominal design value R _nom . The added resistance R _S drops toward zero when the mismatch increases in the first direction (−MM _x ), but its resistance R _S increases, so it is a predetermined design value limit R S
It may be displaced toward infinity when passing beyond _Ymax and mask misalignment MM _x increases in a direction opposite the second direction (+ MM _x). This latter increase in mismatched MM _{x is} a headache for device designers, who have set up bit lines with wider widths than would otherwise be necessary. I have.

Referring to the staggered floating gate arrangement of FIGS. 8A and 8B, the total bit line resistance is shown in FIGS.
It can be easily understood that the influence of the mask mismatch is substantially reduced as compared with the non-staggered layout shown in FIG. 7C. Pinch drop of the first bit line segment is done by photoresist mask
If 50 * and floating gate pattern 60 * are shifted relative to each other, they are offset by expansion of the second bit line segment. In the plot of FIG. 8C, a first orientation set N ₁ of a total of N floating gates
Increase (when moving in the + MM _x direction) is caused by the second set of orientations of N floating gates on the same bit line.
Offset by the resistance decrease of N _2, therefore the overall bit line resistance does not change drastically different from those in the 7D FIG. In the 7D diagram, the N segments when inconsistency occurs in + MM _x-direction have increased simultaneously resistance. In the first 8C view, the same total number of segments, namely a N = N ₁ + N _2, only N ₁ segments have increased resistance (N ₁ <N), further, N ₂ segments are , The resistance is reduced (when mismatch occurs in the + MM _x direction). Thus, one advantage of such a staggered or staggered layout is that before the total bit line resistance reaches and exceeds the design limit _RYmax , the absolute value of the larger mask mismatch can be reduced. Value | MM _x |
> 0 can be tolerated.
(Of course, this comparison assumes that the depicted dimensions of the bit lines in FIG. 8A are the same as the corresponding dimensions in FIG. 7A.) On the other hand, for a fixed value of the worst case mismatch For example, smaller feature sizes can be tolerated. Of course, it is also possible to use the staggered floating gate pattern of FIG. 8A to derive various combinations of increased mismatch intersections and reduced cell dimensions.

Furthermore, it is possible to increase the number N = N ₁ + N ₂ of transistors associated with each contact node. In previous configurations (e.g., non-staggered virtual ground configuration), it has been found that it is necessary to provide less than 32 floating gates between successive contact nodes of a bit line having multiple contact nodes did. Since each contact node consumes a finite substrate area, the density of the previous memory array configuration (non-staggered virtual ground) as a whole increases as the memory capacity increases and more contact nodes are provided. Tend to be restricted. With the present invention, it is possible to integrate at most 48 transistors between the contact nodes of a single bit line without encountering the problem of generating excessive bit line resistance due to mismatch. So that it is possible to reduce the number of contact nodes required to realize a large capacity memory, and to use more substrate area for other functions Turned out to be possible. As an example, by using the staggered or staggered layout of the present invention, 88000 contacts were required to form a 4-megabit memory array (ie, 4,194,3).
04/48 = 87,381). This is the case for a line width of 1.2 microns.

Using the concept of the present invention, it has been found that it is possible to reduce the cell size by about 40% using a design rule of 1.2 microns (the area per cell of the non-staggered virtual ground configuration is reduced). What used to be 17.5 square microns is now less than about 10 square microns according to the present invention). In one embodiment of the present invention, the pitch P _BL (the repetition distance from one bit line to the next bit line) is 3.4 microns for bit lines and 2.8 microns pitch P for word lines. _WL , resulting in an average cell area of at least 9.5 square microns (again, using a 1.2 micron design rule).

Even if the cell size is not reduced, a staggered or staggered floating gate arrangement in which a floating gate is used to simultaneously define each side of each bit line is advantageous. because,
This arrangement makes the overall bit line resistance more uniform (+ or -MM _x ) with respect to manufacturing process variations, and thus provides a more consistent electrical connection between one manufacturing batch and another. It is possible to easily mass-produce a device having characteristics.

As it is clear from reference to FIG. 6C, the design criteria around the row R1 * and R3 * corners of four as shown corner i.e. corners top and bottom of the floating gate FG _M in the middle row R2 * it is possible to minimize the pitch between the floating gates in the direction of both the x and y directions by abutting against the yen DRC ₁ to DRC _4. Of course, the degree of integration in the x-direction will be affected by the available patterning techniques for the upper portion of the array. At present, highly integrated EP
The biggest concern among ROM chip manufacturers is the metal wire M
The design criteria related to L ₁ −ML _{k + 1} is that the bit line pitch P _BL is
For example, the first few layers implanted into the substrate or above the substrate (eg, poly 1 floating gate layer)
The goal is to prevent other features of the memory array, such as features patterned therein, from being reduced to levels comparable to smaller design criteria that can be used to reduce the size.

The limitations imposed by metal (metal) wire design standards are:
This can be understood by referring to FIG. 2A. The contact nodes N _Y1 -N _Y3 must have a minimum width C _min (which may be, for example, 1.2 microns). Metal lines are typically patterned to have a larger minimum width M _x (eg, 1.8 microns). Width M
_The metal line pattern forming step for forming the metal line _x is usually performed with the minimum inter-metal spacing dimension MS
(Eg, 1.4 microns).
To prevent mismatch problems, the minimum dimension CO (eg, each
Contact overlap portion having a 0.2 micron) typically metal lines are formed on the side of the minimum metal width M _x in the region for the contact node overlap. For the configuration shown in FIG. 2A, these design dimensions force the use of a minimum bit line pitch defined by P _BL ≧ CO + M _x + MS. (Using the 0.2 micron, 1.8 micron, and 1.4 micron values of this example for CO, _Mx and MS, the minimum bit line pitch _PBL is 3.4 micron.) The floating gate in FIG. Cannot be integrated very close in the direction,
Therefore, the minimum pitch condition of the metal design standard is violated.
Also, the values of the transistor overlap lengths L _p1 , L _p2 and L _D must be considered as limitations on how closely the floating gate can be integrated.

One less obvious consequence of the staggered configuration is that it is possible to limit the leakage current between adjacent bit lines to an acceptable level, and thus eliminate the field oxide portion. Is possible. If the bit line width is reduced but the bit line repetition distance (pitch) is unchanged, the spacing between the facing ends of adjacent bit lines increases. As an example, the spacing between facing bit line ends can be increased by the same 0.4 microns if the reduction in bit line width is 0.4 microns. Leakage current I _x through the lightly doped inter-channel region between the spaced bit line ends increases with increasing spacing between the bit line ends.
Decrease. Thus, as the bit line width is reduced, the need for oxide isolation between bit lines is reduced, and the thicker field oxide portion FO can be removed if desired.

As the bit line width is reduced (with or independently of the reduction in bit line length), the size of the PN junction formed at the interface between the substrate (P-type) and the bit line dopant (N-type) decreases. And the capacitance of the bit line relative to the substrate is reduced.
This reduces the charge / discharge time of the PN junction, thus speeding up the cell read time or reducing the minimum read current requirement. The minimum read current is proportional to the bit line capacitance.

I _Rmin = ΔV _sense C _bitline / Δt _{sense In the} above equation, ΔV _sense is a predetermined voltage swing, C _bitline is the capacity of the bit line with respect to the substrate,
Δt _sense is a predetermined time window for detecting a voltage swing. If I _Rmin can be reduced by a decrease in C _bitline , then the minimum effective channel width W _min can be reduced. This is because when I _Rmin decreases, W _min decreases. Such a decrease in the minimum channel width W _min allows for a smaller overall representation or set floating gate width F _yd *, and the word line pitch P _WL * = F _yd ++.
FS * can be further reduced.

FIG. 9A is a schematic plan view of a memory array 100 according to the present invention. Asterisks (stars) are used to distinguish those parts of FIG. 2A that use similar reference numbers. It should be noted that the floating gate FG ₁₁ * partially overlaps the left side of the bit line BL ₂ *, while the floating gate FG ₁₁ *
₂₂ * is in the right side and partially overlapping the bit lines BL ₂ *. Furthermore it should be noted that (although not with reference to Figure 9A, apparently belonging to the gate FG ₂₁ *) drain part D ₂₁ * of the transistor Q ₂₁ *, the bit line
Along the left side of BL ₂ is not aligned longitudinally with the drain D ₁₁ * (of the gate FG ₁₁ *), but the bit line BL
₁ * it is diagonally disposed to the right of, and thus the floating gate FG ₂₁ * and FG ₁₁ * minimum separation distance FS between
* Is measured from corner to corner and at a predetermined angle to the y-axis. There is no thick oxide portion FO in the array 100. Word lines WL ₁ * and WL ₂ *
_Are dimensioned to be substantially narrower than the y-dimension F _yp * after fabrication of the floating gate (W _yp
* <F _yp *). The actual width difference F _yp * −W _yp * is exaggerated in FIG. 9A. Typically, this difference is less than about 33% of the floating gate width F _yp * (eg, F _yp * = 1.9 microns and W _yp * = 1.4 microns). The removal of the field oxide part FO
This is better illustrated by the schematic cross-sectional view of FIG. 9C taken along line 9C-9C of FIG. 9A. All bottom surface portions of the floating gate FG * should be less than 500 mm from the substrate surface, preferably 2
It is evenly spaced a distance of less than 50-300 °. The effective channel width W _p of the floating gate is basically equal to the dimension F _yp * after fabrication. The word line pitch can be reduced and the cell size can be as small as 9.5 square microns using a design rule of at most 1.2 microns. And a technique for removing the field oxide and making the word line narrower than the floating gate.

According to current calculations, the present invention provides a better cell area than the conventional cell area A _cell without removing the field oxide portion, without changing any of the lithography criteria, and without changing the mismatch constraints. New cell area A _cell * 15
% To 20% can be made smaller. Removing the field oxide eliminates the bird's beak problem and can further reduce cell size. Even when the design standard is constrained to a line width of 1 micron or more (for example, 1.2 microns), the bit line pitch is set to 3.5 microns or less and the word line pitch is set to 3.0 microns.
It can be submicron.

Instead of inhibiting the cross current _Ix from occurring with the oxidation isolation technique, the word line width W _yd * before fabrication (not shown) is preferably at least in the region of the word line where the word line passes above the floating gate. , The floating gate width F _yd * is drawn or set substantially narrower than the floating gate width F _yd *. Slight misalignment (in the y-direction) of the word line definition mask relative to the floating gate patterning mask
Is the word line width W _yp * after the floating gate is manufactured.
Compensated by the fact that it has a post-aligned width F _yp * that is substantially wider than (eg, about 0.3 microns wide on each side). Electrons passing through the effective channel width of the control gate (word line) are reliably introduced into the channel region under the control of the floating gate, even if a mismatch occurs.

Referring to the embodiment 200 shown in the schematic plan view of FIG. 9B, it is understood that the word lines WL need not be uniformly narrow along their entire length. The word lines WL can be substantially narrower in the region WLn where they pass above the floating gate FG.
The difference in width between the narrow region WLn and the wide region WLw is 9B
The drawing is exaggerated. Usually, a small difference in this width is sufficient, for example in the region WLn
If the widths of WL and WLw are 1.4 microns and 1.9 microns, respectively, about 0.5 microns is sufficient. As shown in FIG. 9A, when the word line has a certain narrow width,
The reduced effective channel width below the control gate portions of the transistors in FIG. 9A does not significantly reduce the magnitude of the read current I _R through those transistors. The potential on the floating gate is usually the factor that overcomes it. As will be appreciated, providing alternating wide and narrow portions along the word line can be used to eliminate the "necking" problem described below.

Referring to FIG. 9C, there is a problem of bird's beak formation where the end portions 16a *, 16b * of the floating gates FG * ₁₂ , FG * ₂₂ are lifted from the substrate surface 15a * when the field oxide portion is removed. The effective width Weff * of the floating gate (i.e., each floating gate having a point sufficiently close to the substrate surface, eg, on the order of less than 500 °, to substantially control inversion in the underlying substrate. Portion) is essentially equal to the depiction of the floating gate, ie the shrinkage due to the set width F _yd * _-etching .

Removing the field oxide eliminates the problem of mismatch between the field oxide patterning step and the bit line patterning step. Previously, the bit line dimension B _xpo was affected by oxide growth and mask mismatch. Once the field oxide is removed, the total bit line resistance is no longer a function of the mismatch between the oxide pattern and the floating gate pattern, thus making it possible to mass produce devices with more uniform characteristics. Become.

Removing the field oxide portion allows the substrate surface 15a * to have a substantially flatter topography. If the field oxide is used in a conventional configuration, it may create a surface recess of 2500 mm or more below the main surface of the substrate surface (i.e., for a 5000 mm thick field oxide), This complicates subsequent lithography steps. When the field oxide is removed, the substrate surface 15a * becomes substantially flatter and the design criteria can be relaxed. Regarding the ideal flat shape of the floating gate shown in FIG. 9C, when the oxide insulating layer for separating the word line from the floating gate is thermally grown, the ends 16a *, 16b
* May slightly rise from the substrate (for example, 100
<Å), which typically does not substantially reduce the effective width of the floating gate.

FIG. 10 is a schematic diagram having a reference numeral similar to that of FIG. 1 illustrating a memory array 100 'according to the present invention. It should be noted that the drain-to-source orientations of adjacent rows are oppositely arranged. This means that the X address unit 118 may have to share at least one address line _Xo with the Y address unit 120, and thus the Y address unit 12
0 means that it is possible to determine which of the nodes N _{Y1 to} N _{Y (k + 1)} will drive the drain of the transistor in the selected row and which will drive the source of that transistor. ing. In the circuit 100 'shown, the Y address unit 120 sets its node voltage differently depending on whether the odd or even row is selected.

FIG. 11 is a schematic plan view of an embodiment 300 according to the present invention. The embodiment 300 has a plurality of word lines WL * ₁ , WL * ₂ , each of which has a wide portion and a narrow portion that occur alternately. Wide part 30 of the first word line WL * ₁
8 are arranged in such a manner as to mesh with the narrow portion 306 of the adjacent second word line WL * _{2 in} a tile shape (or like a puzzle part), so that the word line pitch P * _WL is minimized. It is possible to do. Since the minimum feature interval WS * of the word line pattern forming step is measured at a predetermined angle relative to the word line pitch P * _WL and from corner to corner (corner to corner), the word line pitch P *
_WL should be much smaller than would be possible if the minimum feature spacing WS * was measured along a line parallel to the word line pitch measurement line and from flat to flat. It is possible.

This aspect of the invention can be better understood with reference to FIG. 9B. Example 20 of FIG. 9B
At 0, the distance FS * from corner to corner of the staggered floating gate is measured not only at a predetermined angle relative to the pitch (y-axis) of the floating gate adjacent in the longitudinal direction, but also in the longitudinal direction. It is understood that the spacing WS * from corner to corner of a word line adjacent in the direction is also measured at a predetermined angle with respect to the word line pitch P _WL *. Four design reference circles 201-204
Are the preselected minimum spacing references FS belonging to the floating gate and word line pattern forming steps, respectively.
* And WS * trajectories are shown centered around each of the left and right bottom corners of the floating gate and wide word line portions. The corners of these parts are marked with their corresponding design reference circles 20
The word line pitch P _WL * can be minimized by changing the dimensions of the floating gate and the wide word line region WLw while keeping the periphery of the floating gate 1-24 in contact.

As shown in FIGS. 9B and 11, the use of an alternate wide and narrow word line configuration provides manufacturing advantages. It is possible to reduce the effects of the so-called "photoresist necking" problem. When a word line is manufactured in mass production form, there is a probability that some portion along its length will be over pinched or completely disconnected. This probability is directly related to the length of the word line portions, and in the opposite sense to their width. By providing alternating wide portions between the narrow portions of the word lines, the overall length of the narrow portions is reduced, thus reducing the likelihood of "necking". This gives the designer the option to improve manufacturing yield and / or reduce the width of the narrow word line portions.

The In Figure 11, the metal bit line MBL ₁ is the bit lines BL ₁
Is shown above. The connection node (ie, through conductor) N _Y1n of the metal line to the bit line formed by diffusion
Are also shown. For each predetermined number of transistors along each bit line, e.g., 48 transistors, the row RC otherwise having memory cells is a contact node, i.e.
N _Y1n has been inserted to give. As more contact node rows RC are used, less substrate area is available to implement the memory cells, thus affecting the overall memory density of memory chips with finite surface area . If the bit line resistance is kept small according to the method described herein, it is possible to place more transistors between the contact rows, a smaller number of contact rows RC is required, and the overall chip It is possible to increase the degree of memory integration.

The bit lines BL ₁ to BL ₄ in FIG. 11 has a zigzag shape, therefore, the moving distance with respect to the leakage current I _x are the maximum, whereas the distance to the read current I _R is as small as possible Have been. Each of the word lines WL * ₁ and WL * ₂ has alternating wide and narrow portions 308 and 306, which are arranged in a tiled (or puzzle piece) fashion along the contact rows. The narrow portions opposing the wide portions are fitted together, so that the word line pitch P _WL
Can be minimized. The contact row RC is provided repeatedly for every twelve transistor rows, but one for each of the four bit lines of the row RC along each contact row RC.
A number of contact vias or through conductors (ie, N _Y1n ) are provided. Thus, the actual spacing between the contact nodes of each bit line is still 48 transistors,
The maximum source-to-contact node resistance and maximum drain-to-contact node resistance occur in a staggered or staggered manner in the y-direction. Transistors having a source region in between the nodes of the first bit line will not be simultaneously victimized by having their drain regions in between the contact nodes of adjacent second bit lines, The benefits are gained. A field oxide portion OXF is used to separate adjacent bit line portions disposed along the contact row RC.

FIG. 11 shows the layout in the illustrated or set form. In FIG. 11, the floating gate
FG is can be understood that the illustrated so as to have ears 304 extending in the illustrated That set the bit line shape BL ₁ -BL _4. After plasma etching, these ears 304 tend to be square corners (corners), and thus, after fabrication, the floating gate FG is substantially at least in the portion above the bit line. It has a rectangular shape. It can be seen that the narrow portion 306 of the word line is above the floating gate of embodiment 300, while the wide portion 308 is above the protruding portion 301 of the bit line. Although not shown in FIG. 11, during the manufacturing period,
Photoresist stripping zigzag are provided on the white area 302 in FIG. 11, to be understood to define a channel region controlled by the word lines interposed between the bit line patterns BL ₁ -BL ₄ zigzag It is.

As described above, the specific embodiments of the present invention have been described in detail. However, the present invention is not limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. Of course, it is. For example, materials other than monocrystalline silicon, polycrystalline silicon, and silicon dioxide (eg, for insulating layers) may be used to form various substrates, word lines, and insulating layer portions of the disclosed memory arrays.
It is also possible to use Si ₃ N ₄ ) instead of having the floating gates in opposing rows interleaved with each other as shown in the preferred embodiment herein. Rows may be grouped together so as not to be affected by inconsistency. Furthermore, preferentially narrowing the word line relative to the floating gate width in connection with removing the field oxide portion can be selected independently of the staggered or staggered floating gate configuration. It is.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing a virtual ground memory array composed of split gate transistors, FIG. 2A is a schematic plan view showing a part of the memory array shown in FIG. FIG. 2B is an enlarged schematic view of a portion of FIG.
2C is a schematic plan view showing a part of FIG. 2B appearing after manufacturing, FIG. 3 is a schematic sectional view taken along line 3-3 in FIG. 2A, and FIG. FIG. 5 is a schematic cross-sectional view taken along line 4-4, FIG. 5 is a schematic cross-sectional view taken along line 5-5 of FIG. 2A, and FIG. FIG. 6B is a schematic plan view showing whether a staggered configuration, that is, a staggered configuration is used, and FIG. 6B shows how the word line pitch can be reduced by inverting the source-drain orientation of an adjacent row. FIG. 6C is a schematic plan view showing how the pitch between floating gates can be optimized in both the x and y directions, and FIG. 7A is a schematic plan view showing Combine the floating gate pattern with the photoresist mask to achieve the bit line injection shape. FIG. 7B is a schematic exploded perspective view showing one method for determining the position of the floating gate pattern, and FIG. 7A is a state in which the floating gate pattern is projected and positioned by a first amount in the area of the injection window defined in the photoresist mask. FIG. 7C is a schematic diagram showing an image of the bit line implantation of FIG. 7A, and FIG. 7C shows how the bit line image of FIG. 7A shows when the floating gate pattern shifts and further projects by a second amount into the area of the photoresist injection window. FIG. 7D is a schematic diagram showing what is pinched, FIG. 7D is an explanatory diagram showing the relationship between the mismatch between the photoresist mask and the floating gate pattern of FIG. 7A and the total bit line resistance, FIG. FIG. 8B illustrates that it is possible to reduce the effects of mismatch by shifting the floating gate to overlap the opposing sides of the bit line in accordance with the present invention. The schematic exploded perspective view and the schematic plan view, respectively, and FIG. 8C show how the bit line resistance can be coupled to the mismatch characteristics of opposing rows to reduce the effects of mismatch. FIG. 9A is a schematic plan view of the first embodiment according to the present invention, and FIG. 9B satisfies the minimum design criterion while enabling the word line pitch to be less than the minimum interval criterion. A second example of how the spacing between the corners of the floating gate and the spacing between the corners of the word line with alternating wide and narrow portions can be arranged to FIG. 9C is a schematic plan view of the embodiment, FIG. 9C is a schematic sectional view taken along line 9C-9C of FIG. 9A, FIG. 10 is a schematic view of a memory array according to the present invention,
FIG. 11 is a schematic plan view showing a memory array composed of word lines having a wide portion and a narrow portion, and the word lines are inclined to minimize the word line pitch. ,. (Explanation of symbols) C: column R: row FG: floating gate FO: field oxide part

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Liza Kezaronian United States, California 94501, Alameda, Shepherdson Lane 23 (56) References JP-A-62-1115777 (JP, A) JP-A-63-196071 ( JP, A) JP-A-63-219156 (JP, A)

Claims (17)

(57) [Claims] An array of erasable writable read-only memory cells (EPROM array) includes first, second and third rows of split gate transistors, each split gate transistor having a floating gate. Wherein the second row is interposed between the first and third rows, and the second row is offset with respect to the first and third rows, and thus the The floating gates of the transistors in the two rows are offset in a direction orthogonal to a substantially linear bit line common to the floating gates of the transistors in the first and third rows, and thus are aligned in the column direction. An array characterized by not being. 2. A floating gate according to claim 1, wherein the floating gates in the first, second and third rows have corner portions, and the floating gates in the second row and one of the first and third rows. Is the linear distance extending from corner to corner at an angle to the word line pitch direction, and said minimum distance is equal to the radius of a predetermined minimum design reference circle An array, characterized in that: 3. The method according to claim 2, wherein the angle is 15 ° to 75 °.
An array, wherein the array is within the range of ゜. 4. An array of erasable writable read-only memory cells (EPROM array) having a semiconductor substrate in which said memory cells are partially formed, wherein each memory cell of said array is self-aligned. A self-aligned split-gate single transistor comprising: (a) a source region; (b) a drain region; and (c) a channel region separating the drain region from the source region. (D) a floating gate formed above and insulated from a first portion of the channel region, wherein a first end of the floating gate is aligned with and defines one end of the drain region; And the second end of the floating gate is formed at the same time as the first end and is located from the first end. (E) positioned at a distance and above the channel region and separated from a closest end of the source region by a second portion of the channel region; A control gate formed above and insulated therefrom, and the array further has a first side and a second side where each bit line is laterally opposed. A plurality of bit line regions extending in the longitudinal direction and defined in the substrate, the first side and the second side having a drain portion, and each bit line The drain portion on the first side of the region serves as the drain region of the first set of split gate transistors, and the drain portion on the second side of each bit line region is the drain portion of the second set of split gate transistors. Acts as a region, wherein the drain portion of the second side of each bit line region does not face the drain portion and the transverse direction of the first side of each bit line regions EPRO
M array. 5. The EPROM array according to claim 4, wherein said first and second sets of transistors are alternately arranged in a longitudinal direction. 6. An EPROM array according to claim 4, wherein no insulating layer having a thickness of more than 500 ° is interposed between the floating gates of the split gate transistors and the channel regions of these transistors. 7. The method of claim 4 wherein the spacing between the substrate and the substrate facing the surface in substantially all portions of each surface of the floating gate is such that the floating gate inhibits inversion. An EPROM array characterized in that it is small enough to allow substantially inversion to be induced in said substrate when not writably charged. 8. The method of claim 7, wherein the spacing between the substrate and the substrate facing the surface of each floating gate is substantially constant for all portions of the substrate facing the surface. EPROM array featured. 9. The split gate transistor of claim 4, wherein said split gate transistors are arranged in horizontal rows, and further each having a horizontal width to interconnect a control gate of a single row split gate transistor. A plurality of word lines that extend, each word line having a first portion that is narrower than a width dimension of the floating gate, and the first portion being connected to the floating gate. An EPROM array having an overlapping shape. 10. The EPROM array according to claim 9, wherein each of said word lines has a second portion wider than said first portion. 11. The word line of claim 10, wherein said first word line is laterally offset so that a relatively narrow first portion of one word line is replaced by a relatively wide second portion of an adjacent word line. EP characterized by alignment in the longitudinal direction
ROM array. 12. A memory array formed on a semiconductor substrate, wherein first and second split gate transistors are provided, each of said first and second split gate transistors being integrally formed in said substrate. And a bit line defining end disposed insulated above the first channel region to inhibit inversion in the first channel region when data is written. A floating gate, a source region integrally formed in the substrate and spaced apart from the first channel region, and a source region integrally formed in the substrate and the first channel region and the source. A second channel region interposed between the first channel region and the first channel region; A drain region self-aligned with a bit line defining end of the floating gate and partially overlapping with the floating gate, and wherein the bit line region is the first and second split gate transistors And the bit line region extends in the longitudinal direction and is opposed to the first side portion and the second side portion. Extending longitudinally over a distance substantially greater than the width of the bit line region, wherein the drain regions of the first and second split gate transistors are first and second sides of the bit line region. A memory array, wherein the memory array is positioned in each of the sections. 13. The transistor of claim 12, wherein the first and second split gate transistors belong to first and second laterally extending rows of transistors formed on the substrate, respectively. , Wherein said first and second rows are adjacent to each other. 14. The control gate according to claim 12, wherein each of the first and second divided gate transistors has a control gate portion insulated above the second channel region. The portion is connected to a conductive word line passing above the floating gate,
A memory array, wherein at least a part of the word line located at a position where the word line passes above the floating gate is formed to have a width smaller than a width of the floating gate. 15. The device according to claim 12, wherein a distance between a floating gate of each transistor and a corresponding first channel region of the transistor is less than 500 ° in all portions of the floating gate. Memory array. 16. The method of claim 12, wherein at each surface of the floating gate, at substantially all of the surface, the spacing between the substrate and the substrate facing the surface is such that the floating gate is inverted. A memory array that is small enough to induce substantial inversion in said substrate when not charged by writing to inhibit. 17. The method of claim 12, wherein the insulating spacing between the floating gate of each transistor and the first channel region of the transistor is substantially constant for all portions of the floating gate. Memory array.