CN220367920U - Semiconductor device - Google Patents

Abstract

The application provides a semiconductor device relates to semiconductor technical field, including the substrate and set up the epitaxial layer on the substrate, the epitaxial layer has passive district and active area array, and adjacent two active areas separate through passive district, and adjacent two are listed as active area dislocation in the active area array arranges, on the basis that does not increase the device size, through the width of make full use of source metal, effectively improves the radiating effect of device. The epitaxial layer is provided with source electrode ohmic metal and drain electrode ohmic metal which are at least correspondingly positioned in each active region, the epitaxial layer is also provided with grid electrode metal which passes through the active regions in the same column, and the cross section area of a first grid electrode metal part of the grid electrode metal along the row direction of the active region array is larger than that of a second grid electrode metal part along the row direction of the active region array, so that the grid electrode metal resistance is reduced, and the device performance is improved.

Description

Semiconductor device

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device.

Background

With the high integration of semiconductor devices, efforts have been made to improve the yield of semiconductor fabrication. In the process of manufacturing a semiconductor device, as shown in fig. 1, a passive region 01 is generally disposed on the device so as to divide a two-dimensional electron gas into discontinuous active regions 02 along the y direction, and meanwhile, a source metal 04, a drain metal 03 and a gate metal 05 are disposed on the device, wherein, in order to reduce the volume of the device, a layout form of a common drain is adopted.

When the device shown in fig. 1 is in normal operation, heat is generated at the channel in the active region 02, so that the heat at the channel can only be dissipated in the y direction, which has a problem of poor heat dissipation. Meanwhile, the width of the drain metal 03 of the device in the y direction is smaller, so that the distance between two adjacent channels is smaller, heat accumulation caused by thermal coupling between the channels is easy to occur, and the problem of poor heat dissipation of the device is further aggravated.

Disclosure of Invention

The present application aims to provide a semiconductor device which aims at the defects in the prior art.

In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

in one aspect of the embodiments of the present application, a semiconductor device is provided, including a substrate and an epitaxial layer disposed on the substrate, where the epitaxial layer has an inactive region and an active region array, the active region array includes a plurality of active regions, each active region includes a plurality of active regions that are sequentially arranged at intervals, two adjacent active regions are separated by the inactive region, and the two adjacent active regions are arranged in a staggered manner; the epitaxial layer is provided with source electrode ohmic metal and drain electrode ohmic metal which are at least correspondingly positioned in each active region, the epitaxial layer is also provided with grid electrode metal penetrating through the active regions in the same column, the grid electrode metal comprises a first grid electrode metal part positioned in the inactive region and a second grid electrode metal part positioned in the active region, and the cross section area of the first grid electrode metal part along the row direction of the active region array is larger than that of the second grid electrode metal part along the row direction of the active region array.

Optionally, the width of the first gate metal portion along the row direction of the active area array is greater than the width of the second gate metal portion along the row direction of the active area array.

Optionally, the thickness of the first gate metal portion perpendicular to the substrate direction is greater than the thickness of the second gate metal portion perpendicular to the substrate direction.

Optionally, the semiconductor device further includes drain interconnect metals respectively connected to the drain ohmic metals in the same column of active regions.

Optionally, the semiconductor device further includes a plurality of source interconnect metals connected in one-to-one correspondence with the source ohmic metals of the plurality of active regions, the source interconnect metals of the same column being recessed relative to the gate metals of adjacent columns in a side-by-side position to form a gap between the source interconnect metals and the gate metals.

Optionally, any two source interconnect metals are connected via an air bridge or a dielectric bridge.

Optionally, a back metal is disposed on a side of the substrate facing away from the epitaxial layer, and a source via penetrating the epitaxial layer and the substrate is disposed in the inactive region, the source interconnect metal being connected to the back metal through the source via.

Optionally, two adjacent columns of active regions do not have overlapping regions along the row direction of the active region array.

Optionally, a gate pad is further disposed in the inactive region, and the gate pad is connected to the gate metal.

Optionally, a drain pad is further disposed in the inactive region, the drain pad being in metal connection with the plurality of drain interconnects.

The beneficial effects of this application include:

the application provides a semiconductor device, which comprises a substrate and an epitaxial layer arranged on the substrate, wherein the epitaxial layer is provided with an inactive region and an active region array, the active region array comprises a plurality of active regions, each active region comprises a plurality of active regions which are sequentially arranged at intervals, two adjacent active regions are separated by the inactive region, and the two adjacent active regions are arranged in a staggered manner; on the basis of not increasing the size of the device, the heat dissipation effect of the device is effectively improved by fully utilizing the width of the source metal. The epitaxial layer is provided with source electrode ohmic metal and drain electrode ohmic metal which are at least correspondingly positioned in each active region, the epitaxial layer is also provided with grid electrode metal which passes through the active regions in the same column, the grid electrode metal comprises a first grid electrode metal part positioned in the inactive region and a second grid electrode metal part positioned in the active region, the cross section area of the first grid electrode metal part along the row direction of the active region array is larger than that of the second grid electrode metal part along the row direction of the active region array, so that the grid electrode metal resistance is reduced, and the device performance is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a semiconductor device according to the prior art;

fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

FIG. 3 is a cross-sectional view of A-A of FIG. 2;

FIG. 4 is a cross-sectional view of B-B of FIG. 2;

FIG. 5 is one of the cross-sectional views of C-C of FIG. 2;

FIG. 6 is a second cross-sectional view of the structure of FIG. 2C-C;

fig. 7 is a second schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;

fig. 8 is a third schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.

Icon: 01. 130-inactive region; 02. 120-active region; 03-drain metal; 04-source metal; 05. 160-gate metal; 06. 172-source via; 100-a substrate; 110-an epitaxial layer; 140-source ohmic metal; 150-drain ohmic metal; 161-a first gate metal portion; 162-a second gate metal portion; 163-a first gate metal; 170-source interconnect metal; 171-first column source interconnect metal; 180-air bridge; 190-drain pads; 210-gate pad; 220-drain interconnect metal.

Detailed Description

The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "over" another element, it can be directly on or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Related terms such as "below" or "above" … "or" upper "or" lower "or" horizontal "or" vertical "may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It should be understood that these terms, and those terms discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the conventional semiconductor device, as shown in fig. 1, since the source through hole 06 needs to be disposed below the source metal 04 in the passive region 01 so as to facilitate grounding of the source metal 04, the width of the source metal 04 in the y direction is larger, the distance between two adjacent channels is larger, and heat dissipation is better. In particular, embodiments of the present application will be described below with reference to the accompanying drawings.

Referring to fig. 2 or 9, a semiconductor device is provided, including a substrate 100 and an epitaxial layer 110 disposed on the substrate 100, where the epitaxial layer 110 has a passive region 130 and an active region array, the active region array includes 4 rows of active regions (from left to right to be first to fourth rows of active regions respectively), each row of active regions includes 2 active regions 120 sequentially spaced apart from each other, and adjacent two rows of active regions are staggered, so that 8 active regions 120 included in the active region array can be staggered along the x direction and the y direction respectively, forming a layout shown in fig. 2 or 9, and the adjacent two active regions 120 are separated by the passive region 130, so that after the source ohmic metal 140 and the drain ohmic metal 150 disposed on the epitaxial layer 110 and the gate metal 160 disposed between the source ohmic metal 140 and the drain ohmic metal 150, the semiconductor device can perform heat dissipation in the y direction and also perform heat dissipation in the x direction when operating, thereby helping to improve the heat dissipation effect of the device and reduce the junction temperature of the device. For ease of understanding, the row direction of the active area array in this application is the y direction, and the column direction is the x direction.

Referring to fig. 1 and 2 in combination, fig. 2 of the present application is equivalent to dividing the large active region 02 on the left side in fig. 1 into four small active regions (i.e. the active regions 120 of the present application) along the x-direction, and then translating the two small active regions at intervals to the right along the y-direction, thereby forming a first column active region (including two small active regions) left in the original position and a second column active region (including two small active regions) after translation, and the large active region on the right side in fig. 1 can be divided by referring to the large active region, thereby forming four columns of active regions, 8 active regions 120 in total, wherein the four columns of active regions can fully utilize the region with the original source metal 04 having a larger width along the y-direction, so that the heat dissipation effect of the device is effectively improved without increasing the size of the device.

Of course, fig. 2 or fig. 9 are only an example of the present application, and it should be understood that the number of active areas 120 included in the active area array is not limited in the present application, and thus, the number of columns and rows included in the active area array may be reasonably changed according to actual requirements.

As shown in fig. 8, at least a source ohmic metal 140 and a drain ohmic metal 150 corresponding to each of the active regions 120 are disposed on the epitaxial layer 110, in other words, the source ohmic metal 140 and the drain ohmic metal 150 are disposed in each of the active regions 120, and on this basis, the source ohmic metal 140 and the drain ohmic metal 150 in each of the active regions may also extend toward the inactive region 130, respectively, as shown in fig. 8, if necessary. And a plurality of gate metals 160 are further disposed on the epitaxial layer 110, the gate metals may pass through the same column of active regions in a surface of a side of the epitaxial layer 110 facing away from the substrate 100, and in particular, the number of gate metals 160 passing through the same column of active regions is not limited, for example, as shown in fig. 8, two gate metals 160 may pass through the same column of active regions.

As shown in fig. 8, the gate metal 160 includes a first gate metal portion 161 located in the inactive region and a second gate metal portion 162 located in the active region, and a cross-sectional area of the first gate metal portion 161 in the y-direction is larger than a cross-sectional area of the second gate metal portion 162 in the y-direction, so that the first gate metal portion 161 can be thickened in the y-direction and/or the z-direction (i.e., a direction perpendicular to the x-direction and the y-direction, respectively), thereby having a larger cross-sectional area, contributing to a reduction in the resistance of the gate metal 160, and thus improving the device performance.

Optionally, the width of the first gate metal portion 161 along the y direction is greater than the width of the second gate metal portion 162 along the y direction, so that the cross-sectional area of the first gate metal portion 161 along the y direction is greater than the cross-sectional area of the second gate metal portion 162 along the y direction, which helps to reduce the resistance of the gate metal 160, thereby improving the device performance.

Optionally, the thickness of the first gate metal portion 161 perpendicular to the substrate 100 (i.e., the z direction) is greater than the thickness of the second gate metal portion 162 perpendicular to the substrate 100, so that the cross-sectional area of the first gate metal portion 161 along the y direction is greater than the cross-sectional area of the second gate metal portion 162 along the y direction, which helps to reduce the resistance of the gate metal 160, thereby improving the device performance.

As shown in fig. 7, the two-dimensional electron gas in the epitaxial layer 110 may be destroyed by etching, ion implantation, or the like, thereby forming an active region array and a passive region array as shown in fig. 7. On the basis of fig. 7, as shown in fig. 8, a source ohmic metal 140 and a drain ohmic metal 150 may be disposed in each active region 120 (of course, the source ohmic metal 140 and the drain ohmic metal 150 in the active region 120 may also extend to the inactive region 130 as needed), so that the source ohmic metal 140 and the drain ohmic metal 150 corresponding to the same active region 120 may form a conductive channel by means of two-dimensional electron gas in the active region 120, and then a gate metal 160 penetrating the same column of active regions 120 may be disposed to control the conductive channel. In the x-direction, the source ohmic metal 140 and the drain ohmic metal 150 may or may not cover the active region 120, as shown in fig. 8 where the active region 120 is not covered, the actual conductive channel width is the width covered by the source ohmic metal 140 or the drain ohmic metal 150. Of course, the width of the active region 120 is the same if covered.

On the basis of fig. 8, as shown in connection with fig. 9, a plurality of drain interconnect metals 220 are provided, each drain interconnect metal 220 being connected to a drain ohmic metal 150 within a corresponding same column of active regions 120, respectively. A plurality of source interconnect metals 170 are provided, each source interconnect metal 170 may be connected to one source ohmic metal 140, the source interconnect metal 170 may be located in the inactive region 130, and adjacent two source interconnect metals 170 may be spaced apart from each other or may be connected to each other, as shown in fig. 9, the source interconnect metals 170 located at the left side of the first column active region and the right side of the fourth column active region may be connected to each other, and the source interconnect metals 170 between adjacent two columns of active regions may be spaced apart from each other.

As shown in fig. 9, in order to reduce parasitic capacitance, the gate metals in the same column disposed in parallel with respect to the adjacent columns are shrunk, specifically, as shown in fig. 9, the inactive region between the first column active region and the second column active region may be used as a first inactive region, the first column source interconnection metal 171 is located in the first inactive region, and each source interconnection metal included in the first column source interconnection metal 171 is respectively connected to the source ohmic metal corresponding to the first column active region in a one-to-one correspondence manner, the gate metal passing through the second column active region and adjacent to the first inactive region may be used as a first gate metal 163, and in view of the misalignment between the adjacent two columns of active regions, the first column source interconnection metal 171 may be disposed in parallel with the first gate metal portion 161 of the first gate metal 163, thereby enabling the first column source interconnection metal 171 to be shrunk with respect to the first gate metal 163 (i.e., the first gate metal portion 161 in the same row) in order to ensure that the distance a between the source interconnection metal 170 and the first gate metal portion 161 is larger, so as to reduce parasitic capacitance. Of course, the source interconnect metal and the gate metal between other adjacent columns may also be referred to as being disposed.

On the basis of fig. 9, as shown in connection with fig. 2, any two source interconnect metals 170 may be connected via an air bridge 180, whereby parasitic capacitance can be reduced, wherein the air bridge 180 may be disposed only above the inactive region 130. Of course, in other embodiments, the spaced apart source interconnect metals 170 may be connected via dielectric bridges.

Referring to fig. 2 and 3 in combination, the source interconnect metal 170 on both sides of the active region may not be connected through the air bridge 180.

Referring to fig. 2 and 4 in combination, the source interconnect metal 170 on the left and right sides of the active region 120 of the same column may be connected over the inactive region 130 through an air bridge 180 or a dielectric bridge, thereby enabling to reduce parasitic capacitance.

As shown in fig. 2 and 5, the source interconnect metal 170 in the inactive region 130 may be directly connected, and as shown in fig. 2 and 6, the source interconnect metal 170 in the inactive region 130 may be connected through an air bridge 180.

Alternatively, as shown in fig. 2, a back metal is provided on the side of the substrate 100 facing away from the epitaxial layer 110, and a source via 172 is provided through the epitaxial layer 110 and the substrate 100 in the inactive region 130, the source interconnect metal 170 being connected to the back metal via 172.

Alternatively, as shown in fig. 2, two adjacent columns of active regions 120 have no overlapping area along the y-direction. Of course, in other examples, two adjacent columns of active regions 120 may also have overlapping regions along the y-direction.

Optionally, as shown in fig. 2, a gate pad 210 is further disposed in the inactive region 130, and the gate pad 210 is connected to the plurality of gate metals 160.

Optionally, as shown in fig. 2, a drain pad 190 is further disposed in the inactive region 130, and the drain pad 190 is connected to a plurality of drain interconnect metals 220.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. The semiconductor device is characterized by comprising a substrate and an epitaxial layer arranged on the substrate, wherein the epitaxial layer is provided with a passive region and an active region array, the active region array comprises a plurality of active regions, each active region comprises a plurality of active regions which are sequentially arranged at intervals, two adjacent active regions are separated by the passive region, and the active regions in two adjacent columns are arranged in a staggered manner;

the epitaxial layer is provided with source electrode ohmic metal and drain electrode ohmic metal which are at least correspondingly positioned in each active region, the epitaxial layer is also provided with grid electrode metal which passes through the active regions in the same column, the grid electrode metal comprises a first grid electrode metal part positioned in the inactive region and a second grid electrode metal part positioned in the active region, and the cross section area of the first grid electrode metal part along the row direction of the active region array is larger than the cross section area of the second grid electrode metal part along the row direction of the active region array.

2. The semiconductor device of claim 1, wherein a width of the first gate metal portion along a row direction of the active area array is greater than a width of the second gate metal portion along a row direction of the active area array.

3. The semiconductor device according to claim 1 or 2, wherein a thickness of the first gate metal portion in a direction perpendicular to the substrate is larger than a thickness of the second gate metal portion in a direction perpendicular to the substrate.

4. The semiconductor device of claim 1, further comprising drain interconnect metals respectively connected to drain ohmic metals within the same column of active regions.

5. The semiconductor device of claim 1, further comprising a plurality of source interconnect metals connected in one-to-one correspondence with source ohmic metals corresponding to a plurality of the active regions, the source interconnect metals of a same column being recessed relative to the gate metals of an adjacent column in a side-by-side position to form a gap between the source interconnect metals and the gate metals.

6. The semiconductor device of claim 5, wherein any two of said source interconnect metals are connected via an air bridge or a dielectric bridge.

7. The semiconductor device of claim 5, wherein a back metal is disposed on a side of the substrate facing away from the epitaxial layer, and a source via is disposed through the epitaxial layer and the substrate in the inactive region, the source interconnect metal being connected to the back metal through the source via.

8. The semiconductor device of claim 1, wherein two adjacent columns of the active regions have no overlap region along a row direction of the active region array.

9. The semiconductor device of claim 1, wherein a gate pad is further provided in the inactive region, the gate pad being connected to the gate metal.

10. The semiconductor device of claim 4, wherein a drain pad is further provided in said inactive region, said drain pad being in metal connection with a plurality of said drain interconnections.