JPH08111526A - Power transistor - Google Patents
Power transistorInfo
- Publication number
- JPH08111526A JPH08111526A JP6245475A JP24547594A JPH08111526A JP H08111526 A JPH08111526 A JP H08111526A JP 6245475 A JP6245475 A JP 6245475A JP 24547594 A JP24547594 A JP 24547594A JP H08111526 A JPH08111526 A JP H08111526A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type semiconductor
- semiconductor region
- type
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 148
- 239000000758 substrate Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 53
- 239000012535 impurity Substances 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、パワートランジスタに
関し、特に、縦型ＭＩＳＦＥＴ（Ｍetal Ｉnsulator Ｓ
emiconductor Ｆield Ｅffect Ｔransistor)に並列に接
続され、かつそのチャネル形成領域に流れる電流の方向
に対して逆方向に接続される定電圧ダイオード素子を有
するパワートランジスタに適用して有効な技術に関する
ものである。BACKGROUND OF THE INVENTION This invention relates to power transistors, in particular, a vertical MISFET (M etal I nsulator S
emiconductor F ield is connected in parallel with the E ffect T ransistor), and a technique effectively applied to a power transistor having a constant voltage diode connected in reverse direction to the direction of current flowing through the channel formation region Is.
【０００２】[0002]
【従来の技術】図７(要部断面図)に示すように、パワー
トランジスタに塔載される例えばｎチャネル導電型の縦
型ＭＩＳＦＥＴＱは、ゲート絶縁膜３Ａ、ゲート電極３
Ｂ、ドレイン領域、チャネル形成領域及びソース領域等
で構成される。ドレイン領域はn+型半導体基板２Ａ及び
その主面上に形成されたn-型エピタキシャル層２Ｂで構
成される。チャネル形成領域はn-型エピタキシャル層２
Ｂの主面に形成されたｐ型半導体領域４で構成される。
ソース領域はｐ型半導体領域４の主面に形成されたn+型
半導体領域５で構成される。2. Description of the Related Art As shown in FIG. 7 (a cross-sectional view of a main part), a vertical MISFET Q of, for example, an n-channel conductivity type mounted on a power transistor has a gate insulating film 3A and a gate electrode 3
B, a drain region, a channel forming region, a source region, and the like. The drain region is composed of an n + type semiconductor substrate 2A and an n− type epitaxial layer 2B formed on the main surface thereof. The channel formation region is the n-type epitaxial layer 2
The p-type semiconductor region 4 is formed on the main surface of B.
The source region is composed of the n + type semiconductor region 5 formed on the main surface of the p type semiconductor region 4.
【０００３】前記縦型ＭＩＳＦＥＴＱには、そのチャネ
ル形成領域に過大な電圧が印加されるのを防止する目的
として、定電圧ダイオード素子ＺＤが並列に接続され
る。この定電圧ダイオード素子ＺＤは、縦型ＭＩＳＦＥ
ＴＱのチャネル形成領域に流れる電流の方向に対して逆
方向に接続される。つまり、ｎチャネル導電型の場合、
定電圧ダイオード素子ＺＤのアノード領域(ｐ型領域)は
縦型ＭＩＳＦＥＴＱのソース領域に接続され、カソード
領域(ｎ型領域)はドレイン領域に接続される。A constant voltage diode element ZD is connected in parallel to the vertical MISFET Q for the purpose of preventing an excessive voltage from being applied to its channel forming region. This constant voltage diode element ZD is a vertical MISFE.
The connection is made in the direction opposite to the direction of the current flowing in the TQ channel forming region. That is, in the case of n-channel conductivity type,
The anode region (p-type region) of the constant voltage diode element ZD is connected to the source region of the vertical MISFET Q, and the cathode region (n-type region) is connected to the drain region.
【０００４】前記定電圧ダイオート素子ＺＤのアノード
領域は、n-型エピタキシャル層２Ｂの主面からその深さ
方向に向ってn+型半導体基板１Ａの主面に接触したp+型
半導体領域１３で構成され、カソード領域はn+型半導体
基板２Ａで構成される。つまり、定電圧ダイオード素子
ＺＤは、n-型エピタキシャル層１Ｂとn+型半導体基板１
Ａとの界面部にｐｎ接合部を形成している。The anode region of the constant voltage die auto element ZD is composed of the p + type semiconductor region 13 which is in contact with the main surface of the n + type semiconductor substrate 1A from the main surface of the n− type epitaxial layer 2B in the depth direction thereof. The cathode region is composed of the n + type semiconductor substrate 2A. That is, the constant voltage diode element ZD is composed of the n − type epitaxial layer 1B and the n + type semiconductor substrate 1.
A pn junction is formed at the interface with A.
【０００５】なお、前記縦型ＭＩＳＦＥＴＱに接続され
る定電圧ダイオード素子ＺＤについては、例えば特開昭
６０−１９６９７５号公報に記載されている。The constant voltage diode element ZD connected to the vertical MISFET Q is described in, for example, Japanese Patent Laid-Open No. 60-196975.
【０００６】[0006]
【発明が解決しようとする課題】前記パワートランジス
タの縦型ＭＩＳＦＥＴＱに接続される定電圧ダイオード
素子ＺＤは、n-型エピタキシャル層２Ｂの主面からその
深さ方向に向ってn+型半導体基板２Ａの主面に接触した
p+型半導体領域１３及びn+型半導体基板２Ａで構成さ
れ、n-型エピタキシャル層２Ｂとn+型半導体基板２Ａと
の界面部にｐｎ接合部を形成している。このため、p+型
半導体領域１３の領域に相当する分、n-型エピタキシャ
ル層２Ｂでの縦型ＭＩＳＦＥＴＱのドレイン領域の占有
面積が減少し、パワートランジスタのオン抵抗が増大す
るという問題があった。The constant voltage diode element ZD connected to the vertical MISFETQ of the power transistor is formed in the n + type semiconductor substrate 2A from the main surface of the n− type epitaxial layer 2B in the depth direction. Touched the main surface
It is composed of the p + type semiconductor region 13 and the n + type semiconductor substrate 2A, and a pn junction is formed at the interface between the n − type epitaxial layer 2B and the n + type semiconductor substrate 2A. For this reason, there is a problem that the area occupied by the drain region of the vertical MISFET Q in the n − type epitaxial layer 2B is reduced by the amount corresponding to the region of the p + type semiconductor region 13 and the on-resistance of the power transistor is increased.
【０００７】また、定電圧ダイオード素子ＺＤのp+型半
導体領域１３は熱拡散法でn-型エピタキシャル層２Ｂの
主面からその深さ方向(縦方向)に向って深く形成される
が、この深さ方向の広がりに伴って平面方向(横方向)に
も広がる。このため、定電圧ダイオード素子ＺＤの占有
面積が増大し、パワートランジスタのチップサイズが大
型化するという問題があった。Further, the p + type semiconductor region 13 of the constant voltage diode element ZD is formed deeper in the depth direction (vertical direction) from the main surface of the n− type epitaxial layer 2B by the thermal diffusion method. It also spreads in the plane direction (horizontal direction) as it expands in the vertical direction. Therefore, there is a problem that the area occupied by the constant voltage diode element ZD is increased and the chip size of the power transistor is increased.
【０００８】本発明の目的は、縦型ＭＩＳＦＥＴに並列
に接続される定電圧ダイオード素子を有するパワートラ
ンジスタのオン抵抗を低減することが可能な技術を提供
することにある。An object of the present invention is to provide a technique capable of reducing the on-resistance of a power transistor having a constant voltage diode element connected in parallel with a vertical MISFET.
【０００９】また、本発明の他の目的は、前記目的を達
成し、前記パワートランジスタのチップサイズの小型化
を図ることが可能な技術を提供することにある。Another object of the present invention is to provide a technique capable of achieving the above object and reducing the chip size of the power transistor.
【００１０】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１１】[0011]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.
【００１２】（１）第１導電型又は第２導電型の半導体
基板及びその主面上に形成された第１導電型の半導体層
をドレイン領域とする縦型ＭＩＳＦＥＴに並列に接続さ
れ、かつそのチャネル形成領域に流れる電流の方向に対
して逆方向に接続される定電圧ダイオード素子を有する
パワートランジスタにおいて、前記定電圧ダイオード素
子を前記第１導電型の半導体層の主面からその深さ方向
に向って順次配列された第２導電型の第１半導体領域、
第１導電型の第２半導体領域の夫々で構成する。(1) A semiconductor substrate of the first conductivity type or the second conductivity type and a vertical MISFET having a drain region of the semiconductor layer of the first conductivity type formed on the main surface thereof are connected in parallel and In a power transistor having a constant voltage diode element connected in a direction opposite to a direction of a current flowing in a channel forming region, the constant voltage diode element is provided from a main surface of the first conductivity type semiconductor layer in a depth direction thereof. A first semiconductor region of a second conductivity type sequentially arranged toward
Each of the second semiconductor regions of the first conductivity type is configured.
【００１３】（２）前記第２導電型の第１半導体領域、
第１導電型の第２半導体領域の夫々をイオン打込み法で
形成する。(2) The first semiconductor region of the second conductivity type,
Each of the second semiconductor regions of the first conductivity type is formed by the ion implantation method.
【００１４】[0014]
【作用】上述した手段（１）によれば、定電圧ダイオー
ド素子のｐｎ接合部を第１導電型の半導体層の主面から
その深さ方向(縦方向)に向って浅い位置に設定でき、定
電圧ダイオード素子下の第１導電型の半導体層を縦型Ｍ
ＩＳＦＥＴのドレイン領域として使用することができる
ので、この半導体層での縦型ＭＩＳＦＥＴのドレイン領
域の占有面積を増加できる。この結果、パワートランジ
スタのオン抵抗を低減することができる。According to the above-mentioned means (1), the pn junction portion of the constant voltage diode element can be set at a shallow position from the main surface of the first conductivity type semiconductor layer in the depth direction (vertical direction) thereof, The first conductive type semiconductor layer below the constant voltage diode element is formed into a vertical type M
Since it can be used as the drain region of the ISFET, the area occupied by the drain region of the vertical MISFET in this semiconductor layer can be increased. As a result, the on resistance of the power transistor can be reduced.
【００１５】上述した手段（２）によれば、第２導電型
の第１半導体領域、第１導型の第２半導体領域の夫々の
平面方向(横方向)の広がりを低減でき、定電圧ダイオー
ド素子の占有面積を縮小することができるので、パワー
トランジスタのチップサイズの小型化を図ることができ
る。According to the above-mentioned means (2), the spread in the plane direction (lateral direction) of each of the second conductive type first semiconductor region and the first conductive type second semiconductor region can be reduced, and the constant voltage diode can be reduced. Since the area occupied by the element can be reduced, the chip size of the power transistor can be reduced.
【００１６】[0016]
【実施例】以下、本発明の構成について、ｎチャネル導
電型の縦型ＭＩＳＦＥＴを塔載するパワートランジスタ
に本発明を適用した実施例とともに説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a power transistor on which an n-channel conductivity type vertical MISFET is mounted.
【００１７】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１８】（実施例１）本発明の実施例１であるパワ
ートランジスタの概略構成を図１（チップレイアウト
図）及び図２(図１の要部平面図)に示す。(Embodiment 1) A schematic configuration of a power transistor which is Embodiment 1 of the present invention is shown in FIG. 1 (chip layout diagram) and FIG. 2 (main part plan view of FIG. 1).
【００１９】図１及び図２に示すように、パワートラン
ジスタは平面が方形状に形成された半導体チップ１で構
成される。この半導体チップ１の中央領域１Ａには複数
の縦型ＭＩＳＦＥＴＱが塔載される。複数の縦型ＭＩＳ
ＦＥＴＱの夫々は、行列状に規則的に配置され、電気的
に並列に接続される。As shown in FIGS. 1 and 2, the power transistor is composed of a semiconductor chip 1 having a rectangular plane. In the central region 1A of the semiconductor chip 1, a plurality of vertical MISFETQ are mounted. Multiple vertical MIS
Each of the FETs Q is regularly arranged in a matrix and electrically connected in parallel.
【００２０】前記半導体チップ１の中央領域１Ａの周囲
には周辺領域１Ｂが配置される。この周辺領域１Ｂは、
縦型ＭＩＳＦＥＴＱが配置される中央領域１Ａの周囲を
囲み、その平面形状がリング形状で構成される。A peripheral region 1B is arranged around the central region 1A of the semiconductor chip 1. This peripheral area 1B is
The central area 1A in which the vertical MISFET Q is arranged surrounds the periphery of the central area 1A, and its planar shape is a ring shape.
【００２１】前記半導体チップ１は、基本的に単層配線
構造(単層アルミニウム配線構造)で構成される。半導体
チップ１の中央領域１Ａには、その大半の領域にソース
配線１０Ａが構成され、その一部の領域にゲート配線１
０Ｂが構成される。また、半導体チップ１の周辺領域１
Ｂには、その大半の領域にソース配線１０Ａと同電位の
ソースフィールドプレート配線１０Ｃが構成され、その
一部の領域にゲート配線１０Ｂが構成される。つまり、
本実施例のパワートランジスタは、ゲート抵抗を低減す
る目的として、ゲート配線１０Ｂを半導体チップ１の周
辺領域１Ｂにも配置している。The semiconductor chip 1 basically has a single-layer wiring structure (single-layer aluminum wiring structure). In the central area 1A of the semiconductor chip 1, the source wiring 10A is formed in most of the area and the gate wiring 1 is formed in part of the area.
0B is configured. In addition, the peripheral region 1 of the semiconductor chip 1
In B, the source field plate wiring 10C having the same potential as the source wiring 10A is formed in most of the area, and the gate wiring 10B is formed in part of the area. That is,
In the power transistor of this embodiment, the gate wiring 10B is also arranged in the peripheral region 1B of the semiconductor chip 1 for the purpose of reducing the gate resistance.
【００２２】前記半導体チップ１は、図２及び図３（図
２に示すＡ−Ａ切断線で切った断面図）に示すように、
例えば単結晶珪素からなるn+型半導体基板２Ａの主面上
にn-型エピタキシャル層２Ｂを形成した半導体基板２を
主体に構成される。n+型半導体基板２Ａの主面と対向す
るその裏面上にはドレイン電極１２が構成される。The semiconductor chip 1 is, as shown in FIGS. 2 and 3 (a sectional view taken along the line AA shown in FIG. 2),
For example, it is mainly composed of a semiconductor substrate 2 in which an n-type epitaxial layer 2B is formed on the main surface of an n + type semiconductor substrate 2A made of single crystal silicon. The drain electrode 12 is formed on the back surface of the n + type semiconductor substrate 2A, which faces the main surface.
【００２３】前記半導体基板１の主面(n-型エピタキシ
ャル層２Ｂの主面)には縦型ＭＩＳＦＥＴＱが構成され
る。この縦型ＭＩＳＦＥＴＱは、ゲート絶縁膜３Ａ、ゲ
ート電極３Ｂ、ドレイン領域、チャネル形成領域及びソ
ース領域等で構成される。ゲート絶縁膜３Ａは、n-型エ
ピタキシャル層２Ｂの主面上に形成され、例えば酸化珪
素膜で形成される。ゲート電極３Ｂは、ゲート絶縁膜３
Ａの主面上に形成され、例えば多結晶珪素膜で形成され
る。このゲート電極３Ｂの平面パターンは、網の目状で
構成される。ドレイン領域はn+型半導体基板２Ａ及びそ
の主面上に形成されたn-型エピタキシャル層２Ｂで構成
される。チャネル形成領域はn-型エピタキシャル層２Ｂ
の主面に形成されたｐ型半導体領域４で構成される。こ
のｐ型半導体領域４はゲート電極３で周囲を囲まれたn-
型エピタキシャル層２Ｂの主面に構成される。ソース領
域はｐ型半導体領域４の主面に形成されたn+型半導体領
域５で構成される。A vertical MISFET Q is formed on the main surface of the semiconductor substrate 1 (the main surface of the n--type epitaxial layer 2B). The vertical MISFET Q is composed of a gate insulating film 3A, a gate electrode 3B, a drain region, a channel forming region, a source region and the like. The gate insulating film 3A is formed on the main surface of the n − type epitaxial layer 2B, and is formed of, for example, a silicon oxide film. The gate electrode 3B is the gate insulating film 3
It is formed on the main surface of A and is formed of, for example, a polycrystalline silicon film. The plane pattern of the gate electrode 3B is formed in a mesh pattern. The drain region is composed of an n + type semiconductor substrate 2A and an n− type epitaxial layer 2B formed on the main surface thereof. The channel formation region is the n-type epitaxial layer 2B
Of the p-type semiconductor region 4 formed on the main surface. The p-type semiconductor region 4 is surrounded by the gate electrode 3 and is surrounded by n-
It is formed on the main surface of the type epitaxial layer 2B. The source region is composed of the n + type semiconductor region 5 formed on the main surface of the p type semiconductor region 4.
【００２４】前記縦型ＭＩＳＦＥＴＱのチャネル形成領
域であるｐ型半導体領域４、ソース領域であるn+型半導
体領域５の夫々には層間絶縁膜８に形成された接続孔９
を通してソース配線１０Ａが電気的に接続される。この
ソース配線１０Ａとゲート電極３Ｂとは層間絶縁膜８で
互いに電気的に分離される。層間絶縁膜８は例えばＰＳ
Ｇ(Ｐhospho Ｓilicate Ｇlass）膜で形成される。ま
た、縦型ＭＩＳＦＥＴＱのゲート電極３Ｂには層間絶縁
膜８に形成された接続孔(図示せず)を通してゲート配線
１０Ｂが接続される。A connection hole 9 formed in the interlayer insulating film 8 is formed in each of the p-type semiconductor region 4 which is the channel forming region and the n + type semiconductor region 5 which is the source region of the vertical MISFET Q.
The source wiring 10A is electrically connected through the. The source wiring 10A and the gate electrode 3B are electrically separated from each other by the interlayer insulating film 8. The interlayer insulating film 8 is, for example, PS
Formed by G (P hospho S ilicate G lass ) film. Further, the gate electrode 10B is connected to the gate electrode 3B of the vertical MISFET Q through a connection hole (not shown) formed in the interlayer insulating film 8.
【００２５】前記ソース配線１０Ａ上、ゲート配線１０
Ｂ上及びソースフィールドプレート配線１０Ｃ上を含む
半導体基板２の主面上には最終保護膜１１が形成され
る。この最終保護膜１１は例えばポリイミド系樹脂膜で
形成される。A gate wiring 10 is formed on the source wiring 10A.
A final protective film 11 is formed on the main surface of the semiconductor substrate 2 including B and the source field plate wiring 10C. The final protective film 11 is formed of, for example, a polyimide resin film.
【００２６】前記縦型ＭＩＳＦＥＴＱには、そのチャネ
ル形成領域に過大な電圧が印加されるのを防止する目的
として、定電圧ダイオード素子ＺＤが並列に接続され
る。この定電圧ダイオード素子ＺＤは、縦型ＭＩＳＦＥ
ＴＱのチャネル形成領域に流れる電流の方向に対して逆
方向に接続される。つまり、本実施例の定電圧ダイオー
ド素子ＺＤは、縦型ＭＩＳＦＥＴＱがｎチャネル導電型
で構成されているので、図４（等価回路図）に示すよう
に、縦型ＭＩＳＦＥＴＱのソース領域にアノード領域
(ｐ型領域)が電気的に接続され、縦型ＭＩＳＦＥＴＱの
ドレイン領域にカソード領域(ｎ型領域)が電気的に接続
される。A constant voltage diode element ZD is connected in parallel to the vertical MISFET Q for the purpose of preventing an excessive voltage from being applied to its channel forming region. This constant voltage diode element ZD is a vertical MISFE.
The connection is made in the direction opposite to the direction of the current flowing in the TQ channel forming region. That is, in the constant voltage diode element ZD of the present embodiment, since the vertical MISFET Q is of the n-channel conductivity type, as shown in FIG. 4 (equivalent circuit diagram), the anode region is formed in the source region of the vertical MISFET Q.
The (p-type region) is electrically connected, and the cathode region (n-type region) is electrically connected to the drain region of the vertical MISFET Q.
【００２７】前記定電圧ダイオード素子ＺＤのアノード
領域、カソード領域の夫々は、図３に示すように、n-型
エピタキシャル層２Ｂの主面からその深さ方向(縦方向)
に向って順次配列されたp+型半導体領域７、n+型半導体
領域６の夫々で構成される。p+型半導体領域７はソース
配線１０Ａを介して縦型ＭＩＳＦＥＴＱのソース領域で
あるn+型半導体領域５に電気的に接続される。n+型半導
導体領域６は縦型ＭＩＳＦＥＴＱのドレイン領域である
n-型エピタキシャル層２Ｂ及びn+型半導体基板２Ａに電
気的に接続される。このp+型半導体領域７、n+型半導体
領域６の夫々はn-型エピタキシャル層２Ｂの主面からそ
の深さ方向に向って浅い位置に構成され、p+型半導体領
域７とn+型半導体領域６とが接合するｐｎ接合部の位置
（n-型エピタキシャル層２Ｂの主面からの位置）はｐ型
半導体領域４の底面とn-型エピタキシャル層２Ｂとが接
合するｐｎ接合部の位置（n-型エピタキシャル層２Ｂの
主面からの位置）に比べて浅く構成される。このよう
に、定電圧ダイオード素子ＺＤをn-型エピタキシャル層
２Ｂの主面からその深さ方向に向って順次配列されたp+
型半導体領域７、n+型半導体領域６の夫々で構成するこ
とにより、p+型半導体領域７とn+型半導体領域６とが接
合するｐｎ接合部をn-型エピタキシャル層２Ｂの主面か
らその深さ方向に向って浅い位置に設定することがで
き、定電圧ダイオード素子ＺＤ下のn-型エピタキシャル
層２Ｂを縦型ＭＩＳＦＥＴＱのドレイン領域として使用
することができる。As shown in FIG. 3, each of the anode region and the cathode region of the constant voltage diode element ZD extends in the depth direction (vertical direction) from the main surface of the n-type epitaxial layer 2B.
Of the p + type semiconductor region 7 and the n + type semiconductor region 6 which are sequentially arranged toward each other. The p + type semiconductor region 7 is electrically connected to the n + type semiconductor region 5, which is the source region of the vertical MISFET Q, via the source wiring 10A. The n + type semiconductor region 6 is the drain region of the vertical MISFET Q.
It is electrically connected to the n-type epitaxial layer 2B and the n + type semiconductor substrate 2A. Each of the p + type semiconductor region 7 and the n + type semiconductor region 6 is formed at a shallow position from the main surface of the n− type epitaxial layer 2B in the depth direction thereof, and the p + type semiconductor region 7 and the n + type semiconductor region 6 are formed. Is the position of the pn junction (the position from the main surface of the n-type epitaxial layer 2B) at which the bottom of the p-type semiconductor region 4 and the n-type epitaxial layer 2B are joined (n-type). It is shallower than the position (from the main surface of the epitaxial layer 2B). In this way, the constant voltage diode elements ZD are sequentially arranged from the main surface of the n-type epitaxial layer 2B in the depth direction to the p +
Since the p-type semiconductor region 7 and the n + -type semiconductor region 6 are respectively formed, the pn junction where the p + -type semiconductor region 7 and the n + -type semiconductor region 6 are joined is formed from the main surface of the n-type epitaxial layer 2B to the depth thereof. It can be set at a shallow position in the direction, and the n − type epitaxial layer 2B under the constant voltage diode element ZD can be used as the drain region of the vertical MISFET Q.
【００２８】前記p+型半導体領域７、n+型半導体領域６
の夫々はイオン打込み法で形成される。このイオン打込
み法は、p+型半導体領域７、n+型半導体領域６の夫々の
平面方向(横方向)の拡がりを熱拡散法に比べて抑えるこ
とができ、p+型半導体領域７、n+型半導体領域６の占有
面積を縮小することができる。The p + type semiconductor region 7 and the n + type semiconductor region 6
Are formed by the ion implantation method. This ion implantation method can suppress the spread of the p + type semiconductor region 7 and the n + type semiconductor region 6 in the plane direction (lateral direction) as compared with the thermal diffusion method, and the p + type semiconductor region 7 and the n + type semiconductor region 6 can be suppressed. The area occupied by 6 can be reduced.
【００２９】前記p+型半導体領域７、n+型半導体領域６
の夫々は、縦型ＭＩＳＦＥＴＱのチャネル形成領域であ
るｐ型半導体領域４で周囲を囲まれたn-型エピタキシャ
ル層２Ｂの主面に構成される。つまり、定電圧ダイオー
ド素子ＺＤは、ｐ型半導体領域４の占有面積内に構成さ
れる。このように、定電圧ダイオード素子ＺＤのp+型半
導体領域７、n+型半導体領域６の夫々をｐ型半導体領域
４で周囲を囲まれたn-型エピタキシャル層２Ｂの主面に
構成することにより、定電圧ダイオード素子ＺＤの占有
面積を廃止することができる。The p + type semiconductor region 7 and the n + type semiconductor region 6
Are formed on the main surface of the n-type epitaxial layer 2B surrounded by the p-type semiconductor region 4 which is the channel forming region of the vertical MISFETQ. That is, the constant voltage diode element ZD is formed within the occupied area of the p-type semiconductor region 4. Thus, by configuring each of the p + type semiconductor region 7 and the n + type semiconductor region 6 of the constant voltage diode element ZD on the main surface of the n − type epitaxial layer 2B surrounded by the p type semiconductor region 4, The occupied area of the constant voltage diode element ZD can be eliminated.
【００３０】前記縦型ＭＩＳＦＥＴＱのソース領域であ
るn+型半導体領域５は例えば１×１０21［atoms/cm3］
程度の不純物濃度に設定される。チャネル形成領域であ
るｐ型半導体領域４は例えば１×１０17［atoms/cm3］
程度の不純物濃度に設定される。ドレイン領域であるn-
型エピタキシャル層１Ｂは例えば７×１０15［atoms/cm
3］程度の不純物濃度に設定され、n+型半導体基板２Ａ
は例えば２×１０18［atoms/cm3］程度の不純物濃度に
設定される。The n + type semiconductor region 5 which is the source region of the vertical MISFET Q is, for example, 1 × 10 21 [atoms / cm 3 ].
The impurity concentration is set to a level. The p-type semiconductor region 4 which is a channel forming region is, for example, 1 × 10 17 [atoms / cm 3 ].
The impurity concentration is set to a level. Drain region n-
The type epitaxial layer 1B has, for example, 7 × 10 15 [atoms / cm
The impurity concentration is set to about 3 ], and the n + type semiconductor substrate 2A
Is set to an impurity concentration of, for example, 2 × 10 18 [atoms / cm 3 ].
【００３１】前記定電圧ダイオード素子ＺＤのアノード
領域であるp+型半導体領域７は例えば１×１０18［atom
s/cm3］程度の不純物濃度に設定される。カソード領域
であるn+型半導体領域６は例えば１×１０16［atoms/cm
3］程度の不純物濃度に設定される。なお、定電圧ダイ
オード素子ＺＤのp+型半導体領域７、n+型半導体領域６
の夫々の不純物濃度は本実施例に限定されるものではな
く、n-型エピタキシャル層２Ｂとｐ型半導体層４とが接
合するｐｎ接合部での逆耐圧に比べてp+型半導体領域７
とn+型半導体領域６とが接合するｐｎ接合部での逆耐圧
を小さくできる不純物濃度であれば、p+型半導体領域
７、n+型半導体領域６の夫々をいかなる不純物濃度に設
定してもよい。The p + type semiconductor region 7 which is the anode region of the constant voltage diode element ZD is, for example, 1 × 10 18 [atom].
The impurity concentration is set to about s / cm 3 ]. The n + type semiconductor region 6 which is the cathode region is, for example, 1 × 10 16 [atoms / cm
The impurity concentration is set to about 3 ]. Incidentally, the p + type semiconductor region 7 and the n + type semiconductor region 6 of the constant voltage diode element ZD.
The impurity concentration of each is not limited to that in the present embodiment, and the p + type semiconductor region 7 is compared with the reverse breakdown voltage at the pn junction where the n − type epitaxial layer 2B and the p type semiconductor layer 4 are joined.
The impurity concentration of each of the p + type semiconductor region 7 and the n + type semiconductor region 6 may be set to any impurity concentration as long as it can reduce the reverse breakdown voltage at the pn junction where the n + type semiconductor region 6 and the n + type semiconductor region 6 are joined.
【００３２】以上、ｎチャネル導電型の縦型ＭＩＳＦＥ
ＴＱに接続される定電圧ダイオード素子ＺＤを有するパ
ワートランジスタについて説明したが、本実施例によれ
ば以下の作用効果が得られる。As described above, the n-channel conductivity type vertical MISFE
Although the power transistor having the constant voltage diode element ZD connected to TQ has been described, the following operational effects can be obtained according to this embodiment.
【００３３】n+型半導体基板２Ａ及びその主面上に形成
されたn-型エピタキシャル層２Ｂをドレイン領域とする
縦型ＭＩＳＦＥＴＱに並列に接続され、かつそのチャネ
ル形成領域に流れる電流の方向に対して逆方向に接続さ
れる定電圧ダイオード素子ＺＤを有するパワートランジ
スタにおいて、前記定電圧ダイオード素子ＺＤをn-型エ
ピタキシャル層２Ｂの主面からその深さ方向に向って順
次配列されたp+型半導体領域７、n+型半導体領域６の夫
々で構成することにより、定電圧ダイオード素子ＺＤの
ｐｎ接合部をn-型エピタキシャル層２Ｂの主面から深さ
方向に向って浅い位置に設定でき、定電圧ダイオード素
子ＺＤ下のn-型エピタキシャル層２Ｂを縦型ＭＩＳＦＥ
Ｔのドレイン領域として使用することができるので、こ
のn-型エピタキシャル層２Ｂでの縦型ＭＩＳＦＥＴのド
レイン領域の占有面積を増加できる。この結果、パワー
トランジスタのオン抵抗を低減することができる。The n + type semiconductor substrate 2A and the n-type epitaxial layer 2B formed on the main surface of the n + type semiconductor substrate 2A are connected in parallel to the vertical MISFET Q having a drain region, and the direction of the current flowing in the channel forming region is set. In the power transistor having the constant voltage diode elements ZD connected in the reverse direction, the constant voltage diode elements ZD are sequentially arranged in the depth direction from the main surface of the n-type epitaxial layer 2B. , N + type semiconductor region 6, the pn junction part of the constant voltage diode element ZD can be set at a shallow position in the depth direction from the main surface of the n− type epitaxial layer 2B. The n-type epitaxial layer 2B under the ZD is formed into a vertical MISFE.
Since it can be used as the drain region of T, the area occupied by the drain region of the vertical MISFET in the n − type epitaxial layer 2B can be increased. As a result, the on resistance of the power transistor can be reduced.
【００３４】また、p+型半導体領域７、n+型半導体領域
６の夫々をイオン打込み法で形成することにより、p+型
半導体領域７、n+型半導体領域６の夫々の平面方向(横
方向)の広がりを低減でき、定電圧ダイオード素子ＺＤ
の占有面積を縮小することができるので、パワートラン
ジスタの小型化を図ることができる。Further, by forming each of the p + type semiconductor region 7 and the n + type semiconductor region 6 by the ion implantation method, the p + type semiconductor region 7 and the n + type semiconductor region 6 respectively spread in the plane direction (lateral direction). Constant voltage diode element ZD
Since the area occupied by the power transistor can be reduced, the power transistor can be downsized.
【００３５】また、p+型半導体領域７、n+型半導体領域
６の夫々を縦型ＭＩＳＦＥＴＱのチャネル形成領域であ
るｐ型半導体領域４で周囲を囲まれたn-型エピタキシャ
ル層２Ｂの主面に構成することにより、定電圧ダイオー
ド素子ＺＤの占有面積を廃止できるので、この占有面積
に相当する分、パワートランジスタの小型化を図ること
ができる。Further, each of the p + type semiconductor region 7 and the n + type semiconductor region 6 is formed on the main surface of the n − type epitaxial layer 2B surrounded by the p type semiconductor region 4 which is the channel forming region of the vertical MISFET Q. By doing so, the occupied area of the constant voltage diode element ZD can be eliminated, and the power transistor can be miniaturized by the amount corresponding to this occupied area.
【００３６】（実施例２）本発明の実施例２であるパワ
ートランジスタの概略構成を図５(要部断面図)に示す。(Embodiment 2) A schematic configuration of a power transistor which is Embodiment 2 of the present invention is shown in FIG. 5 (main part sectional view).
【００３７】図５に示すように、パワートランジスタは
n+型半導体基板２Ａの主面上にn-型エピタキシャル層２
Ｂを形成した半導体基板２を主体に構成される。この半
導体基板２の主面には、前述の実施例１と同様に、ｎチ
ャネル導電型の縦型ＭＩＳＦＥＴＱが構成される。As shown in FIG. 5, the power transistor is
The n-type epitaxial layer 2 is formed on the main surface of the n + type semiconductor substrate 2A.
The semiconductor substrate 2 on which B is formed is mainly formed. On the main surface of the semiconductor substrate 2, an n-channel conductivity type vertical MISFET Q is formed as in the first embodiment.
【００３８】前記縦型ＭＩＳＦＥＴＱには定電圧ダイオ
ード素子ＺＤが並列に接続される。定電圧ダイオード素
子ＺＤは、n-型エピタキシャル層２Ｂの主面からその深
さ方向に向って順次配列されたｐ型半導体領域４、n+型
半導体領域６の夫々で構成される。つまり、定電圧ダイ
オード素子ＺＤのアノード領域は縦型ＭＩＳＦＥＴＱの
チャネル形成領域であるｐ型半導体領域４で構成され
る。A constant voltage diode element ZD is connected in parallel with the vertical MISFET Q. The constant voltage diode element ZD is composed of a p-type semiconductor region 4 and an n + -type semiconductor region 6 which are sequentially arranged from the main surface of the n-type epitaxial layer 2B in the depth direction. That is, the anode region of the constant voltage diode element ZD is composed of the p-type semiconductor region 4 which is the channel formation region of the vertical MISFETQ.
【００３９】前記定電圧ダイオード素子ＺＤにおいて、
ｐ型半導体領域４とn+型半導体領域６とが接合するｐｎ
接合部の位置(n-型エピタキシャル層２Ｂの主面からの
位置)は、ｐ型半導体領域４の底面とn-型エピタキシャ
ル層２Ｂとが接合するｐｎ接合部の位置（n-型エピタキ
シャル層２Ｂの主面からの位置）に比べて浅く構成され
る。In the constant voltage diode element ZD,
pn in which the p-type semiconductor region 4 and the n + -type semiconductor region 6 are joined
The position of the junction (the position from the main surface of the n-type epitaxial layer 2B) is the position of the pn junction where the bottom surface of the p-type semiconductor region 4 and the n-type epitaxial layer 2B are joined (n-type epitaxial layer 2B). The position from the main surface) is shallower than that of the main surface.
【００４０】このように、定電圧ダイオード素子ＺＤを
n-型エピタキシャル層２Ｂの主面からその深さ方向に向
って順次配列されたｐ型半導体領域４、n+型半導体領域
６の夫々で構成することにより、前述の実施例１と同様
の効果が得られる。In this way, the constant voltage diode element ZD is
By configuring the p-type semiconductor region 4 and the n + -type semiconductor region 6 which are sequentially arranged from the main surface of the n-type epitaxial layer 2B in the depth direction, the same effect as that of the first embodiment described above can be obtained. can get.
【００４１】また、定電圧ダイオード素子ＺＤのカソー
ド領域を縦型ＭＩＳＦＥＴＱのチャネル形成領域である
ｐ型半導体領域４で構成することにより、定電圧ダイオ
ード素子ＺＤの製造工程を簡略化することができるの
で、パワートランジスタの歩留まりを高めることができ
る。Further, by forming the cathode region of the constant voltage diode device ZD by the p-type semiconductor region 4 which is the channel forming region of the vertical MISFET Q, the manufacturing process of the constant voltage diode device ZD can be simplified. The yield of power transistors can be increased.
【００４２】（実施例３）本発明の実施例３であるパワ
ートランジスタの概略構成を図６(要部断面図)に示す。(Embodiment 3) A schematic structure of a power transistor which is Embodiment 3 of the present invention is shown in FIG.
【００４３】図６に示すように、パワートランジスタは
n+型半導体基板２Ａの主面上にn-型エピタキシャル層２
Ｂを形成した半導体基板２を主体に構成される。この半
導体基板２の主面には、前述の実施例２と同様に、ｎチ
ャネル導電型の縦型ＭＩＳＦＥＴＱが構成される。As shown in FIG. 6, the power transistor is
The n-type epitaxial layer 2 is formed on the main surface of the n + type semiconductor substrate 2A.
The semiconductor substrate 2 on which B is formed is mainly formed. On the main surface of the semiconductor substrate 2, an n-channel conductivity type vertical MISFET Q is formed as in the second embodiment.
【００４４】前記縦型ＭＩＳＦＥＴＱには定電圧ダイオ
ード素子ＺＤが並列に接続される。定電圧ダイオード素
子ＺＤは、n-型エピタキシャル層２Ｂの主面からその深
さ方向に向って順次配列されたｐ型半導体領域４、n+型
半導体領域６の夫々で構成される。このｐ型半導体領域
４とn+型半導体領域６とが接合するｐｎ接合部の位置(n
-型エピタキシャル層２Ｂの主面からの位置)は、ｐ型半
導体領域４の底面とn-型エピタキシャル層２Ｂとが接合
するｐｎ接合部の位置（n-型エピタキシャル層２Ｂの主
面からの位置）と同一に構成される。A constant voltage diode element ZD is connected in parallel to the vertical MISFET Q. The constant voltage diode element ZD is composed of a p-type semiconductor region 4 and an n + -type semiconductor region 6 which are sequentially arranged from the main surface of the n-type epitaxial layer 2B in the depth direction. The position of the pn junction where the p-type semiconductor region 4 and the n + -type semiconductor region 6 are joined (n
The position from the main surface of the − type epitaxial layer 2B is the position of the pn junction where the bottom surface of the p type semiconductor region 4 and the n − type epitaxial layer 2B are joined (the position from the main surface of the n − type epitaxial layer 2B). ) Is configured the same.
【００４５】このように、定電圧ダイオード素子ＺＤを
n-型エピタキシャル層２Ｂの主面からその深さ方向に向
って順次配列されたｐ型半導体領域４、n+型半導体領域
６の夫々で構成し、このｐ型半導体領域４とn+型半導体
領域６とが接合するｐｎ接合部の位置をｐ型半導体領域
４の底面とn-型エピタキシャル層２Ｂとが接合するｐｎ
接合部の位置と同一に構成することにより、前述の実施
例２と同様の効果が得られる。In this way, the constant voltage diode element ZD is
Each of the p-type semiconductor region 4 and the n + -type semiconductor region 6 is sequentially arranged from the main surface of the n-type epitaxial layer 2B in the depth direction, and the p-type semiconductor region 4 and the n + -type semiconductor region 6 are formed. The position of the pn junction where is joined to is the pn where the bottom of the p-type semiconductor region 4 and the n-type epitaxial layer 2B are joined.
By configuring the same as the position of the joining portion, the same effect as that of the above-described second embodiment can be obtained.
【００４６】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００４７】例えば、本発明は、ｐチャネル導電型の縦
型ＭＩＳＦＥＴに並列に接続される定電圧ダイオード素
子を有するパワートランジスタに適用できる。この場
合、定電圧ダイオード素子ＺＤのアノード領域は縦型Ｍ
ＩＳＦＥＴのドレイン領域に電気的に接続され、カソー
ド領域はソース領域に電気的に接続される。For example, the present invention can be applied to a power transistor having a constant voltage diode element connected in parallel with a vertical MISFET of p-channel conductivity type. In this case, the anode region of the constant voltage diode element ZD is a vertical M type.
The drain region of the ISFET is electrically connected, and the cathode region is electrically connected to the source region.
【００４８】[0048]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００４９】縦型ＭＩＳＦＥＴに並列に接続される定電
圧ダイオード素子を有するパワートランジスタのオン抵
抗を低減することができる。It is possible to reduce the on-resistance of the power transistor having the constant voltage diode element connected in parallel to the vertical MISFET.
【００５０】また、前記パワートランジスタのチップサ
イズの小型化を図ることができる。Further, the chip size of the power transistor can be reduced.
【図１】 本発明の実施例１であるパワートランジスタ
の概略構成を示すチップレイアウト図。FIG. 1 is a chip layout diagram showing a schematic configuration of a power transistor that is Embodiment 1 of the present invention.
【図２】 図１の要部平面図。FIG. 2 is a plan view of a main part of FIG.
【図３】 図２に示すＡ−Ａ切断線で切った断面図。FIG. 3 is a cross-sectional view taken along the line AA shown in FIG.
【図４】 前記パワートランジスタに塔載される縦型Ｍ
ＩＳＦＥＴ及び定電圧ダイオード素子の等価回路図。FIG. 4 is a vertical M mounted on the power transistor.
The equivalent circuit diagram of ISFET and a constant voltage diode element.
【図５】 本発明の実施例２であるパワートランジスタ
の要部断面図。FIG. 5 is a cross-sectional view of essential parts of a power transistor that is Embodiment 2 of the present invention.
【図６】 本発明の実施例３であるパワートランジスタ
の要部断面図。FIG. 6 is a cross-sectional view of essential parts of a power transistor that is Embodiment 3 of the present invention.
【図７】 従来のパワートランジスタの概略構成を示す
要部断面図。FIG. 7 is a cross-sectional view of a main part showing a schematic configuration of a conventional power transistor.
１…半導体チップ、２…半導体基板、２Ａ…n+型半導体
基板、２Ｂ…n-型エピタキシャル層、３Ａ…ゲート絶縁
膜、３Ｂ…ゲート電極、４…ｐ型半導体領域、５…n+型
半導体領域、６…n+型半導体領域、７…p+型半導体領
域、８…層間絶縁膜、９…接続孔、１０Ａ…ソース配
線、１０Ｂ…ゲート配線、１１…最終保護膜、１２…ド
レイン配線。DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Semiconductor substrate, 2A ... n + type semiconductor substrate, 2B ... n- type epitaxial layer, 3A ... Gate insulating film, 3B ... Gate electrode, 4 ... P type semiconductor region, 5 ... N + type semiconductor region, 6 ... N + type semiconductor region, 7 ... P + type semiconductor region, 8 ... Interlayer insulating film, 9 ... Connection hole, 10A ... Source wiring, 10B ... Gate wiring, 11 ... Final protective film, 12 ... Drain wiring.
Claims (4)
及びその主面上に形成された第１導電型の半導体層をド
レイン領域とする縦型ＭＩＳＦＥＴに並列に接続され、
かつそのチャネル形成領域に流れる電流の方向に対して
逆方向に接続される定電圧ダイオード素子を有するパワ
ートランジスタにおいて、前記定電圧ダイオード素子を
前記第１導電型の半導体層の主面からその深さ方向に向
って順次配列された第２導電型の第１半導体領域、第１
導電型の第２半導体領域の夫々で構成したことを特徴と
するパワートランジスタ。1. A semiconductor substrate of a first conductivity type or a second conductivity type and a vertical MISFET having a drain region of a semiconductor layer of the first conductivity type formed on the main surface thereof are connected in parallel,
In a power transistor having a constant voltage diode element connected in the direction opposite to the direction of the current flowing in the channel formation region, the constant voltage diode element is formed from the main surface of the first conductivity type semiconductor layer to the depth thereof. A first semiconductor region of a second conductivity type sequentially arranged in a direction,
A power transistor comprising each of the conductive second semiconductor regions.
導電型の第２半導体領域の夫々はイオン打込み法で形成
されることを特徴とする請求項１に記載のパワートラン
ジスタ。2. A first semiconductor region of the second conductivity type, a first
The power transistor according to claim 1, wherein each of the conductive type second semiconductor regions is formed by an ion implantation method.
導電型の第２半導体領域の夫々は、前記縦型ＭＩＳＦＥ
Ｔのチャネル形成領域である第２導電型の第３半導体領
域で周囲を囲まれた領域内に構成されることを特徴とす
る請求項１又請求項２に記載のパワートランジスタ。3. A first semiconductor region of the second conductivity type, a first
Each of the conductive type second semiconductor regions is formed of the vertical MISFE.
3. The power transistor according to claim 1, wherein the power transistor is formed in a region surrounded by a third semiconductor region of the second conductivity type, which is a T channel formation region.
記縦型ＭＩＳＦＥＴのチャネル形成領域として構成され
た半導体領域であることを特徴とする請求項１又は請求
項２に記載のパワートランジスタ。4. The power transistor according to claim 1, wherein the first semiconductor region of the second conductivity type is a semiconductor region configured as a channel formation region of the vertical MISFET. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6245475A JPH08111526A (en) | 1994-10-11 | 1994-10-11 | Power transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6245475A JPH08111526A (en) | 1994-10-11 | 1994-10-11 | Power transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08111526A true JPH08111526A (en) | 1996-04-30 |
Family
ID=17134219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6245475A Pending JPH08111526A (en) | 1994-10-11 | 1994-10-11 | Power transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08111526A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100988690B1 (en) * | 2002-07-31 | 2010-10-18 | 가부시키가이샤 히타치초엘에스아이시스템즈 | A semiconductor memory device |
-
1994
- 1994-10-11 JP JP6245475A patent/JPH08111526A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100988690B1 (en) * | 2002-07-31 | 2010-10-18 | 가부시키가이샤 히타치초엘에스아이시스템즈 | A semiconductor memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2597412B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6713794B2 (en) | Lateral semiconductor device | |
| US5686750A (en) | Power semiconductor device having improved reverse recovery voltage | |
| JPS61182264A (en) | Vertical type mos transistor | |
| JPH02275675A (en) | Mos type semiconductor device | |
| US6703665B1 (en) | Transistor | |
| JP3827954B2 (en) | IGBT with PN separation layer | |
| US20120126312A1 (en) | Vertical dmos-field effect transistor | |
| JP2001007322A (en) | High breakdown strength field-effect transistor | |
| JPH0494576A (en) | Vertical power mos fet | |
| JPWO2003075353A1 (en) | Semiconductor element | |
| JP3448138B2 (en) | Method for manufacturing semiconductor device | |
| JP2723868B2 (en) | Semiconductor device | |
| JP3505039B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH08111526A (en) | Power transistor | |
| JP3217552B2 (en) | Horizontal high voltage semiconductor device | |
| JP3301271B2 (en) | Horizontal power MOSFET | |
| JPH11214511A (en) | Semiconductor device and wiring method in semiconductor device | |
| JPH07118542B2 (en) | Vertical MOSFET | |
| JP2646765B2 (en) | MIS gate controlled thyristor semiconductor device | |
| JP2816985B2 (en) | Vertical MOS field-effect transistor | |
| JPH118381A (en) | Semiconductor device | |
| JPH01290265A (en) | Mos type semiconductor device | |
| JP2002373987A (en) | Insulated gate field effect transistor | |
| JP3275606B2 (en) | Horizontal power MOSFET |