CN111384056A

CN111384056A - Non-volatile memory and forming method thereof

Info

Publication number: CN111384056A
Application number: CN201811642635.6A
Authority: CN
Inventors: 陈耿川
Original assignee: Nexchip Semiconductor Corp
Current assignee: Nexchip Semiconductor Corp
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2020-07-07
Anticipated expiration: 2038-12-29
Also published as: CN111384056B

Abstract

The invention provides a nonvolatile memory and a forming method thereof. And forming a first tip structure on the top surface of the floating gate close to the word line to adjust the end appearance of the floating gate close to the word line, so that the end part of the floating gate close to the word line is provided with a second tip structure. When the nonvolatile memory formed based on the structure executes the erasing operation, the electric field intensity of the floating gate at the second tip structure can be enhanced, so that electrons in the floating gate can be more favorably tunneled into a word line, and the erasing efficiency of the memory is effectively improved.

Description

Non-volatile memory and forming method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a nonvolatile memory and a method for forming the same.

Background

Non-Volatile Memory (NVM) is rapidly evolving due to the push of application requirements. Various nonvolatile memory products are capable of performing operations such as data storage, data reading, and data erasing a plurality of times, and have become a type of memory element widely used in personal computers and electronic devices. Generally, a floating gate (floating gate) is disposed in a nonvolatile memory, and a Coupling Ratio (CR) between the floating gate and other set values directly affects the magnitude of a coupling voltage coupled to the floating gate, and thus the operation efficiency of the nonvolatile memory is affected.

For example, fig. 1a is a schematic structural diagram of a conventional nonvolatile memory, and the nonvolatile memory shown in fig. 1a includes a floating gate, a control gate, a drain doping region and a source doping region. Generally, when performing a programming process, it is desirable to have a higher potential on the floating gate to enhance the longitudinal electric field, thereby facilitating the attraction of electrons to the floating gate. In the programming process, the capacitive coupling effect of the drain doping region and the floating gate is mostly utilized to realize that the coupling voltage is applied to the floating gate, wherein the formula of the coupling voltage of the drain doping region coupled to the floating gate is as follows:

Vfg＝Vd x CR＝Vd x Cfd/(Cfd+Cfs)，

wherein Vfg, represents the coupling voltage on the floating gate;

vd, voltage applied on the drain doped region;

CR, which represents the coupling ratio of the floating gate and the drain doped region;

cfs, which represents a capacitance formed by overlapping the floating gate and the substrate;

cfd represents a capacitance formed by overlapping the floating gate and the drain doped region.

It follows that in order to improve the programming efficiency of a non-volatile memory, one effective means is to increase the coupling ratio CR of the floating gate and the drain doped region. However, increasing the overlap space between the floating gate and the drain doped region to increase the coupling ratio between the floating gate and the drain doped region inevitably leads to an increase in the size of the entire memory.

Based on this, it discloses another non-volatile memory in patent No. US6352895B 1. Referring specifically to fig. 1b, in the nonvolatile memory shown in fig. 1b, an ONO capacitor 10 is disposed on a floating gate FG to increase the total coupling ratio of the floating gate FG, thereby improving the programming efficiency of the nonvolatile memory.

However, although the nonvolatile memory of fig. 1b can improve the efficiency of the program operation, the nonvolatile memory of fig. 1b still requires a larger operation voltage when performing the erase operation, which is not favorable for realizing the efficient erase operation.

Disclosure of Invention

The invention aims to provide a nonvolatile memory to solve the problem of low erasing efficiency of the conventional nonvolatile memory.

To solve the above technical problem, the present invention provides a nonvolatile memory, including:

the semiconductor device comprises at least one substrate, wherein a plurality of active regions are arranged in the substrate, and a source doped region and a drain doped region are formed in the active regions;

at least one floating gate formed on the active region of the substrate, wherein the floating gate is positioned between the source doping region and the drain doping region and partially covers the source doping region, a first tip structure is formed on the top surface of the floating gate far away from the source doping region, the first tip structure points to the drain doping region, and the top surface of the floating gate, which is adjacent to the first tip structure, is connected with the side wall of the floating gate to form a second tip structure;

at least one first side wall formed above the floating gate;

at least one source line formed on the active region of the substrate, wherein the source line is located on one side of the floating gate close to the source doped region, so that the source line is electrically connected with the source doped region; and the number of the first and second groups,

and at least one word line formed on the active region of the substrate, wherein the word line is positioned between the floating gate and the drain doped region and covers the floating gate and a side wall adjacent to the first side wall and close to the drain doped region.

The invention also provides a method for forming the nonvolatile memory, which comprises the following steps:

providing a substrate, wherein the substrate is provided with a plurality of active regions;

forming a floating gate material layer on the active region of the substrate;

forming a shielding layer on the substrate, wherein the shielding layer is provided with an opening, and the opening is at least partially positioned above the floating gate material layer;

performing a local oxidation process by using the shielding layer as a mask to form a local oxide layer on the top surface of the floating gate material layer, wherein the local oxide layer extends from the opening to the position below the shielding layer and forms a first tip structure;

at least partially removing the local oxide layer in the opening to expose the floating gate material layer;

forming a first side wall on the side wall of the shielding layer, and etching the part, corresponding to the opening, of the floating gate material layer exposed from the first side wall to form a channel in the floating gate material layer, wherein the channel is exposed out of the substrate;

performing a first ion implantation process to form a source doped region in the substrate of the active region through the channel;

forming at least one source line on the substrate, the source line filling the channel to electrically connect with the source doped region;

removing the shielding layer to expose the floating gate material layer and the first tip structure of the local oxide layer, etching the exposed floating gate material layer by using the first tip structure as a mask, and enabling the remaining floating gate material layer to form at least one floating gate, wherein the top surface of the floating gate, which is bordered by the first tip structure, is connected with the side wall of the floating gate to form a second tip structure; and the number of the first and second groups,

and forming at least one word line on the side walls of the floating gate and the first side wall, and performing a second ion implantation process to form a drain doping region in the substrate of the active region, wherein the drain doping region is positioned on one side of the word line, which is far away from the floating gate.

In the nonvolatile memory provided by the invention, the first tip structure is formed on the top surface of the floating gate close to the word line to adjust the appearance of the part of the floating gate close to the word line, so that the part of the floating gate close to the word line can conform to the first tip structure to form a second tip structure, and the word line correspondingly covers the second tip structure of the floating gate. The floating gate in the invention is provided with the second tip structure on the end part close to the word line, so that the electric field intensity at the second tip structure can be enhanced when the erasing operation is carried out, and the electrons in the floating gate can be more favorably tunneled into the word line, thereby realizing the high-efficiency erasing operation.

In the forming method of the nonvolatile memory provided by the invention, the surface appearance of the floating gate material layer, which is adjacent to the first tip structure, can be adjusted by forming the shielding layer and performing the local oxidation process to form the local oxide layer with the first tip structure on the floating gate material layer; and controlling the alignment or approximate alignment of the side wall of the finally formed floating gate and the top corner of the first tip structure by using the first tip structure as a mask, so that the side wall of the formed floating gate can be connected with the top surface of the floating gate, which is bordered by the first tip structure, to form a second tip structure. In other words, in the forming method provided by the invention, the morphology of the floating gate can be effectively adjusted to enable the floating gate to have a tip structure, and meanwhile, the process difficulty can be effectively reduced based on a multi-channel self-alignment process, and the size reduction of a device is facilitated.

Furthermore, in the nonvolatile memory, the first side wall of the nonvolatile memory is provided with a dielectric layer and a conductive layer, so that coupling capacitance can be formed among the conductive layer of the first side wall, the dielectric layer and the floating gate. Therefore, when the programming operation is executed, the capacitive coupling effect between the first side wall and the floating gate can be superposed on the capacitive coupling effect between the drain doping region and the floating gate, so that the total coupling rate of the floating gate is greatly increased, and the programming efficiency of the nonvolatile memory is favorably improved.

Drawings

FIG. 1a is a schematic diagram of a conventional non-volatile memory;

FIG. 1b is a schematic diagram of another non-volatile memory according to the prior art;

FIG. 2a is a layout structure of a nonvolatile memory according to an embodiment of the present invention;

FIG. 2b is a cross-sectional view of the nonvolatile memory shown in FIG. 2a corresponding to the aa' direction;

FIG. 2c is a schematic cross-sectional view of the nonvolatile memory shown in FIG. 2a corresponding to the bb' direction;

FIG. 2d is a schematic diagram of an equivalent circuit of a nonvolatile memory according to an embodiment of the present invention;

FIG. 3 is a flow chart illustrating a method for forming a non-volatile memory according to an embodiment of the invention;

fig. 4a is a layout structure of the nonvolatile memory when the nonvolatile memory executes step S100 according to an embodiment of the present invention;

FIGS. 4b to 4c are schematic cross-sectional views of the nonvolatile memory shown in FIG. 4a corresponding to the aa 'direction and the bb' direction during the step S100;

fig. 5a is a layout structure of the nonvolatile memory when the nonvolatile memory executes step S200 according to an embodiment of the present invention;

FIGS. 5 b-5 c are schematic cross-sectional views of the nonvolatile memory in the embodiment of the present invention shown in FIG. 5a corresponding to the aa 'direction and the bb' direction during the step S200;

FIG. 6a is a layout structure of the nonvolatile memory during the step S300 according to an embodiment of the present invention;

FIG. 6b is a cross-sectional view of the nonvolatile memory shown in FIG. 6a corresponding to the aa 'direction and the bb' direction during the step S300;

FIG. 7a is a layout structure of the nonvolatile memory during the step S400 according to an embodiment of the present invention;

FIG. 7b is a cross-sectional view of the nonvolatile memory shown in FIG. 7a in the process of performing step S400 corresponding to the aa 'direction and the bb' direction;

fig. 8a is a layout structure of the nonvolatile memory when the nonvolatile memory executes step S500 in an embodiment of the present invention;

FIGS. 8b to 8c are schematic cross-sectional views of the nonvolatile memory in the embodiment of the present invention shown in FIG. 8a corresponding to the aa 'direction and the bb' direction during the step S500;

fig. 9a is a layout structure of the nonvolatile memory when the nonvolatile memory executes step S600 in an embodiment of the present invention;

FIGS. 9b to 9c are schematic cross-sectional views of the nonvolatile memory in the embodiment of the present invention shown in FIG. 8a corresponding to the aa 'direction and the bb' direction during the step S600;

fig. 10a is a layout structure of the nonvolatile memory when the nonvolatile memory executes step S700 according to an embodiment of the present invention;

FIG. 10b is a cross-sectional view of the nonvolatile memory shown in FIG. 10a in the process of performing step S700, corresponding to the aa 'direction and the bb' direction;

fig. 11a is a layout structure of the nonvolatile memory when the nonvolatile memory executes step S800 in an embodiment of the present invention;

FIG. 11b is a cross-sectional view of the nonvolatile memory in FIG. 11a during the step S800, corresponding to the aa 'direction and the bb' direction;

fig. 12a is a layout structure of the nonvolatile memory when the nonvolatile memory executes step S900 according to an embodiment of the present invention;

FIG. 12b is a cross-sectional view of the nonvolatile memory shown in FIG. 12a corresponding to the aa 'direction and the bb' direction during the step S900;

fig. 13a to 14a are layout structures of the nonvolatile memory in the step S1000 according to an embodiment of the present invention;

fig. 13b to 14b are schematic cross-sectional views of the nonvolatile memory shown in fig. 13a to 14a corresponding to the aa 'direction and the bb' direction during the step S1000.

Wherein the reference numbers are as follows:

100-a substrate;

110-source doped region; 120-drain doped region;

130-trench isolation structures; 100 a-isolation trench;

101-pad oxide layer; 102-a mask layer;

200 a-a first tip structure; 200 b-a second tip structure;

210-a layer of gate dielectric material; 211-a gate dielectric layer;

220-a layer of floating gate material; 220 a-channel;

230-a local oxide layer;

300-a first side wall;

310-a dielectric layer; 320-a conductive layer;

311-a layer of dielectric material; 321-a layer of conductive material;

400-a second side wall; 410-side wall material layer;

500-tunneling an oxide layer;

610-a third side wall; 620-fourth sidewall;

700-interlayer dielectric layer;

810-a conductive plug; 820-a metal silicide layer;

900 a-opening;

910-a buffer oxide layer; 920-a shielding layer;

930-a protective layer;

AA-active region; FG-floating gate;

SL-source line; WL-word line;

BL-bit line;

x direction-first direction; y direction-second direction

PR-photoresist layer.

Detailed Description

The non-volatile memory and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 2a is a layout structure of a nonvolatile memory according to an embodiment of the present invention, fig. 2b is a schematic cross-sectional view of the nonvolatile memory shown in fig. 2a corresponding to a direction aa ', and fig. 2c is a schematic cross-sectional view of the nonvolatile memory shown in fig. 2a corresponding to a direction bb'. As shown in fig. 2a to 2c, the nonvolatile memory includes:

at least one substrate 100, wherein a plurality of active regions AA are disposed in the substrate 100, and a source doped region 110 and a drain doped region 120 are formed in the active regions AA;

at least one floating gate FG (floating gate) formed on the active area AA of the substrate 100, the floating gate FG being located between the source doped region 110 and the drain doped region 120 and partially covering the source doped region 110, and a first tip structure 200a being formed on a top surface of the floating gate FG away from the source doped region 110, the first tip structure 200a pointing away from the source doped region, and a second tip structure 200b being formed by connecting a top surface of the floating gate FG bordering the first tip structure 200a and a sidewall of the floating gate;

at least one first sidewall 300 formed above the floating gate 200;

at least one source line SL (source line) formed on the active region AA of the substrate 100, the source line SL being specifically located on a side of the floating gate FG close to the source doped region 110, so that the source line SL is electrically connected to the source doped region 110; and the number of the first and second groups,

at least one word line WL (word line) formed on the active region AA of the substrate 100, the word line WL being specifically located between the floating gate FG and the drain doping region 120, and the word line WL further covering the floating gate FG and abutting the sidewall of the first sidewall 300 near the drain doping region. In addition, the word line WL also partially covers the drain doped region 120.

When the nonvolatile memory executes a programming operation (program), applying a starting voltage to the word line WL to control a conductive channel in a substrate area below the word line WL to be conducted by utilizing the word line WL and generating hot carriers by a horizontal strong electric field effect between the word line WL and a floating gate FG band gap; and, a voltage is also applied to the source line SL, and at this time, a coupling voltage may be provided to the floating gate FG by a capacitive coupling effect between the source doped region 110 and the floating gate FG, so that the floating gate FG has a higher potential. In the programming process, the generated hot carriers can flow to the lower part of the floating gate FG under the action of a horizontal electric field, and at the moment, the hot carriers can be injected to the floating gate FG under the action of a vertical electric field based on the high potential of the floating gate FG, so that the programming process is realized.

When the nonvolatile memory performs an Erase operation (Erase), a high voltage is applied to the word line WL, so that a large electric field strength exists between the word line WL and the floating gate FG, and electrons in the floating gate FG are tunneled into the word line WL by a F-N tunneling effect (Fowler-Nordheim effect), so as to implement an Erase process.

It should be noted that, in this embodiment, since the end portion of the floating gate FG close to the word line has the second tip structure 200b, and the vertex angle of the second tip structure 200b points to the word line WL, when performing the Erase operation (Erase), a larger electric field intensity is generated at the second tip structure 200b of the floating gate GF, which is beneficial to improving the efficiency of electron tunneling in the floating gate FG, and accordingly, the Erase efficiency of the nonvolatile memory can be effectively improved.

Specifically, the vertex angle of the first tip structure 200a points to the drain doping region 120, and the thickness dimension of the first tip structure 200a gradually increases from the vertex angle to a direction away from the vertex angle, so that the surface topography of the first tip structure 200a bordering on the floating gate FG appears as an arc-shaped protrusion. And the surface topography of the floating gate FG bordering on the first tip structure 200a is matched with the surface topography of the first tip structure 200a, so that the top surface of the floating gate FG bordering on the first tip structure 200a appears as an arc-shaped recess. In this way, the top surface of the arc-shaped recess in the floating gate FG can form the second tip structure 200b with the sidewalls of the floating gate FG connected to each other, and the top angle of the second tip structure 200b corresponds to the tip position of the first tip structure 200 a.

The first tip structure 200a may be formed by oxidizing the floating gate by a local oxidation process, for example. Specifically, the material of the floating gate FG includes, for example, polysilicon (Poly), and the material of the first tip structure 200a includes, for example, silicon oxide (SiO).

With particular reference to fig. 2b and 2c, the second tip structure 200b of the floating gate FG may protrude beyond the sidewalls of the first sidewalls 300 in a direction away from the source dopant region 110. In this embodiment, the first tip structures 200a also protrude from the sidewalls of the first sidewalls 300. It can be considered that a step is formed between the first tip structure 200a and the sidewall of the first sidewall 300, so that the word line WL correspondingly covers the step, and based on this, the word line WL can coat the second tip structure 200b corresponding to the first tip structure to a greater extent. Therefore, it is more advantageous to achieve a tunneling process of electrons in the floating gate FG when performing an erase operation.

In this embodiment, the non-volatile memory further includes a second sidewall 400, and the second sidewall 400 is formed above the first tip structure 200a and between the first sidewall 300 and the word line WL. The second sidewall spacers 400 are made of silicon oxide, for example. That is, by providing the second sidewall 400 to further isolate the word line WL from the first sidewall 300; and when the source line SL also covers the first sidewall 300, the word line WL and the source line SL may be further isolated by using the second sidewall 400.

Based on the formation of the second sidewalls 400, the second tip structures 200b of the floating gates FG may be further protruded from the sidewalls of the second sidewalls 400 in a direction away from the source dopant region, as shown in fig. 2 b. Similarly, the word line WL can cover the second tip structure 200b to a greater extent while covering the sidewall of the floating gate FG and abutting the sidewall of the second sidewall 400.

Further, the non-volatile memory device further includes a tunnel oxide layer 500, the tunnel oxide layer 500 covers the floating gate FG, abuts the sidewall of the first sidewall 300 near the drain doping region 120, and extends to the top surface of the substrate 100, and the word line WL is formed on the tunnel oxide layer 500. In this embodiment, the tunnel oxide layer 500 covers the sidewalls of the second sidewalls 400 correspondingly.

That is, the tunnel oxide layer 500 is spaced between the word line WL and the substrate 100, so that the word line WL is used to control the conduction channel in the substrate region below the word line WL to be turned on or off. And the tunneling oxide layer 500 is spaced between the word line WL and the floating gate FG, so that when an erase operation is performed, electrons in the floating gate FG tunnel through the tunneling oxide layer 500 under an F-N tunneling effect to be further injected into the word line WL.

In addition, a gate dielectric layer is formed between the floating gate FG and the substrate 100. When the nonvolatile memory carries out programming operation, hot carriers generated by a horizontal strong electric field effect between the word line WL and the floating grid FG band gap pass through the grid dielectric layer to be further injected into the floating grid FG.

With continued reference to fig. 2b and 2c, the first sidewall 300 may optionally include a dielectric layer 310 and a conductive layer 320. Wherein the dielectric layer 310 has a horizontal portion formed on a top surface of the floating gate FG and a vertical portion connected to the horizontal portion on an end portion of the horizontal portion away from the source dopant region; and, the conductive layer 320 is formed on the dielectric layer 310 such that the horizontal portion is spaced between the conductive layer 320 and the floating gate FG, and the vertical portion is spaced between the conductive layer 320 and the word line WL.

It should be noted that, because the dielectric layer 310 is spaced between the conductive layer 320 and the floating gate FG, a coupling capacitor can be formed by the conductive layer 320, the dielectric layer 310 and the floating gate FG, and a coupling voltage can be provided to the floating gate FG by a capacitive coupling effect. Specifically, when the nonvolatile memory performs a programming operation, the source doped region 110 may be used to provide a coupling voltage for the floating gate FG, and the first sidewall 300 may be further used to apply the coupling voltage to the floating gate FG, so that the floating gate FG has a higher potential, the strength of the vertical electric field in the floating gate region is enhanced, and further the hot carriers in the substrate are more effectively injected into the floating gate FG, so that the memory has a higher hot carrier collection rate, and the programming efficiency of the memory is greatly improved.

It should be further noted that in this embodiment, a second sidewall 400 is disposed between the first sidewall 300 and the word line WL, and the first sidewall 300 having a conductive layer can be prevented from affecting the word line WL at an interval of the second sidewall 400.

Further, in the first sidewall 300, the dielectric layer 310 includes, for example, one or a combination of a silicon nitride layer and a silicon oxide layer. For example, the dielectric layer 310 is an ONO stack structure of a silicon oxide layer-a silicon nitride layer-a silicon oxide layer. And, the material of the conductive layer 320 includes doped polysilicon, for example.

With continued reference to fig. 2b and 2c, the source line SL covers the sidewall of the floating gate FG near the source doped region 110, and further extends the conductive layer 320 covering the first sidewall 300 to electrically connect to the conductive layer 320. In this way, when a programming operation is performed, by applying a voltage to the source line SL, a voltage is correspondingly applied to the conductive layer 320, so that a capacitive coupling effect with the floating gate FG can be achieved, and the potential of the floating gate FG can be increased.

Further, the non-volatile memory further includes a third sidewall 610, where the third sidewall 610 is formed on a sidewall of the floating gate FG near the source doped region 110, and the third sidewall 600 is spaced between the source line SL and the floating gate FG. That is, in the present embodiment, the third sidewall 600 is used to electrically isolate the source line SL from the floating gate FG.

Furthermore, the nonvolatile memory further includes a fourth sidewall 620, and the fourth sidewall 620 is formed on an outer sidewall of the word line WL near the drain doping region 120 to prevent the outer sidewall of the word line WL from being exposed.

It can be considered that the source doped region 110, the drain doped region 120, and the floating gate FG and the word line WL between the source doped region 110 and the drain doped region 120 constitute one memory cell of the nonvolatile memory.

Referring to fig. 2a with an emphasis on fig. 2b and 2c, in the present embodiment, the active region AA extends along the first direction (Y direction), and the source doping region 110 is formed in the middle region of the active region AA, and the drain doping regions 120 are formed on both end portions of the active region AA. In the same active region AA, the floating gate FG and the word line WL are disposed between the source doped region 110 and the two drain doped regions 120, so that two memory cells may be formed.

That is, two memory cells in each of the active regions AA correspond to two word lines WL, respectively, so that the two word lines WL are used to control the two memory cells, respectively. And each active region AA corresponds to a source line SL, and the source line SL located on the active region AA is located between the two memory cells, so that two memory cells of the same active region share one source doped region 110 and one source line SL. In an alternative, the structures of two memory cells in the same active area AA are symmetrically arranged around the source line SL.

In this embodiment, a plurality of active regions AA are defined on the substrate 100, and the active regions AA are arranged in an array in a first direction (Y direction) and a second direction (X direction). For example, the plurality of active regions AA are aligned in a plurality of columns in the first direction (Y direction) and in a plurality of rows in the second direction (X direction).

The source line SL may extend along the second direction (X direction), so that the source dopants 110 in the active regions AA arranged in the same row along the second direction are all connected to the same source line SL.

The word lines WL may also extend along the second direction (X direction). Specifically, the word lines on a plurality of active regions AA arranged in the same row along the second direction may be connected to each other to constitute word lines WL extending along the second direction. In the active area array, two word lines WL extending in parallel are corresponding to one row of active areas AA.

With continued reference to fig. 2a and 2b, the nonvolatile memory further includes a bit line BL (bit line) extending along the first direction (Y direction) and electrically connected to the drain doping region 120, and the drain doping regions 120 in the active regions AA arranged on the same column are all connected to the same bit line BL.

Further, the bit line BL may be formed above the source line SL and the word line WL, and the bit line BL is isolated from the source line SL and the word line WL therebelow by an interlayer dielectric layer 700, and the drain doped region 120 in the substrate is electrically connected to the bit line BL through a conductive plug 810.

Referring specifically to fig. 2b and 2c, the interlayer dielectric layer 700 is formed on the substrate 100 and covers the drain doped region 120, the word line WL, and the source line SL. In a specific embodiment, the interlayer dielectric layer 700 covers the active area AA. And the conductive plug 810 penetrates the interlayer dielectric layer 700 at a position corresponding to the drain doping region 120 to be connected with the drain doping region 120. The bit line BL is formed on the interlayer dielectric layer 700 and covers the conductive plug 810, so as to electrically connect the bit line BL and the drain doped region 120.

Optionally, a metal silicide layer 820 may be further formed on the drain doped region 120, and the conductive plug 810 is in contact with the metal silicide 900 to lead out the drain doped region 120. By providing the metal silicide layer 820 and contacting the conductive plug 810 and the metal silicide layer 820 in this embodiment, the contact resistance between the conductive plug 810 and the drain doped region 120 can be greatly reduced, compared to making the conductive plug directly contact the drain doped region.

In addition, in this embodiment, the metal silicide layer 820 may be formed on both the word line WL and the source line SL, so that when the word line WL and the source line SL are extracted, contact resistance between a connector and the word line WL and contact resistance between a connector and the source line SL may be reduced.

Fig. 2d is a schematic diagram of an equivalent circuit of a nonvolatile memory according to an embodiment of the present invention, and as described with reference to fig. 2a and 2d, a plurality of memory cells in this embodiment are correspondingly arranged in an array. And the nonvolatile memory has a plurality of word lines (WL1/WL2/WL3 … … WLm), a plurality of source lines SL and a plurality of bit lines (BL1/BL2/BL3 … … BLn).

Wherein the plurality of memory cells arranged in the same row are connected to the same word line WL and the same source line SL to simultaneously perform row gating on the plurality of memory cells in the corresponding row using the same word line WL and the same source line SL. And connecting a plurality of memory cells arranged on the same column with the same bit line BL so as to simultaneously execute column gating on the plurality of memory cells in the corresponding column by using the same bit line BL. The memory cells with the row and column strobes are selected so that corresponding operations can be performed on the selected memory cells.

Based on the nonvolatile memory as described above, a method of forming the nonvolatile memory will be described in detail below. Fig. 3 is a schematic flow chart of a method for forming a nonvolatile memory according to an embodiment of the present invention, fig. 4a to fig. 13a are layout structures of the nonvolatile memory according to an embodiment of the present invention during a manufacturing process thereof, and fig. 4b to fig. 4c, fig. 5b to fig. 5c, fig. 6b to fig. 7b, fig. 8b to fig. 8c, fig. 9b to fig. 9c, and fig. 10b to fig. 13b are schematic cross-sectional views of the nonvolatile memory according to an embodiment of the present invention during the manufacturing process thereof corresponding to directions aa 'and bb'. The steps of forming the nonvolatile memory in this embodiment will be described in detail below with reference to the accompanying drawings.

In step S100, specifically referring to fig. 4a to 4c, a substrate 100 is provided, wherein the substrate 100 has a plurality of active regions AA. The active area AA is used to form a memory cell of a nonvolatile memory.

In this embodiment, the active areas AA extend along a first direction (Y direction), and a plurality of the active areas AA are arranged in an array in the first direction (Y direction) and a second direction (X direction). For example, a plurality of the active regions AA are arranged in a plurality of columns in the first direction (Y direction) and aligned in a plurality of rows in the second direction (X direction).

Wherein the active area AA may be defined by forming a Trench Isolation (STI) 130 in the substrate 100. In this embodiment, the method for forming the trench isolation structure 130 to define the active area AA includes the following steps.

Step one, specifically referring to fig. 4b, sequentially forming a mask layer 102 and a patterned photoresist layer PR on the substrate 100, where the patterned photoresist layer PR defines a plurality of active region patterns. The material of the mask layer 102 includes, for example, silicon nitride.

Optionally, before forming the mask layer 102, the method further includes: a Pad Oxide layer (Pad Oxide)110 is formed on the substrate 100. A subsequently formed mask layer 102 and a patterned photoresist layer PR are sequentially formed on the pad oxide layer 101.

It should be noted that when the mask layer is formed directly on the substrate 100, a large stress difference may exist between the mask layer and the substrate. In particular, when the first mask layer of silicon nitride is used, a large stress is applied to the substrate 100. Based on this, in this embodiment, the pad oxide layer 101 is disposed between the mask layer 102 and the substrate 100, so that the pad oxide layer 101 is used as a buffer layer to implement stress buffering. In addition, the pad oxide layer 101 may also be used to isolate and protect the substrate 100, so as to prevent the surface of the substrate 100 from being contaminated when the mask layer 102 is removed.

The pad oxide layer 101 may be formed by a thermal oxidation process, for example, and the material of the substrate 100 includes silicon, for example, the material of the pad oxide layer 101 includes silicon oxide. In the embodiment, the thickness of the pad oxide layer 101 is, for example, 10nm to 50 nm; the thickness of the mask layer 102 is, for example, 80nm to 200 nm.

And step two, continuing to refer to fig. 4b, sequentially etching the mask layer 102 and the substrate 100 by using the patterned photoresist layer PR as a mask, and etching the substrate 100 to a predetermined depth to form an isolation trench 100a in the substrate 100. It should be appreciated that during the etching of the substrate 100, the mask layer 102 assists the patterned photoresist layer PR in defining the isolation trench 100a with a higher pattern precision.

In this embodiment, the isolation trench 100a sequentially penetrates through the mask layer 102 and the pad oxide layer 101 and extends to a predetermined depth position of the substrate 100, and after the patterned photoresist layer is removed, the top of the isolation trench 100a extends to the top surface of the mask layer 102.

Step three, specifically referring to fig. 4c, an insulating material is filled in the isolation trench 100a to form a trench isolation structure 130. In this embodiment, the top surface of the trench isolation structure 130 is flush with the top surface of the mask layer 102 and protrudes above the top surface of the substrate 100.

Optionally, before filling the insulating material, a liner oxide layer (liner oxide) (not shown) may be formed on the inner wall of the isolation trench 100a by using a thermal oxidation process, so as to repair the etching damage generated on the inner wall of the isolation trench after the etching process. Wherein the thickness of the liner oxide layer is formed, for example, between 5nm and 20 nm. On the basis of this, an insulating material which is then filled is accordingly formed on the liner oxide layer.

And, the method of filling the insulating material in the isolation trench 100a in alignment includes, for example:

first, a High Density Plasma (HDP) process may be used to deposit the insulating material, and the deposited insulating material fills the isolation trench 100a and covers the top surface of the mask layer 102; when the insulating material is deposited by a high-density plasma process, the filling performance of the insulating material to the isolation trench 100a can be effectively improved, and the isolation performance of the finally formed trench isolation structure 130 is ensured; and the material of the insulating material includes, for example, silicon oxide (SiO);

next, a planarization process is used to remove the insulating material covering the top surface of the mask layer 102, and the insulating material filled in the isolation trench 100a may remain to form the trench isolation structure 130. The planarization process is, for example, a Chemical Mechanical Polishing (CMP) process. At this time, a plurality of active regions AA may be surrounded by the trench isolation structure 130.

In step S200, specifically referring to fig. 5a to 5c, a floating gate material layer 220 is formed on the active area AA of the substrate 100. The floating gate material layer 220 is used for further forming a floating gate of the non-volatile memory in a subsequent process.

In this embodiment, the floating gate material layer 220 may be formed in the active region AA in a self-aligned manner. Specifically, the method for forming the floating gate material layer 220 includes the following steps.

In a first step, specifically referring to fig. 5b, the mask layer and the pad oxide layer are sequentially removed to expose the top surface of the substrate in the active area AA. As described above, in the present embodiment, the substrate surface of the active area AA is recessed with respect to the trench isolation structure 130, that is, the substrate surface of the active area AA is lower than the top surface of the trench isolation structure 130 to form a groove. Therefore, in the subsequent process, a planarization process may be combined to achieve the alignment and filling of the floating gate material layer 220 in the active area AA.

For example, an ashing process may be used to remove the patterned photoresist layer, and a wet etching process may be used to remove the mask layer 102, and during the process of removing the mask layer 102, the pad oxide layer 101 may be used to protect the surface of the substrate to prevent the surface of the substrate 110 from being contaminated. Alternatively, the mask layer 102 may be removed by a Wet etching process (Wet Etch), and the etchant may include, for example, hot phosphoric acid (phosphoric acid), so as to have a larger etching selectivity for the mask layer 102 and the trench isolation structure 130 when etching the mask layer 102. And after removing the mask layer 102, continuously removing the pad oxide layer 101.

In a second step, continuing with fig. 5c, a gate dielectric material layer 210 is formed on the substrate 100. The gate dielectric material layer 210 may be formed by a thermal oxidation process, and the thickness of the gate dielectric material layer 210 is, for example, between 5nm and 15nm, and the material of the first gate dielectric material layer 210 includes, for example, one or a combination of silicon oxide and silicon oxynitride.

A third step of depositing a conductive material layer on the substrate 100, wherein the conductive material layer fills the recess of the active area AA and covers the trench isolation structure 130. The conductive material used to form the floating gate material layer includes, for example, polysilicon, and more specifically, N-doped polysilicon.

A fourth step, specifically referring to fig. 5c, a planarization process is performed to remove a portion of the conductive material layer above the trench isolation structure 130, so that the remaining conductive material layer is aligned and filled in the recess and correspondingly formed in the active area AA.

In this way, the floating gate material layer 220 is formed in the active area AA in an aligned manner, and the floating gate material layer 220 also extends along the first direction (Y direction).

In step S300, referring to fig. 6a and 6b in particular, a shielding layer 920 is formed on the substrate 100, the shielding layer 920 has an opening 900a therein, and the opening 900a is at least partially located above the floating gate material layer 220.

It is believed that the masking layer 920 is used to provide a partial masking effect for the subsequent local oxidation process to define the region where the local oxide layer is to be formed, so as to control the position of the tip of the floating gate. Specifically, the material of the shielding layer 920 includes, for example, silicon nitride (SiN), and the thickness of the shielding layer 920 is, for example, 100nm to 500 nm.

In an alternative, specifically referring to fig. 6b, before forming the shielding layer 920, the method further includes: a buffer oxide layer 910 is formed on the floating gate material layer 220. Accordingly, the shielding layer 920 is formed to at least partially cover the buffer oxide layer 910, and the opening 900a of the shielding layer 920 correspondingly exposes the buffer oxide layer 910.

It should be noted that, by forming the buffer oxide layer 910, on one hand, when performing a local oxidation process subsequently, lateral migration of oxygen-containing particles is facilitated, so that the finally formed local oxide layer can extend to the lower side of the shielding layer 920 to have a tip structure; on the other hand, the stress buffer layer can also be used as a stress buffer between the shielding layer 920 and the floating gate material layer 220, so as to prevent the shielding layer 920 from applying a large stress to the floating gate material layer 220.

Specifically, the top surface of the floating gate material layer 220 may be oxidized by a thermal oxidation process to form the buffer oxide layer 910, and more particularly, the buffer oxide layer 910 may be formed by a dry thermal oxidation process. In this embodiment, the material of the floating gate material layer 220 includes polysilicon, and the material of the buffer oxide layer 910 may correspondingly include silicon oxide. And a thickness of the buffer oxide layer 910 is, for example, 10nm or less. In addition, the material of the insulating material of the trench isolation structure 130 includes an oxide layer, so that when a thermal oxidation process is performed to form the buffer oxide layer 910, the buffer oxide layer 910 can be formed on the top surface of the floating gate material layer 220 in a self-aligned manner.

In this embodiment, the floating gate material layer 220 extends along the first direction corresponding to the active area AA and is in a stripe structure. And, the shielding layer 920 covers end regions of the active area AA (respectively covers both end portions of the floating gate material layer 220), and the opening 900a in the shielding layer 920 is located above a middle region of the active area AA, so that the upper portion of the active area AA corresponding to the middle region is exposed in the opening 900 a. That is, the opening 900a is correspondingly located above the middle region of the floating gate material layer 220.

With reference to fig. 6a, based on the active areas AA arranged in an array, a plurality of openings 900a may be formed in the shielding layer 920, the openings 900a are sequentially arranged along a first direction (Y direction), and each of the openings 900a extends along a second direction (X direction), so that the upper portions of the middle regions of the active areas AA arranged in the same row along the second direction are all exposed in the same opening 900 a.

In step S400, referring to fig. 7a and 7b in particular, a local oxidation process is performed by using the shielding layer 920 as a mask to form a local oxide layer 230 on the top surface of the floating gate material layer 220, wherein the local oxide layer 230 extends from the opening 900a to below the shielding layer 920 and constitutes a first tip structure 200 a.

Specifically, the local oxidation process includes a wet thermal oxidation process (wet thermal oxidation), for example, an oxidation process is performed using water vapor to form the local oxide layer 230 having a large thickness, and the thickness of the local oxide layer 230 is, for example, 20nm to 80 nm.

As described above, the buffer oxide layer 910 is formed on the top surface of the floating gate material layer 220, so that the provided oxygen-containing particles can longitudinally penetrate through the buffer oxide layer 910 to the surface of the floating gate material layer 220 to react with the floating gate material layer 220 when the local oxidation process is performed; moreover, the oxygen-containing particles may also laterally migrate to the lower side of the shielding layer 920 by using the buffer oxide layer 910, and undergo an oxidation reaction with the floating gate material layer 220 located below the shielding layer 920 to form the first tip structure 200 a. In this embodiment, after the local oxidation process is performed, the buffer oxide layer 910 exposed in the opening 900a is also used to form a portion of the local oxide layer 230.

It should be appreciated that when oxidizing the floating gate material layer 220 to form the local oxide layer 230 having the first tip structure 200a, the surface topography in the floating gate material layer 220 bordering the first tip structure 200a, correspondingly, coincides with the surface topography in the first tip structure 200a bordering the floating gate material layer. In this embodiment, the thickness of the first tip structure 200a gradually increases from the vertex angle to the direction away from the vertex angle, so that the surface topography of the first tip structure 200a bordering on the floating gate material layer is an arc-shaped protrusion, and the surface topography of the floating gate material layer 220 bordering on the first tip structure is an arc-shaped depression.

In step S500, referring specifically to fig. 8a and 8c, the local oxide layer 230 in the opening is at least partially removed to expose the floating gate material layer 220.

Specifically, the method of partially removing the local oxide layer to expose the floating gate material layer 220 includes the following steps.

A first step, referring to fig. 8b in particular, forming a sidewall material layer 410 on the substrate 100, wherein the sidewall material layer 410 covers the shielding layer 920 and the local oxide layer 230 exposed in the opening 900 a;

a second step, referring to fig. 8a and 8c specifically, a first etch back process is performed to form a second sidewall 400 in a self-aligned manner on the sidewall of the shielding layer 920, the bottom of the second sidewall 400 covers a portion of the local oxide layer close to the first tip structure 200a, and the exposed local oxide layer is etched continuously to further expose the floating gate material layer 220.

That is, by forming the second sidewall 400 in this embodiment, a masking effect when partially removing the local oxide layer can be achieved. Specifically, when the local oxide layer is partially removed, based on the coverage of the second sidewall 400, the first tip structure 200a in the local oxide layer can be retained in a large area. It is believed that, since the first tip structure 200a of the local oxide layer is retained, the portion of the floating gate material layer 220 corresponding to the first tip structure 200a is covered, so that the portion of the floating gate material layer corresponding to the first tip structure is prevented from being corroded in the subsequent process, and the floating gate finally formed has a better top angle.

In addition, the second sidewall spacers 400 may be used to space the first sidewall spacers and the word lines formed subsequently. And partially removing the local oxide layer to expose the floating gate material layer 220, so that the first sidewall formed subsequently can directly cover the floating gate material layer 220.

With continued reference to fig. 8a, in the present embodiment, the opening 900a of the shielding layer 920 extends along the second direction (X direction), and the second sidewall 400 is formed by self-aligning the sidewall of the shielding layer 920 exposed in the opening 900a, so that the second sidewall 400 can also follow the opening and extend along the second direction (X direction).

In step S600, referring to fig. 9a to 9c specifically, a first sidewall 300 is formed on the sidewall of the shielding layer 920 exposed to the opening 900a by using the shielding layer 920, the first sidewall 300 at least partially covers the floating gate material layer 220, and the floating gate material layer 220 is further etched corresponding to the portion of the opening 900a exposed from the first sidewall 400, so as to form a channel 220a in the floating gate material layer 220, wherein the channel 220a exposes the substrate 100. In a subsequent process, an ion implantation process may be performed through the via 220a to form a source doped region in the substrate 100.

It should be noted that the first sidewall 300 can be formed by self-aligning the shielding layer 920, which not only simplifies the process difficulty, but also facilitates the reduction of the device size. Meanwhile, the floating gate material layer 220 may be etched in an aligned manner by using the first sidewall spacers 300 formed in a self-aligned manner to expose the substrate, and then, in a subsequent process, a source doped region may be further formed in a self-aligned manner based on the floating gate material layer 220. Therefore, the process stability of the nonvolatile memory can be effectively guaranteed, and the size of the device can be further reduced.

With continued reference to fig. 9a and 9c, in an alternative embodiment, the first sidewall 300 includes a conductive layer 320 and a dielectric layer 310, the dielectric layer 310 and the conductive layer 320 are formed on the sidewall of the shielding layer 920 and cover the floating gate material layer 220, wherein the dielectric layer 310 is spaced between the conductive layer 320 and the floating gate material layer 220. That is, the conductive layer 320 may be used to constitute a coupling capacitance with the floating gate FG that is finally formed, so that a coupling voltage may be supplied to the floating gate FG. And, the dielectric layer 310 may be used to form a capacitive dielectric layer between the conductive layer 320 and the floating gate FG.

Specifically, the method for forming the first sidewall spacers 300 including the dielectric layer 310 and the conductive layer 320 includes the following steps.

First, referring specifically to fig. 9b, a dielectric material layer 311 and a conductive material layer 321 are sequentially formed on the substrate 100, and the dielectric material layer 311 and the conductive material layer 321 sequentially cover the sidewalls of the shielding layer 920 and the floating gate material layer 220 exposed in the opening 900 a.

The material of the dielectric material layer 311 includes, for example, one or a combination of silicon oxide and silicon nitride. In this embodiment, the dielectric material layer 311 includes an ONO stacked structure formed by sequentially stacking a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, wherein the thickness of the silicon nitride layer is, for example, 4nm to 8nm, and the thicknesses of the silicon oxide layers on both sides of the silicon nitride layer are, for example, 3nm to 7 nm. Further, the material of the conductive material layer 321 includes, for example, N-doped polysilicon, and the thickness dimension thereof is, for example, between 80nm and 250 nm.

Then, a second etching back process is performed to form the conductive layer 320 in a self-aligned manner, expose the dielectric material layer, continue to etch the exposed dielectric material layer, and retain a portion of the dielectric material layer between the conductive layer 320 and the shielding layer 920 and a portion of the dielectric material layer between the conductive layer 320 and the floating gate material layer 220, so as to form the dielectric layer 310.

In this embodiment, the second sidewall 400 is further formed on the sidewall of the shielding layer 920, and the first sidewall 300 is correspondingly formed on the second sidewall 400. And, the first side wall 300 is extended along the second direction in sequence to the opening.

In this embodiment, the first sidewall 300 includes a conductive layer 320. However, it should be appreciated that in other embodiments, the material of the first sidewall spacers may only include an insulating material (e.g., silicon nitride, etc.), and thus only serve to isolate and protect the finally formed floating gate.

With continued reference to fig. 9c, after the second etch-back process is performed and the floating gate material layer is exposed, the exposed floating gate material layer may be further etched to form the channel 220a in the floating gate material layer 220. It can be understood that after the conductive material layer and the dielectric material layer are sequentially etched to form the first sidewall spacers 300, the exposed floating gate material layer can be aligned and etched under the mask effect of the first sidewall spacers 300. Of course, it should be appreciated that the layer of conductive material of the first sidewall spacers and the layer of floating gate material may be etched separately in different etching steps.

Further, a gate dielectric material layer 210 is formed on the substrate 100, so that when the floating gate material layer 220 is etched to form the channel 220a, the gate dielectric material layer 210 may be further etched, so that the channel 220a also penetrates through the gate dielectric material layer and exposes the surface of the substrate 100.

In addition, as described above, the opening 900a of the shielding layer 920 exposes the middle region of the floating gate material layer 220 in the middle region of the floating gate material layer 220, so that the middle region of the floating gate material layer 220 is exposed from the first sidewall 300 when the first sidewall 300 is formed. Therefore, when the exposed floating gate material layer 220 is etched to form the channel 220a, the floating gate material layer 220 is separated from the middle region to form two separated floating gate material layers 220, the formed channel 220a is correspondingly located between the two separated floating gate material layers 220, and the two separated floating gate material layers 220 are used for forming two memory cells in the same active area AA in a subsequent process.

In step S700, referring specifically to fig. 10a and 10b, a first ion implantation process is performed to form a source doped region 110 in the substrate 100 of the active area AA through the via 220 a. That is, the source doped region 110 may be formed on one side of the floating gate material layer 220 in an aligned manner under the masking of the first sidewall 300, and a thermal annealing process may be combined to extend the finally formed source doped region 110 to a position below the floating gate material layer 220.

In this embodiment, in the same active region AA, the channel 220a corresponds to a middle region of the active region AA and is located between two divided floating gate material layers 220, and accordingly, the source doped region 110 is located between two divided floating gate material layers 220.

Specifically, the first ion implantation process is, for example, performing N-type ion implantation on the exposed active region substrate. In the present embodiment, the implanted ions include, for example, one or a combination of arsenic (As) and phosphorus (P).

Further, after the ion implantation through the channel 220a, the method further includes: a thermal annealing process is performed to activate the implanted ions and diffuse the implanted ions to form the source doped region 110, the source doped region 110 extending to below the floating gate material layer 220.

With continuing reference to fig. 10a and 10b, after forming the source dopant region 110, further comprising: a third sidewall spacer 610 is formed on the sidewall of the floating gate material layer 220 exposed in the channel 220 a. The third sidewall spacers 610 may be used to cover sidewalls of the floating gate material layer 220 exposed in the channel 220a, so as to prevent the floating gate material layer 220 from being exposed, and thus, the floating gate material layer 220 and a source line formed later may be isolated from each other.

The third spacers 610 may be made of, for example, one or a combination of silicon oxide and silicon nitride. And the width dimension of the third sidewall 610 in parallel to the substrate surface is, for example, 10nm to 30 nm.

In step S800, referring specifically to fig. 11a and 11b, at least one source line SL is formed on the substrate 100, and the source line SL fills the channel 220a to electrically connect to the source doped region 110.

In this embodiment, the source line SL is partially formed between two separated floating gate material layers 220 in the same active area AA. And the third sidewall 610 is further spaced between the source line SL and the floating gate material layer 220.

With continued reference to fig. 11b, the source line SL fills the via 220a and further fills the opening 900a to cover the conductive layer 320 of the first sidewall 300. Since the source line SL is connected to the conductive layer 320, a voltage can be applied to the conductive layer 320 in the first sidewall 300 through the source line SL, and thus, the potential of the finally formed floating gate can be increased due to the capacitive coupling effect.

In addition, referring to fig. 11a and 11b, the source line SL can be aligned to fill the opening 900a and extend along the second direction (X direction) along the opening, and accordingly, the source doping regions 110 in the plurality of active regions AA arranged on the same row along the second direction are all connected to the same source line SL.

Specifically, the method for forming the source lines SL includes, for example:

first, a source conductive material layer is deposited on the substrate 100, the source conductive material layer fills the channel 220 and the opening 900a and covers the top surface of the shielding layer 920; the material of the source conductive material layer comprises polysilicon, and further can be N-doped polysilicon;

then, a planarization process is performed to remove the portion of the source conductive material layer covering the top surface of the shielding layer and to leave the portion filled in the opening to form the source line SL. The planarization process is, for example, a Chemical Mechanical Polishing (CMP) process or an etch back (etch back) process.

Of course, in an alternative scheme, the source lines SL may be further etched after the planarization process is performed to reduce the height of the source lines SL so that the top surfaces of the source lines SL are lower than the top surface of the shielding layer 920.

Referring to fig. 11b, in this embodiment, after forming the source lines SL, the method further includes: a protective layer 930 is formed on the surface of the source line SL. The protection layer 930 covers the exposed surface of the source line SL, so that the source line SL is prevented from being exposed to a subsequent process.

The protection layer 930 may be formed by a thermal oxidation process, for example. In this embodiment, the material of the shielding layer 920 includes silicon nitride, and the material of the source line SL includes polysilicon, so that the protection layer 930 can be formed on the source line SL in alignment by a thermal oxidation process. The material of the protective layer 930 includes silicon oxide, and the thickness thereof is, for example, 10nm to 30 nm.

In step S900, referring to fig. 12a to 12b specifically, the shielding layer 920 is removed to expose the floating gate material layer and the first tip structure 200a of the local oxide layer, and the floating gate material layer is etched by using the first tip structure 200a as a mask to remove the exposed floating gate material layer, so that the remaining floating gate material layer forms a floating gate FG, and a top surface of the floating gate FG bordering on the first tip structure 200a and a sidewall of the floating gate FG form a second tip structure 200 b.

As described above, the first tip structure 200a of the local oxide layer extends to the lower side of the shielding layer 920, so that the first tip structure 200a is exposed after the shielding layer is removed. And, in this embodiment, the second sidewall 400 is further formed between the first sidewall 300 and the shielding layer 920, so that after the shielding layer 920 is removed, the sidewall of the second sidewall 400 is also exposed. And, the first tip structure 200a further protrudes from the sidewall of the second sidewall 400 in a direction away from the source doped region 110.

Specifically, the shielding layer may be removed by a wet etching process (wet etch), and an etchant of the wet etching process includes, for example, phosphoric acid. It should be noted that, in the process of etching the shielding layer, the source lines SL are covered by the protective layer 930, and thus can be prevented from being damaged by etching.

As shown in fig. 11b, after removing the shielding layer, the buffer oxide layer 910 formed on the floating gate material layer 220 is exposed, and the exposed buffer oxide layer 910 is further removed to expose the floating gate material layer 220. In this embodiment, the material of the protection layer 930 includes silicon oxide, so that the protection layer 930 is partially consumed when the buffer oxide layer 910 is removed, and at this time, a part of the protection layer 930 remains on the source lines SL.

With continued reference to fig. 12a and 12b, under the mask action of the first tip structure 200a, the second sidewall 400 and the protection layer 930, the floating gate material layer is etched to remove the exposed floating gate material layer, and the remaining floating gate material layer constitutes a floating gate FG. In the floating gate FG, the exposed sidewalls and the top surfaces of the interconnected arc-shaped recesses constitute a second tip structure 200 b.

Further, after the floating gate material layer is partially removed to form the floating gate FG, the gate dielectric material layer is exposed, and the gate dielectric material layer is continuously etched to form a gate dielectric layer 211 under the floating gate FG and expose the substrate 100.

In this embodiment, the gate dielectric material layer includes silicon oxide, so that the protective layer 930 may be consumed when the gate dielectric material layer is etched. Optionally, in the etching process for removing the gate dielectric material layer, the protective layer 930 may be further removed to expose the source line SL, so as to facilitate subsequent leading out of the source line SL.

In step S1000, specifically referring to fig. 13a to 14a and fig. 13b to 14b, at least one word line WL is formed on the floating gate FG and the sidewall of the first sidewall 300, and a second ion implantation process is performed to form a drain doped region 120 in the substrate of the active region AA, wherein the drain doped region 120 is located on a side of the word line WL away from the floating gate FG. The drain doped region 120 may further extend to below the word line WL.

Referring specifically to fig. 13a and 13b, before forming the word line WL, the method further includes: a tunnel oxide layer 500 is formed on the substrate 100, wherein the tunnel oxide layer 500 covers the floating gate FG and the sidewalls of the first sidewalls 300 away from the source doped regions 110, and extends to the top surface of the substrate 100. In this embodiment, the tunnel oxide layer 500 covers the sidewalls of the second sidewalls 400.

In this embodiment, the tunneling oxide layer 500 is, for example, an oxide layer doped with nitrogen. Specifically, the forming method of the tunnel oxide layer 500 includes: firstly, forming an oxide layer by utilizing a high-temperature oxidation process; then, an annealing process is performed in a nitrogen-containing atmosphere to form an oxide layer doped with nitrogen. Wherein the nitrogen-containing atmosphere is, for example, nitrogen monoxide (NO) or dinitrogen monoxide (N)₂O) gas.

After forming tunnel oxide layer 500, word line WL may be self-aligned on tunnel oxide layer 500 using floating gate FG and sidewalls of second sidewall 400. In this embodiment, the word lines WL may respectively extend along the second direction (X direction) following the second sidewalls 400. It is to be understood that the finally formed plurality of memory cells in the plurality of active regions AA arranged in the same row along the second direction may control the conductive channels of the plurality of memory cells using the same word line.

Referring next to fig. 14a and 14b, after the word line WL is formed, a second ion implantation process may be performed under the shadow of the word line WL to implant dopant ions to a side of the word line WL away from the floating gate FG. Of course, a thermal annealing process may be further combined to activate the implanted ions and diffuse the implanted ions to the lower portion of the word line WL to form the drain doped region 120.

In addition, after the word line WL is formed, a fourth sidewall 620 may be formed on the sidewall of the word line WL by using the sidewall of the word line WL in a self-aligned manner, so as to cover the sidewall of the word line WL with the fourth sidewall 620.

In the subsequent process, the method for forming the nonvolatile memory further comprises the following steps:

a plurality of bit lines BL are formed on the substrate 100, and the bit lines BL are electrically connected to the drain doping regions 120.

Referring to fig. 2a and 2b specifically, the method for forming the bit line BL includes:

firstly, forming an interlayer dielectric layer 700 on the substrate 100, wherein the interlayer dielectric layer 700 covers the drain doping region 120; and, the interlayer dielectric layer 700 also covers the word lines WL and the source lines SL;

then, forming a conductive plug 810 in the interlayer dielectric layer 700, wherein the conductive plug 810 penetrates through the interlayer dielectric layer 700 to be 120-connected with the drain doping region;

next, the bit line BL is formed on the interlayer dielectric layer 700, and the bit line BL covers the conductive plug 810 to be electrically connected to the conductive plug 810, so that the bit line BL is electrically connected to the drain doped region 120 through the conductive plug 810.

In this embodiment, the bit line BL extends along the first direction (Y direction), so that two drain doping regions 120 in the same active region AA are connected to the same bit line BL. And the drain doped regions 120 in the plurality of active regions arranged on the same column along the first direction are all connected to the same bit line BL.

In an optional scheme, before forming the interlayer dielectric layer 700, the method further includes: a metal silicide layer 820 is formed on the drain doped region 120. The conductive plugs 810 formed subsequently are connected to the metal silicide layer 820, respectively, to reduce the contact resistance between the conductive plugs 810 and the drain doped regions 120.

Wherein the metal silicide layer 820 may be formed using a Self-Aligned silicide process (Self-Aligned silicide). In this embodiment, when the metal silicide layer 820 is formed, the metal silicide layer 820 may be formed on both the word line WL and the source line SL as well as the drain doped region 120.

In summary, in the nonvolatile memory provided by the present invention, the first tip structure is formed on the top surface of the floating gate close to the word line, so that the end of the floating gate close to the word line correspondingly constitutes the second tip structure. Therefore, when the erasing operation is executed, the electric field intensity of the floating gate at the second tip structure can be enhanced, the tunneling process of electrons can be more favorably realized, and the erasing efficiency of the nonvolatile memory is greatly improved.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A non-volatile memory, comprising:

at least one floating gate formed on the active region of the substrate, wherein the floating gate is positioned between the source doped region and the drain doped region and partially covers the source doped region, a first tip structure is formed on the top surface of the floating gate close to the drain doped region, the first tip structure points to the drain doped region, and the top surface of the floating gate, which is adjacent to the first tip structure, is connected with the side wall of the floating gate to form a second tip structure;

at least one first side wall formed above the floating gate;

2. The non-volatile memory of claim 1, wherein the second tip structure of the floating gate protrudes beyond sidewalls of the first sidewall in a direction away from the source dopant region.

3. The non-volatile memory of claim 1, wherein a top corner of the first tip structure points toward the drain doped region, and a thickness dimension of the first tip structure gradually increases from the top corner to a direction away from the top corner, such that a surface topography of the first tip structure bordering the floating gate is an arc-shaped protrusion, and a top surface topography of the floating gate bordering the first tip structure is an arc-shaped depression.

4. The non-volatile memory of claim 1, wherein the first sidewall comprises a dielectric layer and a conductive layer; wherein the content of the first and second substances,

the dielectric layer is provided with a horizontal part and a vertical part, the horizontal part is formed on the top surface of the floating gate, and the vertical part is connected with the horizontal part on the end part of the horizontal part close to the drain doping region;

the conductive layer is formed on the dielectric layer such that the horizontal portion is spaced between the conductive layer and the floating gate and the vertical portion is spaced between the conductive layer and the word line.

5. The non-volatile memory of claim 4, wherein the source line further covers the conductive layer of the first sidewall and is electrically connected to the conductive layer.

6. The non-volatile memory as claimed in claim 4, wherein the material of the dielectric layer comprises one or a combination of silicon nitride and silicon oxide.

7. The non-volatile memory of claim 1, further comprising:

and the second side wall is formed above the first tip end structure and positioned between the first side wall and the word line.

8. The non-volatile memory of claim 7, wherein the second tip structure of the floating gate protrudes beyond sidewalls of the second sidewalls toward the drain dopant region.

9. The non-volatile memory of claim 1, further comprising:

and the third side wall is formed on the side wall of the floating gate close to the source doped region, and the third side wall is arranged between the source line and the floating gate at intervals.

10. The non-volatile memory of claim 1, further comprising:

at least one tunnel oxide layer covering the floating gate and the sidewall of the first sidewall near the drain doping region and extending to the top surface of the substrate, and the word line is formed on the tunnel oxide layer.

11. The nonvolatile memory of claim 1, wherein the active region extends along a first direction, and a middle region of the active region is formed with the source doping region, the drain doping region is formed on both end portions of the active region, and on the same active region, the floating gate and the word line are provided between the source doping region and both the drain doping regions to constitute two memory cells, respectively, and the source line is provided between the two memory cells.

12. The nonvolatile memory as in claim 11, wherein a plurality of the active regions are arranged in an array in a first direction and a second direction;

the source line extends along the second direction, so that the source doped regions in the active regions arranged on the same row along the second direction are all electrically connected to the same source line; and the word lines on the plurality of active regions arranged on the same row along a second direction are connected to each other to constitute word lines extending along the second direction;

the nonvolatile memory further comprises at least one bit line, wherein the bit line extends along the first direction and is electrically connected with the drain doping region, and the drain doping regions in the active regions arranged on the same column along the first direction are all electrically connected with the same bit line.

13. A method for forming a non-volatile memory, comprising:

forming a floating gate material layer on the active region of the substrate;

14. The method of claim 13, further comprising, after forming the floating gate material layer and before forming the masking layer: forming a buffer oxide layer on the floating gate material layer;

and when the shielding layer is formed, the shielding layer is formed on the buffer oxide layer, and the opening exposes the buffer oxide layer.

15. The method of claim 13, wherein partially removing the local oxide layer comprises:

forming a side wall material layer on the substrate, wherein the side wall material layer covers the side wall of the shielding layer and the local oxide layer exposed in the opening; and the number of the first and second groups,

and performing a first back etching process to form a second side wall on the side wall of the shielding layer in a self-alignment manner, wherein the bottom of the second side wall covers the part, close to the first tip structure, of the local oxide layer, and continuously etching the exposed local oxide layer to further expose the floating gate material layer.

16. The method for forming the nonvolatile memory according to claim 13, wherein the method for forming the first sidewall spacers comprises:

sequentially forming a dielectric material layer and a conductive material layer on the substrate, wherein the dielectric material layer and the conductive material layer sequentially cover the side wall of the shielding layer and the floating gate material layer corresponding to the opening; and the number of the first and second groups,

and performing a second etching process to form a conductive layer in a self-alignment manner, continuously etching the exposed dielectric material layer, and reserving a part of the dielectric material layer between the conductive layer and the shielding layer and a part of the dielectric material layer between the conductive layer and the floating gate material layer to form a dielectric layer, wherein the dielectric layer and the conductive layer form the first side wall.

17. The method of forming a nonvolatile memory as claimed in claim 13, further comprising, before forming the source line: forming a third side wall on the side wall of the floating gate material layer exposed in the channel;

and when the source line is formed, the third side wall is arranged between the source line and the floating gate material layer in an interval mode.

18. The method of claim 13, further comprising, after forming the floating gate and before forming the word line:

forming a tunnel oxide layer on the substrate, wherein the tunnel oxide layer covers the floating gate and the sidewall of the first sidewall far away from the source doped region, and extends to cover the top surface of the substrate.

19. The method of claim 13, wherein the active regions extend along a first direction, and a plurality of the active regions are arranged in an array in the first direction and a second direction.

20. The method according to claim 19, wherein the opening of the shielding layer extends along the second direction so that the openings are exposed over a plurality of active regions arranged in a same row along the second direction;

when the first side wall is formed by utilizing the shielding layer, the first side wall follows the opening and extends along the second direction;

when the source line is formed, the source line also fills the opening and extends along the second direction along the opening in a following manner; and the number of the first and second groups,

when the word lines are formed, the word lines follow the first side walls and extend along the second direction.