CN110600474A - Flash memory device and method of manufacturing the same - Google Patents
Flash memory device and method of manufacturing the same Download PDFInfo
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- CN110600474A CN110600474A CN201910872062.4A CN201910872062A CN110600474A CN 110600474 A CN110600474 A CN 110600474A CN 201910872062 A CN201910872062 A CN 201910872062A CN 110600474 A CN110600474 A CN 110600474A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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Abstract
The invention provides a flash memory device and a manufacturing method thereof, wherein the manufacturing method of the flash memory device comprises the following steps: providing a substrate, and forming a first grid stacking structure and a second grid stacking structure which are adjacent to each other on the substrate, wherein the interval between the first grid stacking structure and the second grid stacking structure is a first groove; forming a polysilicon layer in the first trench, wherein the polysilicon layer does not fill the first trench to expose the sidewall of the first trench with partial height; forming an inner side wall on the exposed side wall of the first groove; and etching the polycrystalline silicon layer in the first groove by taking the inner side wall as a mask so as to form a word line grid. The technical scheme of the invention ensures that the widths of the adjacent word line grids are the same or nearly the same, reduces the risk of short circuit and improves the performance of the flash memory device.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing, and more particularly, to a flash memory device and a method for manufacturing the same.
Background
The split gate flash memory has the advantages that the operations of storing, reading, erasing and the like of data can be carried out for many times, and the stored data can not disappear after power failure, and the split gate flash memory becomes a non-volatile memory element widely adopted by personal computers and electronic equipment.
In the manufacturing process of the split-gate flash memory device, the polysilicon in the word line region between the gate structures (including the floating gate and the control gate, etc.) needs to be etched through a photolithography process to form the word line gate. In the photolithography process, the mask pattern and the gate structure need to be aligned, but in the actual operation process, a shift between the mask pattern and the gate structure is easily caused, that is, an overlay shift (overlay shift) of photolithography occurs, so that the width difference of each word line gate formed after etching is large, and a serious asymmetric condition is presented. The asymmetry of each word line gate can cause the problems of short circuit of the conductive contact plug of the subsequent bit line and the like, thereby affecting the performance of the flash memory device.
Therefore, how to improve the manufacturing process of the conventional split gate flash memory device to make the widths of the adjacent word line grids the same, so as to improve the performance of the flash memory device is a problem that needs to be solved at present.
Disclosure of Invention
The invention aims to provide a flash memory device and a manufacturing method thereof, which enable the widths of adjacent word line grids to be the same or close to the same, further reduce the risk of short circuit and improve the performance of the flash memory device.
To achieve the above object, the present invention provides a method of manufacturing a flash memory device, comprising:
providing a substrate, wherein a first grid stacking structure and a second grid stacking structure which are adjacent to each other are formed on the substrate, and the interval between the first grid stacking structure and the second grid stacking structure is a first groove;
forming a polysilicon layer in the first trench, wherein the polysilicon layer does not fill the first trench and exposes the side wall of the first trench with partial height;
forming an inner side wall on the exposed side wall of the first groove; and the number of the first and second groups,
and etching the polycrystalline silicon layer in the first groove by taking the inner side wall as a mask so as to form a word line grid.
Optionally, the step of forming the inner sidewall spacers on the exposed sidewalls of the first trench includes:
forming a sacrificial layer to cover the polysilicon layer and the first and second gate stack structures, wherein the sacrificial layer fills the first trench;
forming a groove in the sacrificial layer, wherein the groove is located at the middle position above the first groove; and the number of the first and second groups,
and etching the sacrificial layer along the groove by adopting a side wall etching process until the upper surface of the polycrystalline silicon layer in the first groove is exposed so as to form the inner side wall.
Optionally, the groove is formed by using photolithography and etching processes.
Optionally, the groove is formed by controlling the process parameters for forming the sacrificial layer.
Optionally, before forming the polysilicon layer in the first trench, a common source or a common drain is formed in the substrate at the bottom of the first trench.
Optionally, after the polysilicon layer is formed in the first trench and before the inner sidewall is formed on the exposed sidewall of the first trench, ion implantation is performed on the polysilicon layer.
Optionally, a third gate stack structure is provided adjacent to the second gate stack structure, a space between the second and third gate stack structures is a second trench, and an erase gate is formed in the second trench.
Optionally, the method further includes: forming an interlayer dielectric layer on the substrate, and forming a conductive contact plug in the interlayer dielectric layer in the first trench, the conductive contact plug being located at the middle of the first trench.
The present invention also provides a flash memory device, including a substrate, a first gate stack structure and a second gate stack structure adjacent to each other on the substrate, wherein a space between the first and second gate stack structures is a first trench, and further including:
word line gates on sidewalls of the first and second gate stack structures in the first trench, the word line gates having the same width.
Optionally, the flash memory device further includes: a third gate stack adjacent to the second gate stack, the second and third gate stacks spaced apart by a second trench having an erase gate formed therein.
Optionally, the flash memory device further includes: a common source or a common drain in the substrate at the bottom of the first trench.
Optionally, the flash memory device further includes: the substrate comprises an interlayer dielectric layer positioned on the substrate and a conductive contact plug positioned in the interlayer dielectric layer in the first groove, wherein the conductive contact plug is positioned in the middle of the first groove.
Optionally, the first, second and third gate stack structures include a gate structure and a gate sidewall covering a sidewall of the gate structure, and the gate structure sequentially includes a floating gate layer, an inter-gate dielectric layer, a control gate layer and a hard mask layer from bottom to top.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the manufacturing method of the flash memory device of the invention forms a polysilicon layer in a first groove between a first grid stacking structure and a second grid stacking structure which are adjacent on a substrate, and the polysilicon layer does not fill the first groove; forming an inner side wall on the exposed side wall of the first groove; and etching the polysilicon layer in the first trench by using the inner side wall as a mask to form word line gates with the same or nearly the same width, so that the risk of short circuit is reduced, and the performance of the flash memory device is improved.
2. According to the flash memory device, the adjacent first grid stacking structure and the second grid stacking structure which are positioned on the substrate, and the word line grids which are positioned on the side wall of the first groove between the first grid stacking structure and the second grid stacking structure and have the same width or are close to the same width are arranged, so that the risk of short circuit is reduced, and the performance of the flash memory device is improved.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a flash memory device according to an embodiment of the present invention;
fig. 2a to 2h are device diagrams in a method of manufacturing the flash memory device shown in fig. 1.
Wherein, the reference numbers of the attached drawings 1-2 h are explained as follows:
10-a substrate; 101-common source; 102-common drain; 103-a first gate stack structure; 104-a second gate stack structure; 105-a third gate stack structure; 11-a gate structure; 111-floating gate layer; 112-an inter-gate dielectric layer; 113-a control gate layer; 114-a hard mask layer; 12-a gate spacer; 121-a first oxide layer; 122-a nitride layer; 123-a second oxide layer; 131-a first trench; 132-a second trench; 14-a polysilicon layer; 15-a sacrificial layer; 151-grooves; 16-inner side wall; 17-etching the barrier layer; an 18-word wire grid; 19-an erase gate; 20-interlayer dielectric layer; 21-conductive contact plug.
Detailed Description
To make the objects, advantages and features of the present invention more clear, the following describes the flash memory device and the manufacturing method thereof in detail with reference to fig. 1-2 h. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a flash memory device, and referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the present invention, where the method for manufacturing a flash memory device includes:
step S1, providing a substrate, wherein a first gate stack structure and a second gate stack structure which are adjacent to each other are formed on the substrate, and the interval between the first gate stack structure and the second gate stack structure is a first groove;
step S2, forming a polysilicon layer in the first trench, wherein the polysilicon layer does not fill the first trench to expose a sidewall of the first trench with a partial height;
step S3, forming an inner side wall on the exposed side wall of the first groove;
and step S4, etching the polysilicon layer in the first groove by taking the inner side wall as a mask to form a word line grid.
The method for manufacturing the flash memory device according to the present embodiment is described in more detail with reference to fig. 2a to 2h, where fig. 2a to 2h are schematic device diagrams in the method for manufacturing the flash memory device shown in fig. 1, and fig. 2a to 2h are schematic longitudinal cross-sectional views of the device.
Referring to fig. 2a to 2b, according to step S1, a substrate 10 is provided, and a first gate stack structure 103 and a second gate stack structure 104 are formed on the substrate 10, wherein the first gate stack structure 103 and the second gate stack structure 104 are adjacent to each other, and a space between the first gate stack structure 103 and the second gate stack structure 104 is a first trench 131. As shown in fig. 2a, each of the first gate stack structure 103 and the second gate stack structure 104 includes a gate structure 11 and a gate sidewall 12 covering a sidewall of the gate structure 11, the gate structure 11 sequentially includes, from bottom to top, a floating gate layer 111, an inter-gate dielectric layer 112, a control gate layer 113, and a hard mask layer 114, and the gate sidewall 12 may sequentially include, from inside to outside, a first oxide layer 121, a nitride layer 122, and a second oxide layer 123 from the sidewall of the gate structure 11; and a tunnel oxide layer (not shown) is formed between the substrate 10 and the first gate stack structure 103 and the second gate stack structure 104. The first gate stack structure 103 and the second gate stack structure 104 may be formed by the following processes: firstly, depositing materials of the floating gate layer 111, the inter-gate dielectric layer 112, the control gate layer 113 and the hard mask layer 114 on the tunneling oxide layer and the substrate 10 in sequence; then, sequentially etching the materials of the hard mask layer 114, the control gate layer 113, the inter-gate dielectric layer 112 and the floating gate layer 111 to form the gate structure 11; next, forming the first oxide layer 121 on the sidewall of the gate structure 11 by using a rapid thermal oxidation process; next, the nitride layer 122 is formed on the sidewall of the first oxide layer 121; next, the second oxide layers 123 are formed on the sidewalls of the nitride layers 122, and a space between two adjacent second oxide layers 123 is the first trench 131. The first oxide layer 121 and the second oxide layer 123 may be made of silicon oxide, and the nitride layer 122 may be made of silicon nitride. In addition, the gate sidewall spacer 12 may also only include the first oxide layer 121 and the nitride layer 122.
Before the polysilicon layer 14 is formed in the first trench 131, a common source or a common drain may be formed in the substrate 10 at the bottom of the first trench 131. As shown in fig. 2b, the substrate 10 is ion-implanted to form a common drain 102 in the substrate 10 at the bottom of the first trench 131, or a common source in the substrate 10 at the bottom of the first trench 131.
Referring to fig. 2c, according to step S2, a polysilicon layer 14 is formed in the first trench 131, and the polysilicon layer 14 does not fill the first trench 131 to expose a sidewall of a partial height of the first trench 131. As shown in fig. 2c, the top surface of the polysilicon layer 14 is lower than the top surfaces of the first gate stack structure 103 and the second gate stack structure 104.
After the polysilicon layer 14 is formed in the first trench 131 and before the inner sidewall 16 is subsequently formed on the exposed sidewall of the first trench 131, ion implantation is further performed on the polysilicon layer 14 to reduce the resistance of the polysilicon layer 14 and reduce the electron depletion of the polysilicon layer 14. The type of the implanted ions may be N-type or P-type, the N-type ion species may include boron, indium, gallium, or the like, and the P-type ion species may include phosphorus, arsenic, antimony, or the like.
Referring to fig. 2d to 2e, according to step S3, inner spacers 16 are formed on the exposed sidewalls of the first trenches 131. The step of forming the inner sidewall spacers 16 on the exposed sidewalls of the first trenches 131 includes: firstly, forming a sacrificial layer 15 to cover the polysilicon layer 14, the first gate stack structure 103 and the second gate stack structure 104, and filling the first trench 131 with the sacrificial layer 15; then, forming a groove 151 on top of the sacrificial layer 15, the groove 151 being located at an intermediate position above or near the intermediate position of the first trench 131; next, a sidewall etching process is used to etch the sacrificial layer 15 along the groove 151 until the upper surface of the polysilicon layer 14 in the first trench 131 is exposed, so as to form the inner sidewall 16.
Wherein the top of the sacrificial layer 15 in the first trench 131 is unsealed by controlling the process parameters (e.g. deposition time, deposition rate, etc.) when forming the sacrificial layer 15, so as to form the groove 151 on the top of the sacrificial layer 15 in the first trench 131, and the groove 151 is located at or near the middle of the top of the sacrificial layer 15 in the first trench 131. Then, the sacrificial layer 15 at the bottom of the groove 151 is directly removed by using a self-aligned process, as shown in fig. 2e, so as to expose the polysilicon layer 14 at the bottom of the groove 151, and simultaneously, the inner sidewall 16 is also formed, and since the groove 151 is located at the middle position or the position close to the middle position of the top of the sacrificial layer 15 in the first trench 131, the widths of the formed inner sidewalls 16 are the same or nearly the same.
In another embodiment, after the sacrificial layer 15 covering the polysilicon layer 14, the first gate stack structure 103 and the second gate stack structure 104 is formed, the sacrificial layer 15 at or near the middle of the first trench 131 is removed by using photolithography and etching processes to form the groove 151, so that the widths of the two adjacent inner sidewalls 16 formed in the first trench 131 are the same or nearly the same.
The material of the inner sidewall 16 (i.e., the material of the sacrificial layer 15) may include at least one of silicon dioxide, silicon oxynitride, ethyl orthosilicate, borosilicate glass, phosphosilicate glass, and borophosphosilicate glass, and the sacrificial layer 15 may be formed by a deposition process, so that the process for forming the sacrificial layer 15 is relatively simple because the deposition rate of the sacrificial layer 15 is fast.
Referring to fig. 2f to 2g, in step S4, the polysilicon layer 14 in the first trench 131 is etched using the inner sidewall spacers 16 as masks to form word line gates 18 having the same or nearly the same width, that is, the two word line gates 18 in the first trench 131 have the same or nearly the same width. The step of forming the word line gate 18 having the same or nearly the same width includes: first, using the inner spacers 16 as a mask, etching the polysilicon layer 14 in the first trench 131 to expose the top surface of the substrate 10, as shown in fig. 2f, exposing the top surface of the common drain 102 in the substrate 10; next, the inner sidewall 16 is removed, and the polysilicon layer 14 in the first trench 131 forms the word line gate 18, as shown in fig. 2 g. According to the description of the step S3, since the two adjacent inner side walls 16 in the first trench 131 have the same or nearly the same width, the two adjacent word lines 18 etched by using the inner side walls 16 as masks also have the same or nearly the same width. According to the invention, the polycrystalline silicon layer 14 is etched to form the word line grating 18 without adopting a method of aligning a photomask pattern with a grid structure, so that the situation that the adjacent word line gratings 18 are different in width obviously, namely the situation of obvious asymmetry, caused by large alignment offset between the photomask pattern and the grid structure can not occur.
The methods of etching the sacrificial layer 15 and etching the polysilicon layer 14 in the first trench 131 may be both dry etching, and different etching gases are used. The same etching gas may have a high selection ratio for the material of the sacrificial layer 15 and the material of the polysilicon layer 14, so that when the polysilicon layer 14 in the first trench 131 is etched, the inner sidewall 16 may not be etched or may be slightly etched, and the inner sidewall 16 may serve as a mask for etching the polysilicon layer 14. In addition, the method for removing the inner side wall 16 may also be wet etching, and the inner side wall 16 may be removed by cleaning with a hydrofluoric acid solution.
In addition, the method of manufacturing the flash memory device further includes: an erase gate 19 is formed. A third gate stack structure 105 is provided adjacent to the second gate stack structure 104, the second gate stack structure 104 and the third gate stack structure 105 are spaced by a second trench 132, and the erase gate 19 is formed in the second trench 132. The composition and formation process of the third gate stack structure 105 may be the same as those of the first gate stack structure 103 and the second gate stack structure 104, and are not described herein again.
A common source or a common drain may be formed in the substrate 10 at the bottom of the second trench 132 before the polysilicon layer 14 is subsequently formed in the second trench 132. As shown in fig. 2b, the common drain 102 is formed in the substrate 10 at the bottom of the first trench 131, and the common source 101 may be formed in the substrate 10 at the bottom of the second trench 132.
The step of forming the erase gate 19 in the second trench 132 may include:
first, when the polysilicon layer 14 is formed in the first trench 131 in step S2, the polysilicon layer 14 is simultaneously formed in the second trench 132, as shown in fig. 2c, the polysilicon layer 14 does not fill the second trench 132; also, as described in the above step S2, the polysilicon layer 14 in the second trench 132 is ion implanted to reduce the resistance of the polysilicon layer 14 and to reduce the electron depletion of the polysilicon layer 14. The type of the implanted ions may be N-type or P-type, the N-type ion species may include boron, indium, gallium, or the like, and the P-type ion species may include phosphorus, arsenic, antimony, or the like.
Then, in the process of forming the inner sidewall spacers 16 on the exposed sidewalls of the first trench 131 in step S3, the sacrificial layer 15 also covers the polysilicon layer 14 in the second trench 132 and the second gate stack structure 104 and the third gate stack structure 105 on both sides of the second trench 132, and the sacrificial layer 15 fills the second trench 132. In the process of removing the sacrificial layer 15 at the bottom of the groove 151 by etching to form the inner sidewall 16, the sacrificial layer 15 on the second trench 132 is only partially removed by etching. The polysilicon layer 14 in the second trench 132 is still covered with the sacrificial layer 15 with a partial thickness, that is, an etching barrier layer 17 is formed on the polysilicon layer 14 in the second trench 132 to avoid etching the polysilicon layer 14 in the second trench 132 when the polysilicon layer 14 in the first trench 131 is subsequently etched.
In addition, if the recess 151 is formed by photolithography and etching processes, when the sacrificial layer 15 at the middle position of the first trench 131 or at a position close to the middle is directly removed, the sacrificial layer 15 in the second trench 132 may not be removed, or only a portion of the thickness may be removed.
Next, in step S4, when the polysilicon layer 14 in the first trench 131 is etched by using the inner sidewall 16 as a mask, the polysilicon layer 14 in the second trench 132 is not etched due to the etching stop layer 17 formed on the polysilicon layer 14 in the second trench 132, as shown in fig. 2 f; and, when removing the inner sidewall spacers 16, the etch stop layer 17 may be removed at the same time to form the erase gate 19, as shown in fig. 2g, the polysilicon layer 14 in the second trench 132 is formed as the erase gate 19. Since different etching gases are used for etching the sacrificial layer 15 and etching the polysilicon layer 14 in the first trench 131, the etching barrier layer 17 can play a role in blocking when the polysilicon layer 14 in the first trench 131 is etched. And because the material of the etching barrier layer 17 is the same as that of the inner side wall 16 (i.e., both the material of the sacrificial layer 15), the etching barrier layer 17 can also be removed by cleaning with a hydrofluoric acid solution.
In addition, the method of manufacturing the flash memory device further includes: as shown in fig. 2h, an interlayer dielectric layer 20 is formed on the substrate 10, and the interlayer dielectric layer 20 buries the word line gate 18, the erase gate 19, the first gate stack structure 103, the second gate stack structure 104, and the third gate stack structure 105 therein; and forming a conductive contact plug 21 in the interlayer dielectric layer 20 at a position at or near the middle of the first trench 131, wherein the conductive contact plug 21 is separated from the word line gate 18 in the first trench 131 by the interlayer dielectric layer 20, and the bottom of the conductive contact plug 21 is electrically contacted with the common drain 102 in the substrate 10. As shown in the foregoing steps S1 to S4, since the adjacent word line gates 18 have the same or nearly the same width, the conductive contact plugs 21 have the same or nearly the same distance from the word line gates 18 on both sides and the first gate stack structure 103 and the second gate stack structure 104 on both sides, so that the risk of short circuit is reduced and the performance of the flash memory device is improved.
In addition, the steps in the method for manufacturing the flash memory device are not limited to the above forming order, and the order of the steps can be adjusted adaptively.
In summary, the method for manufacturing a flash memory device provided by the present invention includes: providing a substrate, wherein a first grid stacking structure and a second grid stacking structure which are adjacent to each other are formed on the substrate, and the interval between the first grid stacking structure and the second grid stacking structure is a first groove; forming a polysilicon layer in the first trench, wherein the polysilicon layer does not fill the first trench to expose the sidewall of the first trench with partial height; forming an inner side wall on the exposed side wall of the first groove; and etching the polycrystalline silicon layer in the first groove by taking the inner side wall as a mask so as to form a word line grid. The manufacturing method of the flash memory device enables the adjacent word line grids to have the same width or be close to the same width, thereby reducing the risk of short circuit and improving the performance of the flash memory device.
An embodiment of the present invention provides a flash memory device, as shown in fig. 2h, the flash memory device includes a substrate 10, and a first gate stack structure 103 and a second gate stack structure 104 adjacent to each other on the substrate 10, a space between the first gate stack structure 103 and the second gate stack structure 104 is a first trench 131, the flash memory device further includes a word line gate 18 having the same or nearly the same width, and the word line gate 18 is located on a sidewall of the first gate stack structure 103 and the second gate stack structure 104 in the first trench 131.
The flash memory device further includes a third gate stack structure 105 adjacent to the second gate stack structure 104, the second gate stack structure 104 and the third gate stack structure 105 are spaced by a second trench 132, and an erase gate 19 is formed in the second trench 132.
The first gate stack structure 103, the second gate stack structure 104 and the third gate stack structure 105 all include a gate structure 11 and a gate sidewall 12 covering a sidewall of the gate structure 11, the gate structure 11 sequentially includes, from bottom to top, a floating gate layer 111, an inter-gate dielectric layer 112, a control gate layer 113 and a hard mask layer 114, and the gate sidewall 12 may sequentially include, from inside to outside, a first oxide layer 121, a nitride layer 122 and a second oxide layer 123 from the sidewall of the gate structure 11; and a tunnel oxide layer (not shown) is formed between the substrate 10 and the first gate stack structure 103, the second gate stack structure 104, and the third gate stack structure 105. The first oxide layer 121 and the second oxide layer 123 may be made of silicon oxide, and the nitride layer 122 may be made of silicon nitride. In addition, the gate sidewall spacer 12 may also only include the first oxide layer 121 and the nitride layer 122.
In addition, ions are also implanted in the word line gate 18 and the erase gate 19 to reduce the resistance of the word line gate 18 and the erase gate 19 and to reduce the electron depletion of the word line gate 18 and the erase gate 19. The type of the implanted ions may be N-type or P-type, the N-type ion species may include boron, indium, gallium, or the like, and the P-type ion species may include phosphorus, arsenic, antimony, or the like.
The flash memory device further includes: a common source or common drain in the substrate 10 at the bottom of the first trench 131 and a common drain or common source in the substrate 10 at the bottom of the second trench 132. As shown in fig. 2h, a common drain 102 is formed in the substrate 10 at the bottom of the first trench 131, and a common source 101 is formed in the substrate 10 at the bottom of the second trench 132.
The flash memory device further includes: an interlayer dielectric layer 20 located on the substrate 10, and a conductive contact plug 21 located in the interlayer dielectric layer 20 in the first trench 131, wherein the conductive contact plug 21 is located at a position at or near the middle of the first trench 131. Wherein the interlayer dielectric layer 20 buries the word line gate 18, the erase gate 19, the first gate stack structure 103, the second gate stack structure 104, and the third gate stack structure 105 therein; the conductive contact plug 21 is isolated from the word line gate 18 in the first trench 131 by the interlayer dielectric layer 20, and the bottom of the conductive contact plug 21 is in electrical contact with the common drain 102 in the substrate 10.
Since the adjacent word line gates 18 have the same or nearly the same width, the conductive contact plug 21 has the same or nearly the same distance from the word line gate 18 on both sides and the first gate stack structure 103 and the second gate stack structure 104 on both sides, thereby reducing the risk of short circuit and improving the performance of the flash memory device.
In addition, the flash memory device can also be manufactured by adopting the manufacturing method of the flash memory device provided by the invention.
In summary, the flash memory device provided by the present invention includes: the semiconductor device comprises a substrate, a first gate stack structure and a second gate stack structure which are adjacent to each other and are positioned on the substrate, wherein the interval between the first gate stack structure and the second gate stack structure is a first groove, and the semiconductor device further comprises: word line gates of the same or nearly the same width are located on sidewalls of the first and second gate stack structures in the first trench. The flash memory device provided by the invention reduces the risk of short circuit, thereby improving the performance of the flash memory device.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (13)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate, wherein a first grid stacking structure and a second grid stacking structure which are adjacent to each other are formed on the substrate, and the interval between the first grid stacking structure and the second grid stacking structure is a first groove;
forming a polysilicon layer in the first trench, wherein the polysilicon layer does not fill the first trench and exposes the side wall of the first trench with partial height;
forming an inner side wall on the exposed side wall of the first groove; and the number of the first and second groups,
and etching the polycrystalline silicon layer in the first groove by taking the inner side wall as a mask so as to form a word line grid.
2. The method of manufacturing a flash memory device according to claim 1, wherein the step of forming the inner spacers on the exposed sidewalls of the first trench comprises:
forming a sacrificial layer to cover the polysilicon layer and the first and second gate stack structures, wherein the sacrificial layer fills the first trench;
forming a groove in the sacrificial layer, wherein the groove is located at the middle position above the first groove; and the number of the first and second groups,
and etching the sacrificial layer along the groove by adopting a side wall etching process until the upper surface of the polycrystalline silicon layer in the first groove is exposed so as to form the inner side wall.
3. The method of manufacturing a flash memory device according to claim 2, wherein the recess is formed using a photolithography and etching process.
4. The method of manufacturing a flash memory device according to claim 2, wherein the recess is formed by controlling a process parameter of forming the sacrificial layer.
5. The method of manufacturing a flash memory device of claim 1, wherein a common source or a common drain is formed in the substrate at the bottom of the first trench before the polysilicon layer is formed in the first trench.
6. The method of manufacturing a flash memory device according to claim 1, wherein ion implantation is performed on the polysilicon layer after the polysilicon layer is formed in the first trench and before the inner spacers are formed on the exposed sidewalls of the first trench.
7. The method of manufacturing a flash memory device of claim 1, wherein a third gate stack structure is provided adjacent to the second gate stack structure, the space between the second and third gate stack structures being a second trench in which an erase gate is formed.
8. The method of manufacturing a flash memory device according to claim 1, further comprising: forming an interlayer dielectric layer on the substrate, and forming a conductive contact plug in the interlayer dielectric layer in the first trench, the conductive contact plug being located at the middle of the first trench.
9. The method of manufacturing a flash memory device according to any one of claims 1 to 8, wherein widths of the word line gates are the same.
10. A flash memory device comprising a substrate, a first gate stack structure and a second gate stack structure located adjacent to each other on the substrate, a space between the first and second gate stack structures being a first trench, the flash memory device further comprising:
word line gates on sidewalls of the first and second gate stack structures in the first trench, the word line gates having the same width.
11. The flash memory device of claim 10, comprising: a third gate stack adjacent to the second gate stack, the second and third gate stacks spaced apart by a second trench having an erase gate formed therein.
12. The flash memory device of claim 10, further comprising: the substrate comprises an interlayer dielectric layer positioned on the substrate and a conductive contact plug positioned in the interlayer dielectric layer in the first groove, wherein the conductive contact plug is positioned in the middle of the first groove.
13. The flash memory device of claim 11, wherein the first, second, and third gate stack structures each comprise a gate structure and a gate sidewall covering a sidewall of the gate structure, and the gate structure comprises, from bottom to top, a floating gate layer, an inter-gate dielectric layer, a control gate layer, and a hard mask layer.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040197996A1 (en) * | 2003-03-21 | 2004-10-07 | Bomy Chen | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby |
| US20060011966A1 (en) * | 2004-07-15 | 2006-01-19 | Promos Technologies Inc. | Structure of a non-volatile memory cell and method of forming the same |
| CN1992235A (en) * | 2005-12-26 | 2007-07-04 | 东部电子股份有限公司 | Nor-type flash memory cell array and method for manufacturing the same |
| US20130099301A1 (en) * | 2011-10-19 | 2013-04-25 | Magnachip Semiconductor, Ltd. | Nonvolatile memory device and method of manufacturing thereof |
| US20160358928A1 (en) * | 2015-06-03 | 2016-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned flash memory device with word line having reduced height at outer edge opposite to gate stack |
-
2019
- 2019-09-16 CN CN201910872062.4A patent/CN110600474A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040197996A1 (en) * | 2003-03-21 | 2004-10-07 | Bomy Chen | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby |
| US20060011966A1 (en) * | 2004-07-15 | 2006-01-19 | Promos Technologies Inc. | Structure of a non-volatile memory cell and method of forming the same |
| CN1992235A (en) * | 2005-12-26 | 2007-07-04 | 东部电子股份有限公司 | Nor-type flash memory cell array and method for manufacturing the same |
| US20130099301A1 (en) * | 2011-10-19 | 2013-04-25 | Magnachip Semiconductor, Ltd. | Nonvolatile memory device and method of manufacturing thereof |
| US20160358928A1 (en) * | 2015-06-03 | 2016-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned flash memory device with word line having reduced height at outer edge opposite to gate stack |
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