WO2021128908A1

WO2021128908A1 - Method for manufacturing semiconductor device, semiconductor device and electronic device

Info

Publication number: WO2021128908A1
Application number: PCT/CN2020/111336
Authority: WO
Inventors: 张松; 梁志彬; 李小红; 金炎; 王德进
Original assignee: 无锡华润上华科技有限公司
Priority date: 2019-12-24
Filing date: 2020-08-26
Publication date: 2021-07-01
Also published as: CN113035877A; CN113035877B

Abstract

A method for manufacturing a semiconductor device, the semiconductor device and an electronic device. The method comprises: step S1: providing a semiconductor substrate, and forming a floating gate structure on the semiconductor substrate, the floating gate structure comprising a floating gate layer, and the floating gate structure having a spacer region exposing a part of the semiconductor substrate; step S2: forming a dielectric layer on the surface of the semiconductor substrate, wherein the dielectric layer covers the semiconductor substrate and the sidewall of the floating gate layer; step S3: depositing a control gate material layer on the surface of the semiconductor substrate to cover the dielectric layer and the floating gate structure; and step S4: patterning the control gate material layer to form a control gate structure, the control gate structure partially covering the dielectric layer on the sidewall of the floating gate layer.

Description

Manufacturing method of semiconductor device, semiconductor device and electronic device

Technical field

The present invention relates to the technical field of motors, and in particular to a manufacturing method of a semiconductor device, a semiconductor device and an electronic device.

Background technique

Flash memory is divided into two types: stack gate devices and split gate devices. The stacked gate device has a floating gate and a control gate. The control gate is located above the floating gate. The method of manufacturing the stacked gate device is simpler than the method of manufacturing the split gate device. However, the stacked gate device has an over-erasing problem. Different from the stacked gate device, the split gate device forms a word line as the erase gate on one side of the floating gate, and the word line acts as a control gate. In terms of erasing and writing performance, the split gate device effectively avoids the problem of the stacked gate device. Over the erasure problem, the circuit design is relatively simple. Moreover, split-gate devices use source-side hot electron injection for programming, which has higher programming efficiency and is therefore widely used in various electronic products such as smart cards, SIM cards, microcontrollers, and mobile phones.

In flash memory, PIP capacitors are widely used to prevent noise and frequency modulation of analog devices. However, due to the difference between the structure of the split gate device and the stacked gate device, it is necessary to increase the process steps to integrate the PIP capacitor in the process of the split gate device. The process of forming a PIP capacitor cannot be incorporated into the process of forming a split gate device.

For this reason, it is necessary to propose a new manufacturing method of semiconductor devices, semiconductor devices and electronic devices to solve the problems in the prior art.

Summary of the invention

A series of simplified concepts are introduced in the content of the invention, which will be explained in further detail in the specific implementation section. The content of the present invention does not mean to try to limit the key features and necessary technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

In order to solve the problems in the prior art, the present invention provides a method of manufacturing a semiconductor device, the method including:

Step S1, a semiconductor substrate is provided, a floating gate structure is formed on the semiconductor substrate, the floating gate structure includes a floating gate layer, and the floating gate structure includes a spacer region exposing a part of the semiconductor substrate ；

Step S2, forming a dielectric layer on the surface of the semiconductor substrate, wherein the dielectric layer covers the sidewalls of the semiconductor substrate and the floating gate layer;

Step S3, depositing a control gate material layer on the surface of the semiconductor substrate to cover the dielectric layer and the floating gate structure;

Step S4, patterning the control gate material layer to form a control gate structure, the control gate structure partially covering the dielectric layer on the sidewall of the floating gate layer, wherein:

The dielectric layer located between the sidewall of the floating gate layer and the control gate structure is a capacitor dielectric layer, and the floating gate layer, the capacitor dielectric layer and the control gate structure constitute a PIP capacitor.

The present invention also provides a semiconductor device, including:

Semiconductor substrate

A floating gate structure located on a semiconductor substrate, the floating gate structure includes a floating gate layer, and the floating gate structure includes a spacer region exposing a part of the semiconductor substrate;

A dielectric layer covering the sidewalls of the semiconductor substrate and the floating gate layer;

A control gate structure partially covering the dielectric layer on the sidewall of the floating gate layer; wherein,

The present invention also provides an electronic device including the above-mentioned semiconductor device.

The details of one or more embodiments of the present invention are set forth in the following drawings and description. Other features, objects and advantages of the present invention will become apparent from the description, drawings and claims.

Description of the drawings

The following drawings of the present invention are used here as a part of the present invention for understanding the present invention. The drawings show the embodiments of the present invention and the description thereof to explain the principle of the present invention.

In the attached picture:

1A-1E are flowcharts of forming flash memory cells and PIP capacitors in a stacked gate device process according to a manufacturing method of a semiconductor device;

2A-2E are flow charts of a separation gate device process according to a method of manufacturing a semiconductor device;

3A-1-FIG. 3E-5 are structural schematic diagrams of a semiconductor device formed in a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein,

FIGS. 3A-1, 3B-1, 3C-1, 3D-1, and 3E-1 show a flash memory including a split gate structure in a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention Schematic diagram of the structure of the device area,

3A-4, 3B-4, 3C-4, 3D-4, and 3E-4 are the top of the middle PIP capacitor region of the semiconductor device formed in the method of manufacturing a semiconductor device according to an embodiment of the present invention Schematic,

3A-5, FIG. 3B-5, FIG. 3C-5, FIG. 3D-5, and FIG. 3E-5 are the PIP capacitor regions of the semiconductor device formed in the method of manufacturing a semiconductor device according to another embodiment of the present invention Top structure diagram,

Figure 3A-2, Figure 3B-2, Figure 3C-2, Figure 3D-2 and Figure 3E-2 are based on Figure 3A-4, Figure 3B-4, Figure 3C-4, Figure 3D-4 and Figure 3E-4 The schematic diagram of the structure of the semiconductor device viewed in the X direction of the PIP capacitor region shown in,

Figure 3A-3, Figure 3B-3, Figure 3C-3, Figure 3D-3 and Figure 3E-3 are based on Figure 3A-4, Figure 3B-4, Figure 3C-4, Figure 3D-4 and Figure 3E-4 The schematic diagram of the structure of the semiconductor device viewed in the Y direction of the PIP capacitor region shown in;

FIG. 4 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed ways

1A-1E show a process of forming a flash memory cell and a PIP capacitor in a stacked gate device process, where the process of forming a flash memory cell and a PIP capacitor includes: as shown in FIG. 1A, a tunneling oxide is formed on the semiconductor substrate 100 Layer 101, and a floating gate material layer 102 covering the tunnel oxide layer 101; as shown in FIG. 1B, an ONO (oxide layer-nitride layer-oxide layer) layer 103 is formed on the floating gate material layer 102; as shown in FIG. 1C As shown, a control gate material layer 104 is formed to cover the ONO layer 103 and the floating gate material layer 102; as shown in FIG. 1D, the control gate material layer 104, the tunnel oxide layer 101, the floating gate material layer 102 and the ONO layer 103 are patterned, To form a control gate structure A, part of the control gate material layer 102 and the ONO layer 103 are removed to form a logic gate structure B and a PIP capacitor C; as shown in FIG. 1E, a contact hole 105 is formed to connect the semiconductor substrate 100 and the control gate structure, respectively A. Logic gate structure B and PIP capacitor C, wherein the control gate material layer 104 in the PIP capacitor C constitutes the upper plate of the PIP capacitor, and the floating gate material layer 102 in the PIP capacitor C constitutes the lower plate of the PIP capacitor. 2A-2E show the process of forming a split gate device. As shown in FIG. 2A, a floating gate structure 201 is formed on a semiconductor substrate 200. The floating gate structure 201 includes a gate electrode layer 2011 and a floating gate material layer stacked in sequence. 2012 and field oxygen 2013; as shown in FIG. 2B, a tunnel oxide layer 202 is formed; as shown in FIG. 2C, a control gate material layer 203 is formed; as shown in FIG. 2D, the control gate material layer 203 is etched to form a gate structure; As shown in FIG. 2E, contact holes 204 are formed to connect the control gate material layer 203 and the semiconductor substrate 200, respectively. Comparing the process of forming the flash memory cell and the PIP capacitor in the stacked gate device process in FIGS. 1A-1G and the process of forming the split gate device in FIGS. 2A-2E, it is obvious that the process of forming the PIP capacitor cannot be incorporated into the process of forming the split gate device.

Example one

In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, including:

The dielectric layer located between the sidewall of the floating gate layer and the control gate structure is a capacitor dielectric layer, and the floating gate layer, the capacitor dielectric layer, and the control gate structure constitute a PIP capacitor.

3A-1 to 3E-4 and FIG. 4 are exemplary descriptions of a method for manufacturing a semiconductor device according to the present invention. 3A-1 to 3E-4 are structural schematic diagrams of a semiconductor device formed in a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein, FIG. 3A-1, FIG. 3B-1, and FIG. 3C-1 3D-1 and 3E-1 are schematic diagrams of a flash memory device region including a split gate structure in a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIGS. 3A-4 and 3B- 4. FIGS. 3C-4, 3D-4, and 3E-4 are schematic diagrams of the top structure of the middle PIP capacitor region of the semiconductor device formed in the method for manufacturing a semiconductor device according to an embodiment of the present invention, FIGS. 3A-5, 3B-5, 3C-5, 3D-5, and 3E-5 are schematic diagrams of the top structure of the middle PIP capacitor region of the semiconductor device formed in the method of manufacturing a semiconductor device according to another embodiment of the present invention. 3A-2, Figure 3B-2, Figure 3C-2, Figure 3D-2 and Figure 3E-2 are based on Figure 3A-4, Figure 3B-4, Figure 3C-4, Figure 3D-4 and Figure 3E-4 Figure 3A-3, Figure 3B-3, Figure 3C-3, Figure 3D-3 and Figure 3E-3 are based on Figure 3A-4, Figure 3B. Figure 3A-3, Figure 3B-3, Figure 3C-3, Figure 3D-3 and Figure 3E-3 are shown as a schematic diagram of the structure of the semiconductor device observed in the X direction of the PIP capacitor region. -4, Figure 3C-4, Figure 3D-4 and Figure 3E-4 shown in the PIP capacitor region of the Y-direction view of the semiconductor device structure diagram; Figure 4 is a semiconductor device manufacturing according to an embodiment of the present invention Flow chart of the method.

First, referring to FIG. 4, step S1 is performed: a semiconductor substrate is provided, a floating gate structure is formed on the semiconductor substrate, the floating gate structure includes a floating gate layer, and the floating gate structure includes an exposed portion The spacing area of the semiconductor substrate.

As shown in FIGS. 3A-1, 3A-2, 3A-3, 3A-4, and 3A-5, a semiconductor substrate 300 is provided, and a floating gate structure 301 is formed on the semiconductor substrate 300. The floating gate structure 301 includes a spacer region 300A exposing part of the semiconductor substrate 300.

Exemplarily, the semiconductor substrate may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI) ), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. As an example, in this embodiment, the constituent material of the semiconductor substrate is single crystal silicon.

Exemplarily, an isolation structure (not shown) is formed in the semiconductor substrate 300.

Exemplarily, a method for forming an isolation structure in a semiconductor substrate 300 includes: forming a patterned mask layer in the semiconductor substrate to expose a region in the semiconductor substrate where the shallow trench isolation structure is to be formed; The patterned mask layer performs an etching process for the mask to form a shallow trench; performs a chemical meteorological deposition process to fill the isolation material layer in the shallow trench; performs a chemical mechanical polishing process to remove the shallow trench Isolation material layer. The above-mentioned method for forming an isolation structure in a semiconductor substrate can be any method well known to those skilled in the art, and will not be repeated here.

Continuing to refer to FIGS. 3A-1, 3A-2, and 3A-3, the floating gate structure 301 includes a gate dielectric layer 3011, a floating gate layer 3012, and a field oxide 3013.

According to the manufacturing process of the integrated PIP capacitor in the manufacturing process of the split gate device according to the present invention, FIG. 3A-1 shows a schematic diagram of the structure of the flash memory cell device area, and FIG. 3A-2, FIG. 3A-3 and FIG. 3A-4 are PIP capacitors The schematic diagram of the structure of the area, among which, Figures 3A-4 and Figure 3A-5 are the schematic diagrams of the planar structure of the PIP capacitor area, and Figures 3A-2 and 3A-3 are the cross-sections observed in the X and Y directions of Figure 3A-4, respectively Schematic.

Exemplarily, the method of forming the floating gate structure 301 includes: forming a gate dielectric material layer and a floating gate material layer sequentially stacked on a semiconductor substrate; and forming a patterned hard mask layer on the floating gate material layer ( Such as silicon nitride layer); use the patterned hard mask layer as a mask to perform an ion implantation process to form a floating gate implantation area in the semiconductor substrate in the region where the floating gate structure is to be formed; perform a thermal oxidation process to float A field oxygen is formed in the floating gate material layer above the gate injection area; the hard mask layer and the floating gate material layer outside the floating gate injection area are removed.

Exemplarily, the material of the gate dielectric layer 3011 includes silicon oxide.

Exemplarily, the material of the floating gate layer 3012 includes monocrystalline silicon, polycrystalline silicon, doped polycrystalline silicon, and the like.

According to an example of the present invention, in the flash memory cell device area, the floating gate structure 301 is block-shaped.

According to an example of the present invention, as shown in FIGS. 3A-4, in the PIP capacitor region, the floating gate structure 301 includes a spacer region 300A exposing a part of the semiconductor substrate 300, so that a part of the semiconductor substrate 300 connects the floating gate structure 301 Spaced apart. A spacer region is provided in the floating gate structure 301. In the subsequent process of forming the control gate structure of the flash memory cell device, a dielectric layer is formed on the semiconductor substrate 300 (for example, a tunnel oxide layer is formed by oxidizing the semiconductor substrate) to cover the floating gate structure. The sidewall of the gate structure 301 is used as the dielectric layer of the inter-plate dielectric layer in the PIP capacitor, so that the manufacturing process of the PIP capacitor can be incorporated into the manufacturing process of the flash memory cell device of the split gate structure.

Exemplarily, the spacing area 300A is arranged in a strip shape.

Exemplarily, as shown in FIGS. 3A-4, in the PIP capacitor region, the floating gate structure 301 is arranged as a bulk gate, and the bulk gate contains a plurality of the spacer regions 300A arranged side by side along the first direction. The spacer region 300A has a strip shape, and the spacer region 300A exposes the semiconductor substrate 300. Since the floating gate structure is formed by thermal oxidation, the floating gate material layer is oxidized into field oxygen. By arranging the spacer area into multiple strips instead of connecting into a block, the thermal oxidation process can be avoided. The floating gate material layer is completely oxidized and does not conduct electricity, which results in the failure of subsequent PIP device formation.

According to an example of the present invention, as shown in Figs. 3A-4, the spacer area 300A is formed as spacer areas 300A arranged side by side along the first direction (as shown in the Y direction in Fig. 3B-4).

Exemplarily, as shown in FIGS. 3A-5, in the PIP capacitor region, the floating gate structure 301 has at least two strip-shaped gates 301A arranged side by side along the first direction, and there are arranged between the strip-shaped gates 301A. Said spacer region 300A, the spacer region 300A exposes the semiconductor substrate 300. Similar to the above example in which the floating gate structure 301 includes a plurality of strip-shaped spacer regions 300A arranged in parallel along the first direction, the floating gate structure 301 is arranged in a plurality of strip-like shapes arranged in parallel along the first direction. The gate 301A, in which the spacer region 300A is also strip-shaped, can prevent the floating gate material layer from being completely oxidized and non-conductive during the thermal oxidation process, which may result in failure to form subsequent PIP devices.

At the same time, in the above-mentioned setting of the floating gate structure 301 to include the strip-shaped spacer region 300A, in the subsequent process of forming contact holes to connect the floating gate layer in the floating gate structure 301, the contact holes can be arranged in the strip-shaped spacer region In order to increase the probability of contact between the contact hole and the floating gate layer in the floating gate structure 301, so as to avoid poor contact caused by the offset of the contact hole.

In the subsequent embodiments, the floating gate structure 301 will be arranged as a bulk gate in the PIP capacitor area, and a plurality of strips arranged in parallel along the first direction are arranged in the bulk gate. The interval area 300A is described as an example. It should be understood that, in this embodiment, the floating gate structure 301 is configured as a bulk gate and the bulk gate is provided with a plurality of strip-shaped spacer regions arranged in parallel along the first direction, which is merely exemplary. The skilled person should understand that any method of providing a spacer region exposing part of the semiconductor substrate in the floating gate structure is applicable to the present invention.

Exemplarily, the floating gate structure 301 in the bulk flash memory cell device region and the floating gate structure 301 in the PIP capacitor region are formed in the same floating gate formation process. Specifically, when forming the patterned hard mask layer for performing the ion implantation process, the patterned mask layer covers the area of the floating gate structure 301 in the flash memory cell device area where the semiconductor substrate 300 is to be exposed for subsequent After the floating gate implantation region is formed, the hard mask layer and the floating gate material layer other than the floating gate implantation region are removed while exposing the region of the floating gate structure 301 in the flash memory cell device region where the semiconductor substrate 300 is to be exposed. The above process can be performed by designing the photolithography pattern of the patterned hard mask layer, which is a technique well known to those skilled in the art, and will not be repeated here.

Continuing, referring to FIG. 4, step S2 is performed: forming a dielectric layer on the surface of the semiconductor substrate, wherein the dielectric layer covers the semiconductor substrate and the sidewalls of the floating gate layer.

As shown in FIGS. 3B-1, 3B-2, 3B-3, and 3B-4, a dielectric layer 302 is formed on the surface of the semiconductor substrate 300, wherein the dielectric layer 302 also covers the sidewall of the floating gate structure 301.

According to the manufacturing process of the integrated PIP capacitor in the manufacturing process of the flash memory cell device with the split gate according to the present invention, FIG. 3B-1 shows a schematic diagram of the structure of the flash memory cell device area, FIG. 3B-2, FIG. 3B-3, and FIG. 3B-4 And Figure 3B-5 is a schematic diagram of the structure of the PIP capacitor area, in which Figure 3B-4 and Figure 3B-5 are schematic diagrams of the planar structure of the PIP capacitor area, Figure 3B-2, Figure 3B-3 are according to Figure 3B-4 Schematic diagram of the cross-sectional structure observed in the X and Y directions.

As shown in FIG. 3B-1, the sidewalls of the floating gate structure 301 in the flash memory cell device area and the covering dielectric layer 302 on the semiconductor substrate 300 serve as the intermediate between the control gate and the floating gate structure in the subsequent manufacturing process of the flash memory cell device. Electric layer.

As shown in Figure 3B-2, Figure 3B-3, Figure 3B-4 and Figure 3B-5, in the PIP capacitor area, the dielectric layer 302 serves as the dielectric layer 302 between the plates of the subsequent PIP capacitor, and the dielectric layer 302 covers the semiconductor substrate The bottom 300 and the sidewalls of the floating gate layer 3012 of the floating gate structure 301.

Exemplarily, the method of forming the dielectric layer 302 includes: performing a deposition process to cover the surface of the semiconductor substrate 300 and the surface of the floating gate structure 301 with a dielectric material layer, wherein the dielectric material layer also covers the sidewalls of the floating gate structure 301.

Exemplarily, the dielectric layer 302 includes a tunneling oxide layer, and setting the dielectric layer 302 as a tunneling oxide layer can simplify the formation process of the dielectric layer, and at the same time make the formed dielectric layer have a uniform thickness, good dielectric properties, and ultimately improve The performance of semiconductor devices.

Exemplarily, the method of forming the dielectric layer 302 includes: performing a thermal oxidation process to oxidize the surface of the semiconductor substrate 300 and the floating gate layer 3012 of the floating gate structure 301 into a tunnel oxide layer.

Continuing, referring to FIG. 4, step S3 is performed: depositing a control gate material layer on the surface of the semiconductor substrate to cover the dielectric layer and the floating gate structure.

As shown in FIGS. 3C-1, 3C-2, 3C-3, 3C-4, and 3C-5, a control gate material layer 303 is formed on the surface of the semiconductor substrate 300, wherein the control gate material layer 303 covers the flash memory cell The dielectric layer 302 and the floating gate structure 301 in the device area. At the same time, the control gate material layer 301 also covers the floating gate structure 301 and the dielectric layer 302 in the PIP capacitor area.

Exemplarily, the material of the control gate material layer 303 includes monocrystalline silicon, polycrystalline silicon, doped polycrystalline silicon, and the like.

Exemplarily, the method for forming the control gate material layer 303 includes techniques well known to those skilled in the art such as chemical weather deposition and physical vapor deposition, which will not be repeated here.

Continuing, referring to FIG. 4, step S4 is performed: patterning the control gate material layer to form a control gate structure, the control gate structure partially covering the dielectric layer on the sidewall of the floating gate layer.

As shown in FIGS. 3D-1, 3D-2, 3D-3, 3D-4, and 3D-5, after the control gate material layer 303 is patterned, a control gate structure 304 is formed. Wherein, the floating gate layer 3012, part of the dielectric layer 302, and the control gate structure 304 constitute a PIP capacitor, and the dielectric layer 302 constituting the PIP capacitor is the sidewall of the floating gate layer 3012 and the control gate structure 304. The intermediary layer 302 is shown by the dashed box in FIGS. 3D-3 and 3D-4.

According to the manufacturing process of integrating the PIP capacitor in the manufacturing process of the split gate device according to the present invention, FIG. 3D-1 shows a schematic diagram of the structure of the flash memory cell device area, and the control gate structure 304 partially covers the floating gate structure 301. Figure 3D-2, Figure 3D-3, Figure 3D-4 and Figure 3D-5 are schematic diagrams of the structure of the PIP capacitor area, among which Figure 3D-4 is a schematic diagram of the planar structure of the PIP capacitor area, Figure 3D-2, Figure 3D- 3 is a schematic diagram of the cross-sectional structure observed in the X direction and the Y direction in Fig. 3D-4, respectively.

As shown in FIG. 3D-1, the control gate structure 304 of the flash memory cell device region constitutes the separation gate of the flash memory cell.

As shown in FIGS. 3D-2, 3D-3, 3D-4, and 3D-5, the control gate structure 304 in the PIP capacitor region partially covers the floating gate structure 301 that exists as a striped gate, where, The control gate structure 304 covers the floating gate structure 301 along the direction (Y direction) in which the strip-shaped gate is arranged. 3D-2 and 3D-3, in the PIP capacitor, the sidewall of the floating gate structure 301 serves as the upper electrode plate, the control gate structure 304 on the opposite sidewall serves as the lower electrode plate, and the control gate structure 304 The dielectric layer 302 on the sidewall of the PIP capacitor serves as the dielectric layer of the PIP capacitor.

The capacitance value of the PIP capacitor according to the present invention will be exemplified below with reference to an example in which the floating gate structure 301 is configured as a bulk gate and a plurality of strip-shaped spacer regions arranged in parallel along the first direction are provided in the bulk gate. Introduction.

Exemplarily, the thickness of the floating gate layer 3012 in the floating gate structure is h (as shown in FIG. 3D-2). In the area of the PIP capacitor, the width of the control gate structure 304 covering the floating gate structure 301 is L, and the dielectric layer 302 The thickness of the _{strip is d 1} , the strip-shaped spacer region 300A will use the block gate as the floating gate structure 301 to be divided into n strips, the width of a single strip is w, and the space between adjacent strips ( That is, the width of the interval area) is d; therefore, according to the formula of the plate capacitance:

In the present invention, the capacitance of the PIP capacitor is:

Further, in the PIP capacitor according to the present invention, the coverage area of the control gate is taken as the effective area of the PIP capacitor, S′=[w*n+d*(n-1)]*L, when n is large, count n -1≈n, the capacitance per unit area is:

For a process of a specific size, the height of the floating gate structure is determined, that is, the floating gate layer h in the floating gate structure is constant, C′ is divided into the floating gate structure by the interval and the width w of the stripe and the width d of the spacer area and the thickness of the dielectric layer 302 is _{determined. 1} d, _{d. 1} is smaller when the width d of the thickness and the width w of the strip-shaped spacer regions and a dielectric layer 302 'larger capacitance per unit area C.

In the traditional process of flash memory devices with a stacked gate structure, the ONO layer in the PIP capacitor is used as the dielectric layer in the PIP capacitor, and the thickness of the ONO layer is relatively thick, so that the final C′ of the PIP capacitor is small. In the PIP capacitor according to the present invention, by reducing the thickness of the dielectric layer 302, for example, a tunnel oxide layer is formed, thereby increasing the capacitance C′ per unit area. Further, according to an example of the present invention, the spacer area provided in the floating gate structure of the PIP capacitor area is strip-shaped, so that the number n-1 of strip-shaped spacer areas and the covering floating gate can be selected according to the value of the capacitance C′ per unit area. The width L of the gate material layer 303 of the structure 301 is controlled to obtain the required capacitance value.

It should be understood that, in the above process of calculating the capacitance of the capacitor, the floating gate structure 301 is set as an example of a bulk gate and a plurality of strip-shaped spacer regions arranged in parallel along the first direction are provided in the bulk gate. The description is only exemplary, and those skilled in the art should understand that the floating gate structure 301 is arranged in a form of at least two strip-shaped gates 301A arranged side by side and strip-shaped spacer regions 300A are arranged between the strip-shaped gates 301A. Similar calculations can also be made according to the above method.

So far, a method of manufacturing a semiconductor device according to the present invention has been exemplarily introduced. In an example according to the present invention, it further includes: forming a contact structure to electrically connect the respective structures of the flash memory cell device region and the PIP capacitor region to an external circuit.

As shown in FIGS. 3E-1, 3E-2, 3E-3, 3E-4, and 3E-5, a contact hole 305 is formed, wherein the contact hole 305 located in the flash memory cell device region will control the gate structure 304 and The semiconductor substrate 300 is connected to the word line (WL), bit line (BL) and control source line (SL) of the external circuit. At the same time, the contact hole 305 located in the PIP capacitor area connects the control gate structure 304 and the floating gate structure 301 The floating gate layer 3012 is connected to an external circuit as the lower and upper plates of the PIP capacitor.

Exemplarily, the contact hole 305 located in the PIP capacitor region includes a first contact hole 3051 and a second contact hole 3052, wherein the first contact hole 3051 contacts the sidewall of the floating gate structure 301 to float the floating gate structure 301 The gate layer 3012 is connected to the external circuit; the second contact hole 3052 leads the control gate structure to the external circuit.

In an example according to the present invention, as shown in FIG. 3E-2, FIG. 3E-3, FIG. 3E-4 and FIG. 3E-5, the first contact hole 3051 is provided in the spacer region 300A, and is connected to the floating gate structure 301. The sidewall contacts connect the floating gate layer 3012 of the floating gate structure 301 to an external circuit.

In an example according to the present invention, as shown in FIGS. 3E-4 and 3E-5, the spacing area 300A is arranged in a strip shape arranged side by side along the first direction, and the aperture of the first contact hole 3051 is greater than or equal to the spacing area The width in the first direction. Setting the aperture of the first contact hole 3051 to be greater than or equal to the width of the spacer area in the first direction can reduce the occurrence of the phenomenon that the contact hole cannot be contacted with the floating gate layer of the floating gate structure when the contact hole is aligned and offset, and the process cost is reduced , Improve the yield of semiconductor devices.

In an example according to the present invention, as shown in FIGS. 3E-4 and 3E-5, the first contact hole 3051 is located at the end of the spacing area 300A, so that when the aperture of the contact hole is larger than the spacing area in the first direction When the width is large, it can be in contact with at least two side surfaces of the floating gate layer of the floating gate structure (the floating gate structure is set as a bulk gate and the bulk gate is provided with a plurality of bars arranged in parallel along the first direction. In the example of the spacer region, three side surfaces can be contacted, as shown in FIG. 3E-4), thereby further reducing the phenomenon that the floating gate layer of the floating gate structure cannot be contacted due to the offset of the contact hole alignment.

The above is an exemplary introduction of a method of manufacturing a semiconductor device according to the present invention. According to the method of manufacturing a semiconductor device of the present invention, the integration of the manufacturing process of the flash memory device and the PIP capacitor is realized through floating in the floating gate structure. A dielectric layer is arranged between the sidewall of the gate layer and the control gate structure to form a PIP capacitor, and the PIP capacitor of the upper and lower structure is changed to the left and right structure, so that the flash memory cell is manufactured at the same time without increasing any process steps and other costs. PIP capacitor.

Example two

The present invention also provides a semiconductor device, including:

Semiconductor substrate

A control gate structure partially covering the floating gate structure; wherein,

It is manufactured using the method described in the first embodiment.

Referring to FIGS. 3E-1, 3E-2, 3E-3, 3E-4, and 3E-5, a semiconductor device according to an example of the present invention will be exemplarily introduced.

As shown in FIGS. 3E-1, 3E-2, 3E-3, 3E-4, and 3E-5, the semiconductor device according to the present invention includes a semiconductor substrate 300.

Exemplarily, the semiconductor device according to the present invention includes a flash memory device area and a PIP capacitor area. Figure 3E-1 shows a schematic diagram of the device structure of the flash memory device area, Figures 3E-4 and Figure 3E-5 show a schematic plan view of the device in the PIP capacitor area, and Figure 3E-2 and Figure 3E-3 are based on Figure 3E, respectively. -4 Schematic diagram of the device structure observed in the X and Y directions.

According to the semiconductor device of the present invention, the semiconductor substrate 300 includes a floating gate structure 301, and the floating gate structure 301 includes a spacer region 300A exposing a part of the semiconductor substrate 300.

Exemplarily, the floating gate structure 301 includes a gate dielectric layer 3011, a floating gate layer 3012, and a field oxide 3013.

According to the semiconductor device of the present invention, the sidewalls of the floating gate layer 3012 of the semiconductor substrate 300 and the floating gate structure 301 are covered with a dielectric layer 302.

Exemplarily, the dielectric layer 302 includes a tunnel oxide layer. Setting the dielectric layer 302 as a tunnel oxide layer can simplify the formation process of the dielectric layer, and at the same time make the formed dielectric layer have a uniform thickness and good dielectric performance, and ultimately improve the performance of the semiconductor device.

According to the semiconductor device of the present invention, the control gate structure 304 partially covers the dielectric layer 302 on the sidewall of the floating gate layer 3012 of the floating gate structure 301; wherein the floating gate layer 3012, part of the dielectric layer 302 and the control gate structure 304 constitutes a PIP capacitor, wherein the dielectric layer 302 constituting the PIP capacitor is the dielectric layer 302 located between the sidewall of the floating gate layer 3012 and the control gate structure 304.

Exemplarily, as shown in FIGS. 3E-4 and 3E-5, the spacing regions 300A are arranged in strips arranged side by side along the first direction. Since there is a process of oxidizing the floating gate material layer into field oxygen by thermal oxidation during the formation of the floating gate structure, by setting the spacer area into multiple strips instead of connecting into a block, the thermal oxidation can be avoided. During the process, the floating gate material layer is completely oxidized and does not conduct electricity, resulting in failure to form subsequent PIP devices.

At the same time, in the above-mentioned setting of the floating gate structure 301 to include the strip-shaped spacer region 300A, in the subsequent process of forming contact holes to connect the floating gate layer in the floating gate structure 301, the contact holes can be arranged in the strip-shaped spacer region , In order to increase the probability of contact between the contact hole and the floating gate layer in the floating gate structure 301, thereby avoiding poor contact caused by the offset of the contact hole.

Exemplarily, as shown in FIGS. 3E-5, the floating gate structure 301 located in the PIP capacitor region includes at least two strip-shaped gates 301A arranged in parallel along a first direction, and one of the strip-shaped gates The interval area is provided between.

Exemplarily, as shown in FIG. 3E-4, the floating gate structure 301 located in the PIP capacitor area is configured as a bulk gate, and the bulk gate includes multiple gates arranged side by side along the first direction. One of the spaced regions 300A, and the spaced regions are strip-shaped. The spacing area provided in the floating gate structure of the PIP capacitor area is strip-shaped, so that the number of strip-shaped spacing areas and the width of the control gate structure 304 covering the floating gate structure 301 can be selected according to the value of the unit area capacitance to be designed. For the required capacitance value, the specific design process can refer to the description in the first embodiment, which will not be repeated here.

Exemplarily, as shown in FIGS. 3E-4 and 3E-5, the control gate structure 304 covers the floating gate structure along the first direction and exposes a part of the semiconductor substrate.

Exemplarily, as shown in FIG. 3E-1, FIG. 3E-2, FIG. 3E-3, FIG. 3E-4, and FIG. 3E-5, a contact hole 305 is further included. The contact hole 305 connects the floating gate layer, The control gate structure is connected to an external circuit to constitute the PIP capacitor.

Exemplarily, as shown in FIGS. 3E-2, 3E-3, 3E-4 and 3E-5, the contact hole 305 includes a first contact hole 3051 in contact with the floating gate layer 3012 and a control The gate structure 304 contacts the second contact hole 3052, wherein the first contact hole 3051 is in contact with the sidewall of the floating gate layer 3012.

Exemplarily, as shown in FIGS. 3E-2, 3E-3, 3E-4, and 3E-5, the first contact hole 3051 is located in the spacing area 300A.

Exemplarily, as shown in FIGS. 3E-4 and 3E-5, the spacing area 300A is arranged in a strip shape arranged side by side along the first direction, and the aperture of the first contact hole 3051 is greater than or equal to that of the spacing area 300A in the first direction. Upward width. Setting the aperture of the first contact hole 3051 to be greater than or equal to the width of the spacer region 300A in the first direction can reduce the phenomenon that the contact hole cannot be in contact with the floating gate layer of the floating gate structure due to the offset of the contact hole alignment and reduce the process Cost, improve the yield of semiconductor devices.

Exemplarily, the first contact hole 3051 is located at the end of the spacer region 300A, so that when the aperture of the contact hole is larger than the width of the spacer region in the first direction, it can be connected to at least two sides of the floating gate layer of the floating gate structure. Contact (In an example in which the floating gate structure is set as a bulk gate and a plurality of strip-shaped spacer regions arranged side by side along the first direction are provided in the bulk gate, contact on three sides can be achieved, as shown in FIG. 3E -4), so as to further reduce the occurrence of the phenomenon that the floating gate layer of the floating gate structure cannot be contacted due to the offset of the contact hole alignment.

The above is an exemplary introduction of a semiconductor device according to the present invention. According to the semiconductor device of the present invention, a flash memory device and a PIP capacitor are integrated, wherein the sidewalls of the floating gate layer in the floating gate structure and the control gate structure are integrated. A dielectric layer is arranged between them to form a PIP capacitor, and the PIP capacitor of the upper and lower structure is changed to a left and right structure, and the PIP capacitor can be manufactured at the same time as the flash memory cell is manufactured without increasing any process steps and other costs.

Example three

The present invention also provides an electronic device, including the semiconductor device as described in the second embodiment. Due to the semiconductor device according to the present invention, the flash memory device is integrated with the PIP capacitor, wherein the PIP capacitor is formed by arranging a dielectric layer between the sidewall of the floating gate layer in the floating gate structure and the control gate structure, thereby changing the PIP of the upper and lower structure. The capacitor has a left-right structure, and the PIP capacitor can be made at the same time as the flash memory cell without increasing any process steps and other costs; therefore, the electronic device according to the present invention also has the above-mentioned advantages.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications fall under the protection of the present invention. Within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scopes.

Claims

A semiconductor device including:

Semiconductor substrate

A floating gate structure located on a semiconductor substrate, the floating gate structure includes a floating gate layer, and the floating gate structure includes a spacer region exposing a part of the semiconductor substrate;

A dielectric layer covering the sidewalls of the semiconductor substrate and the floating gate layer; and

A control gate structure partially covering the dielectric layer on the sidewall of the floating gate layer; wherein,

The dielectric layer located between the sidewall of the floating gate layer and the control gate structure is a capacitor dielectric layer, and the floating gate layer, the capacitor dielectric layer and the control gate structure constitute a PIP capacitor.
The semiconductor device according to claim 1, wherein the dielectric layer comprises a tunnel oxide layer.
The semiconductor device according to claim 1, wherein the semiconductor substrate includes a flash memory device region and a PIP capacitor region.
The semiconductor device according to claim 1, wherein the spacer region is arranged in a stripe shape arranged side by side along the first direction.
The semiconductor device according to claim 4, wherein the floating gate structure located in the PIP capacitor region comprises at least two strip-shaped gates arranged in parallel along a first direction, one of the strip-shaped gates The interval area is provided between.
The semiconductor device according to claim 4, wherein the floating gate structure located in the PIP capacitor region is configured as a bulk gate, and the bulk gate includes parallelly arranged along a first direction. A plurality of the spaced regions, the spaced regions are strip-shaped.
4. The semiconductor device according to claim 4, wherein the control gate structure covers the floating gate structure along the first direction and exposes a part of the semiconductor substrate.
4. The semiconductor device according to claim 1, further comprising a contact hole that connects the floating gate layer and the control gate structure to an external circuit to form the PIP capacitor.
8. The semiconductor device according to claim 8, wherein the contact hole comprises a first contact hole in contact with the floating gate layer and a second contact hole in contact with the control gate structure, wherein the first contact hole It is in contact with the sidewall of the floating gate layer.
9. The semiconductor device according to claim 9, wherein the first contact hole is located in the spacer region.
The semiconductor device according to claim 10, wherein the spacer region is arranged in a strip shape arranged side by side along a first direction, and the aperture of the first contact hole is greater than or equal to that of the spacer region in the first The width in the direction.
9. The semiconductor device according to claim 9, wherein the first contact hole is located at an end of the spacer region.
A method for manufacturing a semiconductor device includes:

Step S1, a semiconductor substrate is provided, a floating gate structure is formed on the semiconductor substrate, the floating gate structure includes a floating gate layer, and the floating gate structure includes a spacer region exposing a part of the semiconductor substrate ；

Step S2, forming a dielectric layer on the surface of the semiconductor substrate, wherein the dielectric layer covers the sidewalls of the semiconductor substrate and the floating gate layer;

Step S3, depositing a control gate material layer on the surface of the semiconductor substrate to cover the dielectric layer and the floating gate structure; and

Step S4, patterning the control gate material layer to form a control gate structure, the control gate structure partially covering the dielectric layer on the sidewall of the floating gate layer, wherein:

The dielectric layer located between the sidewall of the floating gate layer and the control gate structure is a capacitor dielectric layer, and the floating gate layer, the capacitor dielectric layer and the control gate structure constitute a PIP capacitor.
The method according to claim 13, wherein the step of forming a dielectric layer on the surface of the semiconductor substrate comprises: performing a thermal oxidation process to separate the surface of the semiconductor substrate and the floating gate layer The surface is oxidized into a tunnel oxide layer.
An electronic device comprising the semiconductor device according to claim 1.