CN114005867A - High-electron-mobility heterojunction structure, preparation method, diode and transistor - Google Patents

High-electron-mobility heterojunction structure, preparation method, diode and transistor Download PDF

Info

Publication number
CN114005867A
CN114005867A CN202111070445.3A CN202111070445A CN114005867A CN 114005867 A CN114005867 A CN 114005867A CN 202111070445 A CN202111070445 A CN 202111070445A CN 114005867 A CN114005867 A CN 114005867A
Authority
CN
China
Prior art keywords
region
channel layer
ohmic contact
layer
composite
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111070445.3A
Other languages
Chinese (zh)
Inventor
刘志宏
李蔚然
黎培森
周瑾
邢伟川
李祥东
杨伟涛
周弘
张苇杭
张进成
郝跃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Guangzhou Institute of Technology of Xidian University
Original Assignee
Xidian University
Guangzhou Institute of Technology of Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University, Guangzhou Institute of Technology of Xidian University filed Critical Xidian University
Priority to CN202111070445.3A priority Critical patent/CN114005867A/en
Publication of CN114005867A publication Critical patent/CN114005867A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention relates to a high electron mobility heterojunction structure, a preparation method thereof, a diode and a transistor, wherein the heterojunction structure comprises: the composite buffer region is arranged on the substrate, and the channel layer is arranged on the composite barrier region; the ion implantation region penetrates through the composite barrier region and is positioned in the channel layer, and the part of the ion implantation region positioned in the channel layer forms n-type doping; the groove is positioned in the ion implantation area, penetrates through the composite barrier area and is positioned in the channel layer; the ohmic contact electrode fills the groove. In the heterojunction structure, the ion injection region in the channel layer forms n-type heavy doping, and the ohmic contact electrode in the ion injection region and the n-type heavy doping in the ion injection region form good contact, so that the ohmic contact electrode with extremely low resistance is realized.

Description

High-electron-mobility heterojunction structure, preparation method, diode and transistor
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a high-electron-mobility heterojunction structure, a preparation method thereof, a diode and a transistor.
Background
Gallium nitride and a family of group iii nitride materials thereof, which are typical third-generation semiconductor materials, have excellent characteristics such as wide band gap, high mobility, high polarization coefficient induced high two-dimensional electron gas concentration, high electron saturation velocity, and the like, and have attracted great interest in research and industry of radio frequency devices and power electronic devices. The gallium nitride high electron mobility transistor takes a gallium nitride heterojunction structure as a core, has the advantages of high output power, high efficiency, high temperature resistance, radiation resistance and the like in the aspect of radio frequency system application such as radar, satellite, base station and the like, has the advantages of low on resistance, low loss, high energy conversion efficiency, small volume, high temperature resistance, radiation resistance and the like in the aspect of power system application such as chargers, electric automobiles, power grids and the like, and has wide application prospect.
Ohmic contact to gallium nitride high electron mobility heterojunction structures is one of the key challenges affecting their electronic devices, including diodes and transistors. High performance diodes and transistors based on gallium nitride high electron mobility heterojunction structures require ohmic contacts with low resistance values. At present, the ohmic contact structure and the preparation technology mainly comprise the following steps:
depositing a metal, typically a metal material such as a titanium/aluminum/nickel/gold metal stack, on a gallium nitride heterojunction structure, and then annealing in an inert gas such as nitrogen, the titanium/aluminum/nickel/gold forms an alloy, the nitrogen and titanium/aluminum in the gallium nitride heterojunction structure form titanium nitride/aluminum nitride, and a large number of nitrogen vacancies are formed in the barrier and channel layers of the gallium nitride heterojunction structure, exhibiting a donor effect similar to that of an n-type highly doped, relatively good ohmic contact between the metal and the highly doped nitride region. The technology is currently the mainstream technology of ohmic contact of an aluminum gallium nitride/gallium nitride heterojunction structure, and can obtain good ohmic contact resistance (Rc is approximately equal to 0.3 omega), but the technology meets great difficulty in further reducing the resistance value of ohmic contact, particularly in an aluminum gallium nitride barrier and aluminum nitride barrier structure with high aluminum components.
And secondly, manufacturing a groove on the gallium nitride heterojunction structure, depositing metal in the groove, and directly forming contact between the metal and the two-dimensional electron gas. This technique can further reduce the ohmic contact resistance value compared to the first technique, but is still relatively high (Rc >0.25 Ω). In addition, the effect of ohmic contact has a great relationship with the process parameters of groove etching, the angle of the side wall and the quality of the gallium nitride heterojunction structure, and the process window is narrow, thereby affecting the yield of products.
And thirdly, carrying out ion implantation and annealing activation on the gallium nitride heterojunction structure, forming n-type high doping in the ion implantation area and forming good ohmic contact with the metal on the ion implantation area. This technique can realize ohmic contact (Rc <0.1 Ω) of lower resistance, but in barrier layers having a wider band gap, particularly, aluminum gallium nitride barrier layers and aluminum nitride barrier layers of high aluminum composition, ionization energy of ions is high, activation rate is low, high doping is not easily realized, and thus it is not easy to form relatively good ohmic contact with metal.
In summary, how to obtain low-resistance ohmic contact is an urgent problem to be solved.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a high-electron-mobility heterojunction structure, a preparation method thereof, a diode and a transistor. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a high electron mobility heterojunction structure based on ohmic contact, which comprises: a substrate, a composite buffer region, a channel layer, a composite barrier region, an ion implantation region, a groove and an ohmic contact electrode, wherein,
the substrate, the composite buffer region, the channel layer and the composite barrier region are sequentially stacked;
the ion implantation region penetrates through the composite barrier region and is positioned in the channel layer, and the part of the ion implantation region positioned in the channel layer forms n-type doping;
the groove is positioned in the ion implantation area, penetrates through the composite barrier area and is positioned in the channel layer;
the ohmic contact electrode fills the groove.
In one embodiment of the invention, the substrate is made of one or more of high-resistance silicon, semi-insulating silicon carbide, semi-insulating sapphire, semi-insulating diamond and semi-insulating aluminum nitride, and the thickness of the substrate is 50-1500 μm.
In one embodiment of the invention, the composite buffer region comprises a nucleation layer, a transition layer and a core buffer layer which are sequentially stacked, wherein the nucleation layer is positioned on the substrate.
In one embodiment of the invention, the material of the channel layer comprises one or more of gallium nitride, indium gallium nitride and aluminum gallium nitride, and the thickness is 10-500 nm.
In one embodiment of the present invention, the composite barrier region includes an isolation layer, a core barrier layer, and a cap layer, which are sequentially stacked, wherein the isolation layer is on the channel layer.
In one embodiment of the present invention, the implanted ions in the ion implantation region are one or more of silicon and germanium, and the concentration of the implanted ions is 1 × 1015-1×1022cm-3The depth is 5-1000 nm.
In one embodiment of the invention, the material of the ohmic contact electrode comprises one or more of titanium, aluminum, titanium nitride, gold, nickel, tantalum and tantalum nitride, and the thickness is 50nm-1 μm.
Another embodiment of the present invention provides a method for preparing a high electron mobility heterojunction structure based on ohmic contact, comprising the steps of:
s1, growing a composite buffer region, a channel layer and a composite barrier region on the surface of the substrate in sequence;
s2, performing ion implantation on the composite barrier region and part of the channel layer to form an ion implantation region;
s3, removing the composite barrier region and part of the channel layer in the ion implantation region, and forming a groove with the width smaller than that of the ion implantation region;
and S4, depositing metal in the groove to form an ohmic contact electrode.
Yet another embodiment of the present invention provides a diode having a high electron mobility heterojunction structure, including: a wafer, a cathode at one end of the wafer, and an anode at the other end of the wafer,
the wafer comprises a substrate, a composite buffer region, a channel layer and a composite barrier region which are sequentially stacked;
the cathode comprises a sub-injection region, a groove and an ohmic contact electrode, the ion injection region penetrates through the composite barrier region and is positioned in the channel layer, and the ion injection region part positioned in the channel layer forms n-type high doping; the groove is positioned in the ion implantation area, penetrates through the composite barrier area and is positioned in the channel layer; the ohmic contact electrode fills the groove;
the anode is located in the recombination barrier region.
Yet another embodiment of the present invention provides a transistor having a high electron mobility heterojunction structure, including a wafer, a source electrode at one end of the wafer, a drain electrode at the other end of the wafer, and a gate electrode between the source electrode and the drain electrode,
the wafer comprises a substrate, a composite buffer region, a channel layer and a composite barrier region which are sequentially stacked;
the source electrode and the drain electrode respectively comprise an injection region, a groove and an ohmic contact electrode, the ion injection region penetrates through the composite barrier region and is positioned in the channel layer, and the ion injection region part positioned in the channel layer forms n-type high doping; the groove is positioned in the ion implantation area, penetrates through the composite barrier area and is positioned in the channel layer; the ohmic contact electrode fills the groove;
the gate electrode is located on the composite barrier region.
Compared with the prior art, the invention has the beneficial effects that:
in the heterojunction structure, the ion injection region in the channel layer can form n-type heavy doping, and the ohmic contact electrode in the ion injection region can form good contact with the n-type heavy doping of the ion injection region, so that the problems that a heavily doped region is not easy to form due to the high forbidden bandwidth of the barrier layer and the heterojunction structure with the barrier layer with the high forbidden bandwidth is not easy to obtain low-resistance ohmic contact are solved, and the ohmic contact electrode with extremely low resistance is realized.
Drawings
Fig. 1 is a schematic structural diagram of an ohmic contact-based high electron mobility heterojunction structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a composite buffer according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a composite barrier region according to an embodiment of the present invention;
FIGS. 4a-4g are schematic process diagrams illustrating a method for fabricating an ohmic contact-based high electron mobility heterojunction structure according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a diode having a high electron mobility heterojunction structure according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a transistor having a high electron mobility heterojunction structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a high electron mobility heterojunction structure based on ohmic contact according to an embodiment of the present invention. The high electron mobility heterojunction structure comprises: a substrate 11, a composite buffer region 12, a channel layer 13, a composite barrier region 14, an ion implantation region 21, a groove 22, and an ohmic contact electrode 23.
Wherein, the substrate 11, the composite buffer region 12, the channel layer 13 and the composite barrier region 14 are sequentially laminated from bottom to top to form the wafer 1; a two-dimensional electron gas channel exists between the channel layer 13 and the recombination barrier region 14.
The ion implantation region 21 penetrates the recombination barrier region 14 and is located in the channel layer 13, and includes a region formed by implanting ions in a part of the recombination barrier region 14 and a part of the channel layer 13, and the ion implantation region located in the channel layer 13 is partially formed with n-type heavy doping.
The recess 22 is located in the ion implantation region 21 while penetrating the recombination barrier region 14 and being located in the channel layer 13. Specifically, a part of the recombination barrier region 14 and a part of the channel layer 13 in the ion implantation region 21 are removed to form the groove 22, and therefore, the width and the depth of the groove 22 are smaller than those of the ion implantation region.
The ohmic contact electrode 23 fills the groove 22. Specifically, the side and the bottom of the groove 22 are both in contact with the ion implantation region 21, and a two-dimensional electron gas channel exists between the channel layer 13 and the recombination barrier region 14 of the ion implantation region 21, and therefore, the side of the ohmic contact electrode 23 is in contact with the two-dimensional electron gas channel in the ion implantation region 21.
In this embodiment, the width and depth of the groove 22 are both smaller than those of the ion implantation region, which can ensure that the ohmic contact electrode 23 is in direct contact with the heavily n-doped semiconductor subjected to ion implantation, thereby significantly reducing the contact resistance of the ohmic contact electrode 23.
In a specific embodiment, the material of the substrate 11 comprises one or more of high resistivity silicon, semi-insulating silicon carbide, semi-insulating sapphire, semi-insulating diamond, semi-insulating aluminum nitride, and has a thickness of 50-1500 μm. Optionally, the substrate 11 is made of high-resistivity silicon, the resistivity of the high-resistivity silicon is 1000-30000 Ω · cm, and the crystal orientation is <111 >.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a composite buffer according to an embodiment of the present invention. The composite buffer region includes a nucleation layer 121, a transition layer 122 and a core buffer layer 123 stacked in this order from bottom to top, the nucleation layer 121 being located on the substrate 11.
Specifically, the nucleation layer 121 is made of aluminum nitride and has a thickness of 50-300 nm. The transition layer 122 is a plurality of aluminum gallium nitride layers, wherein Al components of the layers are different, or the transition layer 122 is an aluminum nitride/gallium nitride superlattice layer; the thickness of the transition layer 122 is 0.5-1.5 μm. The material of the core buffer layer 123 includes one or more of gallium nitride, aluminum gallium nitride, and aluminum nitride, and the thickness thereof is 0.5-2 μm.
In other embodiments, the composite buffer region 12 further includes a back barrier layer, the back barrier layer is disposed on the core buffer layer 123, and the material of the back barrier layer 123 includes one or more of aluminum gallium nitride, indium gallium nitride, and aluminum nitride, and the thickness of the back barrier layer is 2-100 nm.
Specifically, the material of the channel layer 13 includes one or more of gallium nitride, indium gallium nitride, and aluminum gallium nitride, and the thickness is 10 to 500 nm.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a composite barrier region according to an embodiment of the invention. The composite barrier region 14 includes an isolation layer 141, a core barrier layer 142, and a cap layer 143, which are stacked in this order from bottom to top, wherein the isolation layer 141 is located on the channel layer 13.
Specifically, the material of the isolation layer 141 includes aluminum nitride, and the thickness thereof is 0.5 to 1.5 nm. The material of the core barrier layer 142 is a material having a high aluminum composition, for example, the material of the core barrier layer 142 includes one or more of aluminum gallium nitride, indium aluminum nitride, and aluminum nitride having a high aluminum composition, the aluminum composition is > 30%, and the thickness thereof is 2-30 nm; optionally, when the material of the core barrier layer 142 is algan, the composition of aluminum in the algan, i.e., the atomic ratio of aluminum in the algan is greater than 30%, and the thickness of the algan is 2 to 30 nm; when the material of the core barrier layer 142 is indium aluminum nitride, the atomic ratio of indium in the indium aluminum nitride, that is, indium in the indium aluminum nitride, is 0.1-0.2, and the thickness of the indium aluminum nitride is 5-30 nm; when the material of the core barrier layer 142 is aluminum nitride, the thickness of the aluminum nitride is 2-10 nm. The material of the cap layer 143 includes one or more of gallium nitride and silicon nitride, and the thickness thereof is 1-10 nm; optionally, when the material of the cap layer 143 is gallium nitride, the thickness of the gallium nitride is 1-3 nm; when the material of the cap layer 143 is silicon nitride, the thickness of the silicon nitride is 1 to 10 nm.
Specifically, the implanted ions in the ion implantation region 21 are one or more of silicon and germanium, and the concentration of the implanted ions is 1 × 1015-1×1022cm-3The depth is 5-1000nm calculated from the cap layer 143 down. The ion-implanted region 21 has an electron concentration of 1X 10 in the channel layer portion15-1×1022cm-3。
Specifically, the material of the ohmic contact electrode 23 includes one or more of titanium, aluminum, titanium nitride, gold, nickel, tantalum, and tantalum nitride, for example, the material of the ohmic contact electrode 23 is, from bottom to top, titanium/aluminum, or titanium/aluminum/titanium nitride, or titanium/aluminum/titanium/gold, or titanium/aluminum/nickel/gold, or tantalum/aluminum/tantalum nitride, and so on. The thickness of the ohmic contact electrode 23 is 50nm to 1 μm.
Compared with the traditional ohmic contact structure of directly depositing metal, preparing a groove or injecting ions, the embodiment has obvious advantages for the gallium nitride heterojunction structure with the high-aluminum component aluminum gallium nitrogen or aluminum nitride barrier layer, and can solve the problem that the high-aluminum component aluminum gallium nitrogen or aluminum nitride barrier layer is difficult to form a heavily doped region due to higher forbidden bandwidth, so that the gallium nitride heterojunction structure with the high-aluminum component aluminum gallium nitrogen or aluminum nitride barrier layer is difficult to obtain low-resistance ohmic contact.
The heterojunction structure of the embodiment realizes n-type high doping in the channel layer of the ion implantation region, and has very low resistivity; forming a groove in the ion injection region and forming an ohmic contact electrode in the groove, wherein good ohmic contact is formed between the ohmic contact electrode and a two-dimensional electron gas channel between the nearby channel layer and the composite barrier region, and the contact resistance is extremely low; in addition, the ohmic contact electrode in the groove is in contact with the n-type highly-doped channel layer in the ion implantation area, so that good ohmic contact resistance is formed, and the contact resistance is extremely low; therefore, good ohmic contact with extremely low resistance is formed between the ohmic contact resistor and the two-dimensional electron gas, and the problems that a heavily doped region is not easy to form due to the fact that the forbidden bandwidth of the barrier layer is high, and the low-resistance ohmic contact is not easy to obtain in a heterojunction structure of the barrier layer with the high forbidden bandwidth are solved.
Example two
On the basis of the first embodiment, please refer to fig. 4a to 4g, and fig. 4a to 4g are process schematic diagrams of a method for fabricating an ohmic contact-based high electron mobility heterojunction structure according to an embodiment of the present invention. The preparation method comprises the following steps:
s1, growing a composite buffer region 12, a channel layer 13 and a composite barrier region 14 on the surface of the substrate 11 in sequence, as shown in fig. 4 a.
Specifically, a composite buffer region 12, a channel layer 13 and a composite barrier region 14 are continuously grown on the surface of a substrate 11, and a wafer 1 with a gallium nitride high electron mobility heterojunction structure is formed. The composite buffer region 12 includes a nucleation layer 121, a transition layer 122, and a buffer layer 123, which are sequentially stacked, as shown in fig. 2; the composite barrier region 14 includes an isolation layer 141, a core barrier layer 142, and a cap layer 143, which are sequentially stacked, as shown in fig. 3.
And S2, performing ion implantation on the composite barrier region 14 and part of the channel layer 13 to form an ion implantation region 21. The method specifically comprises the following steps:
first, a first mask layer S1 is formed on the surface of the composite barrier region 14 by using a photolithography process for the first time, and an ion implantation window is defined by using the pattern of the first mask layer S1, as shown in fig. 4 b.
Next, an ion implantation process is used to implant dopant ions into the composite barrier region 14 and a portion of the channel layer 13 through the portion of the wafer 1 not shielded by the first mask layer S1, so as to form an n-type heavily doped ion implantation region 21, as shown in fig. 4 c.
After the ion implantation region 21 is formed, the first mask layer S1 on the surface of the composite barrier region 14 is removed, and the wafer 1 is annealed to activate the dopant ions in the ion implantation region 21.
And S3, removing the composite barrier region 14 and part of the channel layer 13 in the ion implantation region 21, and forming a groove 22 with the width smaller than that of the ion implantation region 21.
First, a second mask layer S2 is formed on the epitaxial wafer by using a photolithography process for the second time, and a groove window is defined by using the second mask layer S2, as shown in fig. 4 d. Specifically, the recess window should be located within the ion implantation region 21 and have a width less than the width of the ion implantation region window.
Next, using an etching process, the composite barrier layer 14 and a portion of the channel layer 13 are removed at a place of the wafer 1 not shielded by the second mask layer S2, and a groove 22 is formed, as shown in fig. 4 e. Specifically, the width of the groove 22 is smaller than the width of the ion implantation region 21, and the depth of the groove 22 is smaller than the depth of the ion implantation region 21, so that the n-type heavily doped ion implantation region 21 is arranged around the groove 22.
S4, depositing metal in the groove 22 to form the ohmic contact electrode 23.
First, a metal material is deposited in the recess 22 to form an ohmic contact electrode metal, as shown in fig. 4 f.
Then, the second mask layer S2 on the surface of the wafer 1 is removed to form the ohmic contact electrode 23, as shown in fig. 4 g.
Finally, annealing the wafer 1 after the ohmic contact electrode 23 is formed, and forming ohmic contact in a two-dimensional electron gas channel between the channel layer 13 and the composite barrier region 14; wherein the temperature of the annealing treatment is 300-900 ℃, the treatment time is 10-300 s, and the treatment environment is one or a combination of vacuum and inert gas.
Please refer to embodiment one, and details of the heterojunction structure obtained by the above preparation method are not repeated in this embodiment.
In the preparation method of the embodiment, the gallium nitride channel layer is implanted with ions, the n-type heavily doped region is formed in the gallium nitride channel layer, the groove is etched, and the ohmic contact metal is deposited in the groove to form the ohmic electrode, so that the ohmic contact electrode and the ion implanted heavily doped region form good contact, and a very low ohmic contact resistance value is obtained. Compared with the traditional ohmic contact structure and the preparation method of directly depositing metal, a groove or ion implantation, the embodiment has obvious advantages for the gallium nitride heterojunction structure with the high-aluminum component aluminum gallium nitrogen or aluminum nitride barrier layer, and can solve the problem that the high-aluminum component aluminum gallium nitrogen or aluminum nitride barrier layer is difficult to form a heavily doped region due to high forbidden bandwidth, so that the gallium nitride heterojunction structure with the high-aluminum component aluminum gallium nitrogen or aluminum nitride barrier layer is difficult to obtain low-resistance ohmic contact. In addition, the preparation method of the ion implantation combined groove structure can reduce the requirements of the groove etching process, thereby widening the process window of the groove technology and realizing high yield.
EXAMPLE III
On the basis of the first and second embodiments, please refer to fig. 5, and fig. 5 is a schematic structural diagram of a diode with a high electron mobility heterojunction structure according to an embodiment of the present invention. The diode with the high electron mobility heterojunction structure comprises a wafer 1, a cathode 2 positioned at one end of the wafer 1 and an anode 3 positioned at the other end of the wafer 1.
The wafer 1 is a wafer with a gallium nitride high-electron-mobility heterojunction structure, and comprises a substrate 11, a composite buffer region 12, a channel layer 13 and a composite barrier region 14 which are sequentially stacked from bottom to top, wherein a two-dimensional electron gas channel is arranged between the channel layer 13 and the composite barrier region 14.
The cathode 2 includes a sub-injection region 21, a groove 22, and an ohmic contact electrode 23. The ion implantation region 21 penetrates the recombination barrier region 14 and is located in the channel layer 13, and the ion implantation region portion located in the channel layer 13 forms n-type high doping. The recess 22 is located in the ion implanted region 21 while the recombination barrier region 14 and a portion of the channel layer 13 in the recess 22 are removed such that the recess 22 extends through the recombination barrier region 14 and is located in the channel layer 13. The ohmic contact electrode 23 fills the groove 22, the bottom and the side thereof are in contact with the ion implantation region 21, and the side of the ohmic contact electrode 23 is in contact with the two-dimensional electron gas channel between the channel layer 13 and the composite barrier region 14.
The anode 3 is located in the composite barrier region 14, embedded in the composite barrier region 14.
For the specific structures of the substrate 11, the composite buffer region 12, the channel layer 13, and the composite barrier region 14, please refer to the first embodiment, which is not described in detail in this embodiment.
In the embodiment, the cathode adopts the ion implantation area 21 to realize n-type high doping in the channel layer, so that the cathode has very low resistivity, the ohmic contact electrode forms good ohmic contact with the two-dimensional electron gas channel between the nearby channel layer 13 and the composite barrier area 14, and the contact resistance is extremely low; in addition, the ohmic contact electrode 23 in the groove 22 is in contact with the n-type highly doped channel layer in the ion implantation region 21, so that good ohmic contact resistance is formed, and the contact resistance is also extremely low; therefore, good ohmic contact with extremely low resistance is formed between the ohmic contact resistor and the two-dimensional electron gas.
Example four
Referring to fig. 6 on the basis of the first and second embodiments, fig. 6 is a schematic structural diagram of a transistor with a high electron mobility heterojunction structure according to an embodiment of the present invention. The transistor with the high electron mobility heterojunction structure comprises a wafer 1, a source electrode 2 positioned at one end of the wafer 1, a drain electrode 3 positioned at the other end of the wafer 1, and a gate electrode 4 positioned between the source electrode 2 and the drain electrode 3.
The wafer 1 is a wafer with a gallium nitride high-electron-mobility heterojunction structure, and comprises a substrate 11, a composite buffer region 12, a channel layer 13 and a composite barrier region 14 which are sequentially stacked from bottom to top, wherein a two-dimensional electron gas channel is arranged between the channel layer 13 and the composite barrier region 14.
The source electrode 2 and the drain electrode 3 each include an injection region 21, a groove 22, and an ohmic contact electrode 23. The ion implantation region 21 penetrates the recombination barrier region 14 and is located in the channel layer 13, and the ion implantation region portion located in the channel layer 13 forms n-type high doping. The recess 22 is located in the ion implanted region 21 while the recombination barrier region 14 and a portion of the channel layer 13 in the recess 22 are removed such that the recess 22 extends through the recombination barrier region 14 and is located in the channel layer 13. The ohmic contact electrode 23 fills the groove 22, the bottom and the side thereof are in contact with the ion implantation region 21, and the side of the ohmic contact electrode 23 is in contact with the two-dimensional electron gas channel between the channel layer 13 and the composite barrier region 14.
The gate electrode 4 is located on the composite barrier region 14.
Further, a dielectric layer is further arranged on the composite barrier region 14, the source electrode 2 and the drain electrode 3 both penetrate through the dielectric layer, and the gate electrode 4 is located on the composite barrier region 14 and the dielectric layer.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A high electron mobility heterojunction structure based on ohmic contacts, comprising: a substrate (11), a composite buffer region (12), a channel layer (13), a composite barrier region (14), an ion implantation region (21), a groove (22), and an ohmic contact electrode (23),
the substrate (11), the composite buffer region (12), the channel layer (13) and the composite barrier region (14) are sequentially laminated;
the ion implantation region (21) penetrates through the composite barrier region (14) and is positioned in the channel layer (13), and the ion implantation region part positioned in the channel layer (13) forms n-type doping;
the recess (22) is located in the ion-implanted region (21) while penetrating the composite barrier region (14) and being located in the channel layer (13);
the ohmic contact electrode (23) fills the groove (22).
2. The ohmic contact-based high electron mobility heterojunction structure according to claim 1, wherein the material of the substrate (11) comprises one or more of high resistivity silicon, semi-insulating silicon carbide, semi-insulating sapphire, semi-insulating diamond, semi-insulating aluminum nitride, and has a thickness of 50-1500 μm.
3. The ohmic contact-based high electron mobility heterojunction structure according to claim 1, wherein the composite buffer region (12) comprises a nucleation layer (121), a transition layer (122) and a core buffer layer (123) stacked in sequence, wherein the nucleation layer (121) is located on the substrate (11).
4. The ohmic contact-based high electron mobility heterojunction structure according to claim 1, wherein the material of the channel layer (13) comprises one or more of gallium nitride, indium gallium nitride, aluminum gallium nitride, and has a thickness of 10-500 nm.
5. The ohmic contact-based high electron mobility heterojunction structure according to claim 1, wherein the composite barrier region (14) comprises an isolation layer (141), a core barrier layer (142) and a cap layer (143) which are sequentially stacked, wherein the isolation layer (141) is located on the channel layer (13).
6. The high electron mobility heterojunction structure based on ohmic contact as claimed in claim 1, wherein the implanted ions of the ion implantation region (21) are one or more of silicon and germanium, and the concentration of the implanted ions is 1 x 1015-1×1022cm-3The depth is 5-1000 nm.
7. The ohmic contact-based high electron mobility heterojunction structure according to claim 1, wherein the material of the ohmic contact electrode (23) comprises one or more of titanium, aluminum, titanium nitride, gold, nickel, tantalum nitride, and has a thickness of 50nm to 1 μm.
8. A preparation method of a high electron mobility heterojunction structure based on ohmic contact is characterized by comprising the following steps:
s1, growing a composite buffer region (12), a channel layer (13) and a composite barrier region (14) on the surface of a substrate (11) in sequence;
s2, carrying out ion implantation on the composite barrier region (14) and part of the channel layer (13) to form an ion implantation region (21);
s3, removing the composite barrier region (14) and part of the channel layer (13) in the ion implantation region (21) to form a groove (22) with the width smaller than that of the ion implantation region (21);
and S4, depositing metal in the groove (22) to form an ohmic contact electrode (23).
9. A diode having a high electron mobility heterojunction structure, comprising: a wafer (1), a cathode (2) at one end of the wafer (1) and an anode (3) at the other end of the wafer (1), wherein,
the wafer (1) comprises a substrate (11), a composite buffer region (12), a channel layer (13) and a composite barrier region (14) which are sequentially stacked;
the cathode (2) comprises a sub-injection region (21), a groove (22) and an ohmic contact electrode (23), the ion injection region (21) penetrates through the composite barrier region (14) and is positioned in the channel layer (13), and the ion injection region part positioned in the channel layer (13) forms n-type high doping; the recess (22) is located in the ion-implanted region (21) while penetrating the composite barrier region (14) and being located in the channel layer (13); the ohmic contact electrode (23) fills the groove (22);
the anode (3) is located in the recombination barrier region (14).
10. A transistor with a high electron mobility heterojunction structure, comprising a wafer (1), a source electrode (2) at one end of the wafer (1), a drain electrode (3) at the other end of the wafer (1), and a gate electrode (4) between the source electrode (2) and the drain electrode (3), wherein,
the wafer (1) comprises a substrate (11), a composite buffer region (12), a channel layer (13) and a composite barrier region (14) which are sequentially stacked;
the source electrode (2) and the drain electrode (3) respectively comprise an injection region (21), a groove (22) and an ohmic contact electrode (23), the ion injection region (21) penetrates through the composite barrier region (14) and is positioned in the channel layer (13), and the ion injection region part positioned in the channel layer (13) forms n-type high doping; the recess (22) is located in the ion-implanted region (21) while penetrating the composite barrier region (14) and being located in the channel layer (13); the ohmic contact electrode (23) fills the groove (22);
the gate electrode (4) is located on the composite barrier region (14).
CN202111070445.3A 2021-09-13 2021-09-13 High-electron-mobility heterojunction structure, preparation method, diode and transistor Pending CN114005867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111070445.3A CN114005867A (en) 2021-09-13 2021-09-13 High-electron-mobility heterojunction structure, preparation method, diode and transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111070445.3A CN114005867A (en) 2021-09-13 2021-09-13 High-electron-mobility heterojunction structure, preparation method, diode and transistor

Publications (1)

Publication Number Publication Date
CN114005867A true CN114005867A (en) 2022-02-01

Family

ID=79921307

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111070445.3A Pending CN114005867A (en) 2021-09-13 2021-09-13 High-electron-mobility heterojunction structure, preparation method, diode and transistor

Country Status (1)

Country Link
CN (1) CN114005867A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010283048A (en) * 2009-06-03 2010-12-16 Nec Corp Heterojunction field-effect transistor and method of manufacturing the same
CN102341897A (en) * 2008-12-31 2012-02-01 英特尔公司 Quantum well mosfet channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains
CN104362181A (en) * 2014-11-03 2015-02-18 苏州捷芯威半导体有限公司 GaN hetero-junction diode device and method for manufacturing same
CN104377239A (en) * 2013-08-12 2015-02-25 富士通株式会社 Semiconductor device and manufacturing method thereof
US20170373179A1 (en) * 2016-06-24 2017-12-28 Cree, Inc. Depletion mode semiconductor devices including current dependent resistance

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102341897A (en) * 2008-12-31 2012-02-01 英特尔公司 Quantum well mosfet channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains
JP2010283048A (en) * 2009-06-03 2010-12-16 Nec Corp Heterojunction field-effect transistor and method of manufacturing the same
CN104377239A (en) * 2013-08-12 2015-02-25 富士通株式会社 Semiconductor device and manufacturing method thereof
CN104362181A (en) * 2014-11-03 2015-02-18 苏州捷芯威半导体有限公司 GaN hetero-junction diode device and method for manufacturing same
US20170373179A1 (en) * 2016-06-24 2017-12-28 Cree, Inc. Depletion mode semiconductor devices including current dependent resistance

Similar Documents

Publication Publication Date Title
US7919791B2 (en) Doped group III-V nitride materials, and microelectronic devices and device precursor structures comprising same
US5311055A (en) Trenched bipolar transistor structures
TWI436478B (en) Tunnel field effect transistor and method of manufacturing same
CN104094417A (en) Method of fabricating a gallium nitride P-I-N diode using implantation
CN110148625B (en) Gallium oxide vertical junction field effect transistor and preparation method thereof
CN112133749A (en) P-type cap layer enhanced HEMT device and preparation method thereof
CN113421914A (en) P-type metal oxide current blocking layer Ga2O3Vertical metal oxide semiconductor field effect transistor
WO2022199309A1 (en) Hemt device having p-gan cap layer and preparation method therefor
CN111384171B (en) High-channel mobility vertical UMOSFET device and preparation method thereof
CN114899227A (en) Enhanced gallium nitride-based transistor and preparation method thereof
CN109950323A (en) The III group-III nitride diode component and preparation method thereof for the superjunction that polarizes
EP0180457A2 (en) Semiconductor integrated circuit device and method for producing same
CN115775730B (en) GaN Schottky diode with quasi-vertical structure and preparation method thereof
CN116959991A (en) Field effect transistor and preparation method thereof and method for preparing groove structure in drift layer of field effect transistor
CN108878509B (en) Gallium nitride transistor and method for manufacturing same
CN111640795A (en) Gallium nitride high-frequency transistor with arc-shaped gate electrode and manufacturing method
CN116314349A (en) GaN-based power Schottky diode with P-type two-dimensional material intercalation and preparation process thereof
CN114171597B (en) SiC MOSFET device with low source contact resistance and preparation method thereof
CN112201689A (en) Field effect transistor based on III-group nitride heterojunction and preparation method thereof
CN114005867A (en) High-electron-mobility heterojunction structure, preparation method, diode and transistor
CN114725022A (en) Based on GaOxPreparation method of-GaN CMOS inverter
CN113903802A (en) Array strip-based enhancement type switch transistor and manufacturing method thereof
US9985159B2 (en) Passivated contact formation using ion implantation
CN111508839A (en) Manufacturing method of high-voltage enhanced GaN power HEMT device resistant to single event failure
CN111211176A (en) Gallium nitride-based heterojunction integrated device structure and manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20220201