CN111640795A - Gallium nitride high-frequency transistor with arc-shaped gate electrode and manufacturing method - Google Patents
Gallium nitride high-frequency transistor with arc-shaped gate electrode and manufacturing method Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention relates to a gallium nitride high-frequency transistor with an arc-shaped gate electrode and a manufacturing method thereof, wherein the gallium nitride high-frequency transistor comprises the following steps: a wafer structure; the wafer structure comprises a gate electrode, a source electrode and a drain electrode, wherein the gate electrode, the source electrode and the drain electrode are arranged on the wafer structure, the gate electrode comprises a gate pin and a gate head arranged on the gate pin, the volume of the gate head is larger than that of the gate pin, and the joint of the gate head and the gate pin is arc-shaped. The wafer structure is a gallium nitride high-mobility transistor epitaxial structure and comprises a substrate layer, a composite buffer region, a channel layer and a composite barrier region, wherein a gate electrode is of an arc-shaped structure, so that the working frequency of a device can be improved, the breakdown voltage of the device can be increased, and the device has lower on-resistance and higher output current.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a gallium nitride high-frequency transistor with an arc-shaped gate electrode and a manufacturing method thereof.
Background
With the development of microelectronic technology, third generation wide bandgap semiconductor materials represented by gallium nitride have larger bandgap, higher critical breakdown electric field, higher electron saturation drift velocity, stable chemical properties, high temperature resistance, radiation resistance and other physical properties, electronic devices manufactured by using gallium nitride materials can further reduce chip area, improve working frequency, improve working temperature, reduce on-resistance, improve breakdown voltage and the like, and gallium nitride materials have great potential in the aspect of manufacturing microwave devices. Gallium nitride and aluminum gallium nitrogen, indium aluminum nitrogen and the like which have the same material system with the gallium nitride have high polarization coefficients, a heterostructure formed by the gallium nitride and the aluminum gallium nitrogen or the indium aluminum nitrogen with the forbidden band width larger than that of the gallium nitride can form two-dimensional electron gas better, and more than 1500cm can be obtained at room temperature2The electron mobility of the/V.s reaches 1.5 × 10cm7Saturated electron velocity sum of more than 1 × 10 per second13cm-2The two-dimensional electron gas concentration of the semiconductor device, so that high-speed Schottky Barrier Diode (SBD) and High Electron Mobility Transistor (HEMT) devices developed based on gallium nitride materials can have lower on-resistance and higher output current. In addition, the higher critical breakdown field strength of the gallium nitride material can enable the electronic device to have higher breakdown voltageThe voltage is passed, so that the device can work under higher working voltage, the microwave output power density is higher, and compared with a silicon or gallium arsenide microwave transistor with the same output power, the gallium nitride transistor has higher power addition efficiency and lower energy loss.
Important factors affecting the highest oscillation frequency are the gate leg length and the metal resistance of the gate electrode, which is inversely proportional to the cross-sectional area of the gate metal, that is, the length of the gate electrode. Increasing the operating frequency of the transistor requires a reduction in the gate leg length, which, however, increases the metal resistance of the gate electrode. At present, the shape of the gate electrode is designed to improve the operating frequency and breakdown voltage of the gan high-frequency transistor by the following main methods: the asymmetric gate electrode is characterized in that the voltage drop of the transistor in a normal working state is mainly concentrated between the gate and the drain, so that the length of a gate head of the T-shaped gate electrode close to the drain end is increased, the field plate effect of the T-shaped gate electrode can be enhanced, the electric field peak intensity of the gate electrode close to the drain end is effectively reduced, and the breakdown voltage is increased. However, this method has disadvantages in that the length of the gate head becomes wide and an additional parasitic capacitance becomes large, thereby affecting the cutoff frequency and the highest oscillation frequency. The gravity center deviation of the asymmetric gate type gate electrode also makes the gate electrode manufactured by the double-layer glue stripping manufacturing method easier to collapse, thereby influencing the manufacturing yield of the gate electrode. The increase of the width of the gate head can also increase the gate-drain distance, thereby enhancing the drain access resistance of the device and influencing the cut-off frequency, the on-resistance and the power added efficiency of the device. And in order to increase the suspension height of the gate head, reduce the parasitic capacitance between the gate head of the T-shaped gate electrode and the conductive channel of the microwave device and keep the stability of the T-shaped gate electrode, the gate electrode can be made into a Y-shaped structure, namely the suspension part of the gate head is not horizontal but inclined upwards. The Y-shaped gate electrode effectively reduces high parasitic capacitance brought by the T-shaped gate electrode. The disadvantage is that the breakdown voltage is improved compared with the T-shaped gate, but the electric field intensity peak of the edge of the gate electrode is still higher, and the breakdown voltage is still lower. Therefore, most high frequency transistors use a technique called "T-gate" to add a gate head to the gate leg, thereby achieving a thinner gate leg while maintaining a wider gate head and lower metal resistance of the gate electrode.
The introduction of the T-shaped gate also has some disadvantages, and the wider gate head structure introduces additional parasitic capacitance, thereby causing the cut-off frequency and the highest oscillation frequency of the transistor to be reduced; to reduce the additional parasitic capacitance, the height of the gate leg needs to be increased, which can make the gate electrode unstable and easily collapse.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a gallium nitride high frequency transistor with an arc-shaped gate electrode and a manufacturing method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
a gallium nitride high-frequency transistor having an arc-shaped gate electrode, comprising:
a wafer structure;
the wafer structure comprises a gate electrode, a source electrode and a drain electrode, wherein the gate electrode, the source electrode and the drain electrode are arranged on the wafer structure, the gate electrode comprises a gate pin and a gate head arranged on the gate pin, the volume of the gate head is larger than that of the gate pin, and the joint of the gate head and the gate pin is arc-shaped.
In one embodiment of the invention, the cross-sectional area from the top surface of the gate head to the bottom surface of the gate head is gradually reduced, and the side surface of the gate head is arc-shaped.
In one embodiment of the invention, the junction between the top surface of the grid head and the grid head is arc-shaped.
In one embodiment of the present invention, the cross-sectional area from the top surface of the grid leg to the bottom surface of the grid leg is gradually reduced, and the side surface of the grid leg is arc-shaped.
In one embodiment of the invention, the height of the gate head is greater than or equal to the height of the gate foot.
In one embodiment of the invention, the height of the gate pin is 10 nm-300 nm.
In one embodiment of the invention, the height of the gate head is 10nm to 800 nm.
In one embodiment of the present invention, the gate electrode is made of one of nickel/gold, titanium/gold, or oxide/nickel/gold.
In one embodiment of the present invention, the source electrode is made of one of titanium/aluminum/metal/gold, titanium/metal or tantalum/metal, and the drain electrode is made of one of titanium/aluminum/metal/gold, titanium/metal or tantalum/metal.
A method for manufacturing a gallium nitride high-frequency transistor with an arc-shaped gate electrode comprises the following steps:
manufacturing a source electrode (3) and a drain electrode (4) on the wafer structure (1);
coating a first electron beam photoresist (1a) on the wafer structure (1);
coating a second electron beam photoresist (1b) on the first electron beam photoresist (1a), wherein the photosensitivity of the second electron beam photoresist (1b) is greater than that of the first electron beam photoresist (1 a);
exposing, developing and baking the wafer structure (1) coated with the first electron beam photoresist (1a) and the second electron beam photoresist (1b) twice, and forming a gate electrode structure (1c) on the first electron beam photoresist (1a) and the second electron beam photoresist (1 b);
depositing a gate electrode material in the gate electrode structure (1 c);
and stripping the first electron beam photoresist (1a) and the second electron beam photoresist (1b) to obtain a gate electrode (2), wherein the gate electrode (2) comprises a gate pin (21) and a gate head (22) arranged on the gate pin (21), the volume of the gate head (22) is larger than that of the gate pin (21), and the joint of the gate head (22) and the gate pin (21) is arc-shaped.
The invention has the beneficial effects that:
the invention comprises a wafer structure, a gate electrode, a source electrode and a drain electrode, wherein the gate electrode, the source electrode and the drain electrode are all arranged on the wafer structure, the gate electrode comprises a gate head and a gate pin, the gate head is arranged on the gate pin, the volume of the gate head is larger than that of the gate pin, and the joint of the gate head and the gate pin is arc-shaped.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic cross-sectional view of a GaN high-frequency transistor having an arc-shaped gate electrode according to an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view of a gate electrode of a GaN high-frequency transistor having an arc-shaped gate electrode according to an embodiment of the invention;
FIG. 3 is a schematic structural diagram of a wafer structure of a GaN high-frequency transistor with an arc-shaped gate electrode according to an embodiment of the invention;
FIG. 4 is a schematic structural diagram of another wafer structure of a GaN high-frequency transistor with an arc-shaped gate electrode according to an embodiment of the invention;
FIGS. 5a to 5h are schematic diagrams illustrating a method for fabricating a wafer structure of a GaN high-frequency transistor having an arc-shaped gate electrode according to an embodiment of the invention;
fig. 6 to fig. 13 are schematic diagrams of a method for manufacturing a gate electrode of a gan high-frequency transistor having an arc-shaped gate electrode according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1 to 4, fig. 1 is a schematic cross-sectional view of a gan high-frequency transistor with an arc-shaped gate electrode according to an embodiment of the present invention, fig. 2 is a schematic cross-sectional view of a gate electrode of a gan high-frequency transistor with an arc-shaped gate electrode according to an embodiment of the present invention, fig. 3 is a schematic structural view of a wafer structure of a gan high-frequency transistor with an arc-shaped gate electrode according to an embodiment of the present invention, and fig. 4 is a schematic structural view of a wafer structure of another gan high-frequency transistor with an arc-shaped gate electrode according to an embodiment of the present invention. The structure includes:
a wafer structure 1;
the wafer structure comprises a gate electrode 2, a source electrode 3 and a drain electrode 4, wherein the gate electrode 2, the source electrode 3 and the drain electrode 4 are arranged on the wafer structure 1, the gate electrode 2 comprises a gate pin 21 and a gate head 22 arranged on the gate pin 21, the volume of the gate head 22 is larger than that of the gate pin 21, and the joint of the gate head 22 and the gate pin 21 is arc-shaped.
Further, the cross-sectional area from the top surface of the gate head 22 to the bottom surface of the gate head 22 is gradually reduced, and the side surface of the gate head 22 is arc-shaped.
Further, the junction between the top surface of the grid head 22 and the grid head 22 is arc-shaped.
Further, the cross-sectional area from the top surface of the grid leg 21 to the bottom surface of the grid leg 21 is gradually reduced, and the side surface of the grid leg 21 is arc-shaped.
Further, the height of the gate head 22 is greater than or equal to the height of the gate foot 21.
Further, the height of the gate leg 21 is 10nm to 300 nm.
Further, the height of the gate head 22 is 10nm to 800 nm.
Further, the material of the gate electrode 2 is one of nickel/gold, titanium/gold, or oxide/nickel/gold.
Further, the material of the source electrode 3 is one of titanium/aluminum/any metal/gold, titanium/any metal or tantalum/any metal, and the material of the drain electrode 4 is one of titanium/aluminum/any metal/gold, titanium/any metal or tantalum/any metal.
The gate electrode 2, the source electrode 3 and the drain electrode 4 are arranged on the wafer structure 1, the gate electrode 2 comprises a gate head 22 and a gate pin 21, the gate head 22 is arranged on the gate pin 21, and the volume of the gate head 22 is larger than that of the gate pin 21. The structure of the gate electrode 2 is an arc-shaped structure, specifically, the joint of the gate head 22 and the gate leg 21 is arc-shaped, the joint of the top surface of the gate head 22 and the gate head 22 is arc-shaped, the side surfaces of the gate head 22 and the gate leg 21 are arc-shaped, the volume of the gate head 22 is larger than that of the gate leg 21, the cross-sectional area from the top surface of the gate head 22 to the bottom surface of the gate head 22 is gradually reduced, the cross-sectional area from the top surface of the gate leg 21 to the bottom surface of the gate leg 21 is gradually reduced, the height h1 of the gate head 22 is larger than or equal to the height h2 of the gate leg 21, the height h2 of the gate leg is 10nm to 300nm, and. The material of the gate electrode 2 is one of nickel/gold, titanium/gold or oxide/nickel/gold, and the metal layers in each material are sequentially arranged from bottom to top. The material of the source electrode 3 is one of titanium/aluminum/any metal/gold, titanium/any metal or tantalum/any metal, the metal layers in each material are sequentially arranged from bottom to top, and the height is 10 nm-800 nm. The drain electrode 4 is made of one of titanium/aluminum/any metal/gold, titanium/any metal or tantalum/any metal, and metal layers in each material are sequentially arranged from bottom to top and have a height of 10 nm-800 nm.
Preferably, the gate electrode 2 is made of nickel/gold, nickel is deposited firstly, the growth thickness is 50nm, gold is deposited later, the growth thickness is 300nm, the height h2 of the gate pin 21 is 50nm, and the height h1 of the gate head 22 is 300 nm; the material of the source electrode 3 is titanium/aluminum/nickel/gold, the deposition sequence is titanium, aluminum, nickel and gold from bottom to top, and the growth thickness of each layer of metal is 20nm, 120nm, 40nm and 50 nm; the drain electrode 4 is made of titanium/aluminum/nickel/gold, the deposition sequence is titanium, aluminum, nickel and gold from bottom to top, and the growth thickness of each layer of metal is 20nm, 120nm, 40nm and 50 nm.
The main performance indexes of the gallium nitride high-frequency transistor comprise output current, highest oscillation frequency, breakdown voltage and the like, and an important index for showing the high-frequency amplification performance of the transistor is the highest oscillation frequency, wherein the higher the highest oscillation frequency is, the higher the gain of the transistor under a specific frequency is. The length of the gate leg 21 and the metal resistance of the gate electrode 2 are important factors influencing the highest oscillation frequency, the metal resistance of the gate electrode 2 is inversely proportional to the cross-sectional area of the gate metal, namely inversely proportional to the length of the gate electrode 2, and the arc-shaped structure of the gate electrode 2 can improve the working frequency of the transistor, increase the breakdown voltage of the device and enable the transistor to have lower on-resistance and higher output current.
The wafer structure 1 of the present invention is a gan high mobility transistor epitaxial structure, which is a prior art. The wafer structure 1 includes: a substrate layer 11; a composite buffer region 12 disposed on the substrate layer 11; a channel layer 13 disposed on the composite buffer region 12; and a composite barrier region 14 disposed on the channel layer 13.
The substrate layer 11 is made of high-resistance silicon, the doping type is N type or P type, the resistivity is 3000 omega-30000 omega-cm, the crystal orientation is <111>, and the substrate layer 11 can also be made of semi-insulating silicon carbide, semi-insulating sapphire, semi-insulating diamond or semi-insulating aluminum nitride. The wafer structure 1 further includes a nucleation layer 110, the nucleation layer 110 is disposed on the substrate layer 11, and is made of aluminum nitride and grown to a thickness of 200 nm.
The composite buffer region 12 includes a transition region and a core buffer region, and may further include a back barrier layer, the core buffer region is disposed on the transition region, the back barrier layer is disposed on the core buffer region, and the core buffer region is made of group III nitride. The transition region is composed of a plurality of transition layers 121 with different compositions, the material of each transition layer 121 is aluminum gallium nitride, the transition region can also comprise a superlattice layer 122 or a superlattice transition layer 123, the material of the superlattice layer is aluminum nitride/gallium nitride, aluminum nitride is grown firstly, and gallium nitride is grown secondly. The core buffer region is made of gallium nitride, aluminum gallium nitride or aluminum nitride, and further comprises a buffer layer 124 made of gallium nitride and grown to a thickness of 1 μm. The back barrier layer is made of aluminum gallium nitride, indium gallium nitride or aluminum nitride, and the growth thickness is larger than 1 nm.
The channel layer 13 is disposed on the composite buffer region 12, and is made of gallium nitride, indium gallium nitride or aluminum gallium nitride, and the growth thickness is greater than 10 nm.
The composite barrier region 14 is disposed on the channel layer 13, and includes a core barrier layer 141, and may further include an isolation layer 142 or a cap layer 143, the cap layer 143 is disposed on the core barrier layer 141, and the core barrier layer 141 is disposed on the isolation layer 142. The core barrier layer 141 is made of aluminum gallium nitride, the aluminum component is 0.2-0.4, and the growth thickness is 10-30 nm; the core barrier layer 141 can also be made of indium aluminum nitrogen, the indium component is 0.1-0.2, and the growth thickness is 5-30 nm; the core barrier layer 141 may also be aluminum nitride and may be grown to a thickness of 2nm to 10 nm. The isolation layer 142 is made of aluminum nitride and has a growth thickness of 0.5nm to 1.5 nm. The cap layer 143 is made of gallium nitride and has a growth thickness of 1nm to 3 nm; the cap layer 143 may also be silicon nitride and may be grown to a thickness of 1nm to 10 nm. A two-dimensional electron gas is formed at the interface of the channel layer 13 and the recombination barrier region 14, which may serve as a conductive channel of the transistor.
Preferably, the substrate layer 11 is made of high-resistance silicon with a resistance of 5000 Ω, cm, a crystal orientation of <111>, a size of 8 inches, and a thickness of 725 μm; the nucleating layer 110 is made of aluminum nitride and has a thickness of 200 nm; the superlattice transition layer 123 is made of aluminum nitride/gallium nitride and has a thickness of 1 μm; the buffer layer 124 is made of gallium nitride and doped with iron, and the thickness of the buffer layer is 1 μm; the material of the channel layer 13 is gallium nitride, and the thickness is 300 nm; the isolation layer 142 is made of aluminum nitride and has a thickness of 1 nm; the back barrier layer is made of aluminum gallium nitride (AlGaN), the aluminum component is 0.25, and the thickness is 20 nm; the cap layer 143 is made of gallium nitride and has a thickness of 3 nm.
Referring to fig. 5a to 5h, fig. 5a to 5h are schematic diagrams illustrating a method for fabricating a wafer structure of a gan high frequency transistor having an arc-shaped gate electrode according to an embodiment of the present invention. The preparation method of the wafer structure 1 comprises the following steps:
s11, growing a nucleation layer 110 with the thickness of 200nm on the substrate layer 11 by using MOCVD equipment and technology, wherein the substrate layer 11 is made of high-resistance silicon, and the nucleation layer 110 is made of aluminum nitride;
s12, growing a superlattice transition layer 123 with the thickness of 1 μm on the nucleation layer 110, wherein the superlattice transition layer 123 is made of aluminum nitride/gallium nitride;
s13, growing a buffer layer 124 with the thickness of 1 μm on the superlattice transition layer 123, wherein the buffer layer 124 is made of gallium nitride;
s14, growing a channel layer 13 with the thickness of 300nm on the buffer layer 124, wherein the channel layer 13 is made of gallium nitride;
s15, growing a 1nm isolating layer 142 on the channel layer 13, wherein the isolating layer 142 is made of aluminum nitride;
s16, growing a 20nm core barrier layer 141 on the isolation layer 142, wherein the core barrier layer 141 is made of gallium nitride;
and S17, growing a cap layer 143 with the thickness of 3nm on the core barrier layer 141, wherein the material of the cap layer 143 is gallium nitride.
MOCVD Deposition (Metal-organic Chemical Vapor Deposition) is a new Vapor phase epitaxy growth technique developed on the basis of Vapor phase epitaxy growth. It uses organic compound of III group and II group elements and hydride of V group and VI group elements as crystal growth raw material, and adopts thermal decomposition reaction mode to make gas-phase epitaxy on the substrate layer so as to grow various III-V group and II-VI group compound semiconductors and their thin-layer monocrystal materials of multicomponent solid solution.
Example two
Referring to fig. 6 to 13, fig. 6 to 13 are schematic diagrams illustrating a method for manufacturing a gate electrode of a gan high-frequency transistor having an arc-shaped gate electrode according to an embodiment of the present invention. The method comprises the following steps:
s21, the source electrode 3 and the drain electrode 4 are fabricated on the wafer structure 1.
The source electrode 3 and the drain electrode 4 are manufactured by adopting a stripping process, the stripping process is the prior art, the materials of the source electrode 3 and the drain electrode 4 are titanium/aluminum/nickel/gold, the deposition sequence is titanium, aluminum, nickel and gold, the thickness of each layer of metal is 20nm, 120nm, 40nm and 50nm in sequence, the annealing temperature is 825 ℃, and the time is 30 s.
S22, coating a first electron beam photoresist 1a on the wafer structure 1;
the material of the first electron beam resist 1a is PMMA, and the thickness is 100 nm.
S23, coating a second electron beam photoresist 1b on the first electron beam photoresist 1a, wherein the photosensitivity of the second electron beam photoresist 1b is higher than that of the first electron beam photoresist 1 a;
the material of the second electron beam photoresist 1b is P (MMA-MAA), the thickness is 600nm, the coating thickness of the second electron beam photoresist 1b is larger than that of the first electron beam photoresist 1a, and the photosensitivity of the second electron beam photoresist 1b is larger than that of the first electron beam photoresist 1 a.
S24, exposing, developing and baking the wafer structure 1 coated with the first electron beam resist 1a and the second electron beam resist 1b twice, and forming a gate electrode structure 1c on the first electron beam resist 1a and the second electron beam resist 1 b;
carrying out exposure treatment twice on the wafer structure 1 coated with the first electron beam photoresist 1a and the second electron beam photoresist 1b by adopting electron beam lithography equipment, wherein the voltage of an electron beam is 100kV, the current of the electron beam is 0.2nA, the width of an exposure area is 80nm, and the dose is 1000C/cm during exposure for the first time-2The first electron beam photoresist 1a and the second electron beam photoresist 1b are subjected to decomposition reaction in an exposure area with the width of 80 nm; in the second exposure, the voltage of the electron beam was 100kV, the current of the electron beam was 1nA, the exposure field width was 500nm, and the dose was 200C/cm-2The second electron beam resist 1b undergoes a decomposition reaction in an exposed region having a width of 500 nm.
Then carrying out development treatment, wherein the ratio of the developing solution is MIBK: IPA 1: 3. the developing time is 1m, and the exposed first electron beam photoresist 1a and the exposed second electron beam photoresist 1b are dissolved by using a developing solution to obtain a T-shaped groove;
and finally, baking at the temperature of 200 ℃ for 30m, and softening the first electron beam photoresist 1a and the second electron beam photoresist 1b which are subjected to development treatment to form T-shaped grooves to obtain an arc-shaped structure.
The first electron beam photoresist 1a and the second electron beam photoresist 1b after exposure, development and baking for two times obtain arc-shaped grooves, the groove part in the first electron beam photoresist 1a forms a gate pin 21, and the groove part in the second electron beam photoresist 1b forms a gate head 22.
S25, depositing a gate electrode material deposition in the gate electrode structure 1 c;
and depositing gate electrode materials in the arc-shaped grooves of the baked first electron beam photoresist 1a and the baked second electron beam photoresist 1b, wherein the gate electrode 2 is made of one of nickel/gold, titanium/gold or oxide/nickel/gold, and metal layers in each material are sequentially arranged from bottom to top. Preferably, the gate electrode 2 is made of nickel/gold, nickel is deposited first, the growth thickness is 50nm, gold is deposited later, the growth thickness is 300nm, and a gate electrode structure 1c is obtained, wherein the height h1 of the gate head 22 is 300nm, and the height h2 of the gate foot 21 is 50 nm.
S26, stripping the first electron beam photoresist 1a and the second electron beam photoresist 1b to obtain a gate electrode 2, wherein the gate electrode 2 comprises a gate pin 21 and a gate head 22 arranged on the gate pin 21, the volume of the gate head 22 is larger than that of the gate pin 21, and the joint of the gate head 22 and the gate pin 21 is arc-shaped;
after the deposition of the gate electrode material is finished, the first electron beam photoresist 1a and the second electron beam photoresist 1b outside the gate electrode material are stripped to obtain a gate electrode 2, the gate electrode 2 comprises a gate pin 21 and a gate head 22 arranged on the gate pin 21, the volume of the gate head 22 is larger than that of the gate pin 21, and the joint of the gate head 22 and the gate pin 21 is arc-shaped.
And S26, manufacturing a source electrode 3 and a drain electrode 4 on the wafer structure 1.
The source electrode 3 and the drain electrode 4 are manufactured by adopting a stripping process, the stripping process is the prior art, the materials of the source electrode 3 and the drain electrode 4 are titanium/aluminum/nickel/gold, the deposition sequence is titanium, aluminum, nickel and gold, the thickness of each layer of metal is 20nm, 120nm, 40nm and 50nm in sequence, the annealing temperature is 825 ℃, and the time is 30 s.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention; thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A gallium nitride high-frequency transistor having an arc-shaped gate electrode, comprising:
a wafer structure (1);
the wafer structure comprises a gate electrode (2), a source electrode (3) and a drain electrode (4), wherein the gate electrode (2), the source electrode (3) and the drain electrode (4) are arranged on the wafer structure (1), the gate electrode (2) comprises a gate pin (21) and a gate head (22) arranged on the gate pin (21), the volume of the gate head (22) is larger than that of the gate pin (21), and the joint of the gate head (22) and the gate pin (21) is arc-shaped.
2. The gallium nitride high-frequency transistor with an arc-shaped gate electrode according to claim 1, characterized in that the cross-sectional area from the top surface of the gate head (22) to the bottom surface of the gate head (22) is gradually reduced, and the side surface of the gate head (22) is arc-shaped.
3. The gallium nitride high-frequency transistor with an arc-shaped gate electrode according to claim 2, characterized in that the junction of the top surface of the gate head (22) and the gate head (22) is arc-shaped.
4. The gallium nitride high-frequency transistor with an arc-shaped gate electrode according to claim 2, characterized in that the cross-sectional area from the top surface of the gate leg (21) to the bottom surface of the gate leg (21) is gradually reduced, and the side surface of the gate leg (21) is arc-shaped.
5. The gallium nitride high-frequency transistor with an arc-shaped gate electrode according to claim 1, characterized in that the height of the gate head (22) is equal to or greater than the height of the gate foot (21).
6. The gallium nitride high-frequency transistor with an arc-shaped gate electrode according to claim 5, characterized in that the height of the gate leg (21) is 10nm to 300 nm.
7. The gallium nitride high-frequency transistor with an arc-shaped gate electrode according to claim 5, characterized in that the height of the gate head (22) is 10nm to 800 nm.
8. The gallium nitride high-frequency transistor with an arc-shaped gate electrode according to claim 1, characterized in that the material of the gate electrode (2) is one of nickel/gold, titanium/gold or oxide/nickel/gold.
9. The gallium nitride high-frequency transistor with an arc-shaped gate electrode according to claim 1, wherein the source electrode (3) is made of one of titanium/aluminum/random metal/gold, titanium/random metal or tantalum/random metal, and the drain electrode (4) is made of one of titanium/aluminum/random metal/gold, titanium/random metal or tantalum/random metal.
10. A method for manufacturing a gallium nitride high-frequency transistor with an arc-shaped gate electrode is characterized by comprising the following steps:
manufacturing a source electrode (3) and a drain electrode (4) on the wafer structure (1);
coating a first electron beam photoresist (1a) on the wafer structure (1);
coating a second electron beam photoresist (1b) on the first electron beam photoresist (1a), wherein the photosensitivity of the second electron beam photoresist (1b) is greater than that of the first electron beam photoresist (1 a);
exposing, developing and baking the wafer structure (1) coated with the first electron beam photoresist (1a) and the second electron beam photoresist (1b) twice, and forming a gate electrode structure (1c) on the first electron beam photoresist (1a) and the second electron beam photoresist (1 b);
depositing a gate electrode material in the gate electrode structure (1 c);
and stripping the first electron beam photoresist (1a) and the second electron beam photoresist (1b) to obtain a gate electrode (2), wherein the gate electrode (2) comprises a gate pin (21) and a gate head (22) arranged on the gate pin (21), the volume of the gate head (22) is larger than that of the gate pin (21), and the joint of the gate head (22) and the gate pin (21) is arc-shaped.
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