CN111508839A - Manufacturing method of high-voltage enhanced GaN power HEMT device resistant to single event failure - Google Patents
Manufacturing method of high-voltage enhanced GaN power HEMT device resistant to single event failure Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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Abstract
The invention discloses a manufacturing method of a high-voltage enhanced GaN power HEMT device capable of resisting single event failure, and belongs to the technical field of power switch devices. Providing an epitaxial substrate, and forming an AlN nucleating layer and a GaN buffer layer on the epitaxial substrate; manufacturing a selective back barrier buried layer on the GaN buffer layer; continuing epitaxial growth of non-doped GaN channel layer and AlxGa1‑xAn N barrier layer and a p-type GaN-Mg layer; wherein x is 15-25%; etching the p-type GaN and Mg layers outside the grid region to form the grid region; SiN is deposited on the surface; performing source/drain electrode metal deposition and defining a source/drain electrode by photoetching, and performing grid electrode metal deposition and defining a grid electrode by photoetching; and finishing the metal interconnection process. By removing the back barrier layer below the gate region, accumulation of holes below the gate region caused by single particles can be reduced, and improvementThe single event failure resistance of the enhancement mode p-type grid GaN HEMT device is particularly suitable for high-voltage grade devices with the voltage of more than 200V.
Description
Technical Field
The invention relates to the technical field of power switch devices, in particular to a manufacturing method of a high-voltage enhanced GaN power HEMT device capable of resisting single event failure.
Background
The development of wide bandgap semiconductors brings a new generation of power switching devices to the power electronics field. As a typical representative of third-generation wide bandgap semiconductor materials, GaN has the characteristics of more excellent physical properties than Si, wider forbidden bandwidth, higher critical breakdown electric field, higher electron saturation drift velocity, higher ultimate operating temperature, small dielectric constant, good chemical stability and the like, is an excellent semiconductor material for high-frequency, high-temperature, high-voltage and high-power applications, and has wide market prospect. With the development of SiC power devices, GaN power high electron mobility transistors are developing in the microwave and millimeter wave field and enter the development stage of application innovation in the high frequency switch of power electronics.
The GaN high electron mobility transistor with the AlGaN/GaN heterostructure has low on-resistance and high working frequency, and can effectively improve power conversion efficiency and power density. The improvement of operating frequency can effectively reduce inductance, electric capacity and transformer size, improves power conversion efficiency, and then can also reduce the size of radiator. Therefore, the GaN power device has great advantages in the aspects of preparing small-size and high-efficiency power supply components, and can effectively reduce the emission cost of satellites and deep space exploration equipment and simultaneously expand the remote function.
Unlike the relatively mature GaN RF devices, GaN power switching devices require the development of enhanced (normally off) technology in the power electronics field to improve operational safety and ease of driving. At present, the enhanced GaN-based HEMT power device technology mainly has four types: p-type gate technology, cascode composite device technology, F ion implantation technology and groove gate MOSFET technology. The first two technologies have higher maturity, and the p-type gate enhanced GaN device is a single device, can exert the high-speed switching characteristic of GaN, and is a main technical scheme of the current GaN power switch product.
In the space radiation environment, high-energy particles and cosmic rays can have great influence on electrical parameters of electronic devices, and even can directly cause the devices to permanently fail. In view of the research results of GaN power devices at home and abroad, the GaN HEMT has good capability of resisting total dose and displacement damage effect, but for high-voltage devices, the single event effect is a key factor influencing the space application of the high-voltage devices. The single event effect is that the incident high-energy particles generate high-density electron hole pairs in the device to generate non-equilibrium carriers, which affect the electric field distribution of the high-voltage device, so that the device is burnt by single events under the normal rated voltage. Due to new characteristics of a process, a device structure and the like, the p-type grid GaN power device is sensitive to a single event effect, shows a charge collection mechanism different from that of a silicon power MOSFET device, and has few research reports about a GaN HEMT single event failure reinforcing method.
Disclosure of Invention
The invention aims to provide a manufacturing method of a high-voltage enhanced GaN power HEMT device capable of resisting single event failure, and the method is used for solving the problem that the conventional GaN high-voltage device is easily influenced by a single event effect, so that the device is burnt.
In order to solve the technical problem, the invention provides a manufacturing method of a high-voltage enhanced GaN power HEMT device capable of resisting single event failure, which comprises the following steps:
providing an epitaxial substrate, and forming an AlN nucleating layer and a GaN buffer layer on the epitaxial substrate;
manufacturing a selective back barrier buried layer on the GaN buffer layer;
continuing epitaxial growth of non-doped GaN channel layer and AlxGa1-xAn N barrier layer and a p-type GaN-Mg layer; wherein x is 15-25%;
etching the p-type GaN and Mg layers outside the grid region to form the grid region; SiN is deposited on the surface;
performing source/drain electrode metal deposition and defining a source/drain electrode by photoetching, and performing grid electrode metal deposition and defining a grid electrode by photoetching;
and finishing the metal interconnection process.
Optionally, the method for manufacturing the selective back barrier layer on the GaN buffer layer includes:
forming a back barrier layer on the GaN buffer layer;
removing part of the back barrier layer to form a region below the gate; the area without the back barrier layer covers the grid area and is biased to the source electrode;
and
epitaxially growing a non-doped GaN buffer layer, gluing and exposing a graphic window, and forming a back barrier layer in a region below the grid by ion implantation doping acceptor type impurities; activation of the implanted impurity and lattice repair are accomplished by annealing.
Optionally, forming a back barrier layer on the GaN buffer layer, removing a portion of the back barrier layer, and forming a region below the gate includes:
synchronously doping acceptor type impurities during epitaxial growth to form a GaN: C or GaN: Fe or GaN: Mg back barrier layer with the impurity concentration of 1016～1017cm-3(ii) a Or epitaxially growing AlxGa1-xN is used as a back barrier layer, and x is 5 to 10 percent;
removing part of the back barrier layer by dry etching through gluing and exposing a pattern window; and then epitaxially and non-doping GaN fills the groove formed by etching below the grid.
Optionally, the thickness of the GaN channel layer is 1-2 μm, and the Al isxGa1-xThe thickness of the N barrier layer is 15-25 nm, and the thickness of the p-type GaN-Mg layer is 100-200 nm.
Optionally, the epitaxial substrate is Si or SiC.
Optionally, the AlN nucleating layer is 50-200 nm thick, and the GaN buffer layer is 1-3 μm thick.
The invention has the following beneficial effects:
(1) by removing the back barrier layer below the grid region, the accumulation of holes below the grid region caused by single particles can be reduced, and the single particle failure resistance of the enhanced p-type grid GaN HEMT device is improved, particularly for high-voltage-level devices with voltage of more than 200V;
(2) the internal electric field of the high-voltage GaN HEMT device in an off state is highly non-uniformly distributed, the back barrier layer plays a role in improving the transverse (grid-drain) uniformity of the electric field, but only the back barrier layer below the drift region plays a main role, so that the back barrier layer below the grid region is removed, the normal withstand voltage characteristic in a non-radiation environment is not excessively sacrificed, and the withstand voltage characteristics in the normal environment and the radiation environment are comprehensively ensured;
(3) the patterning process of the back barrier layer can be realized by patterned injection of GaN doping, and can also be completed by selective area epitaxy after GaN growth synchronous doping and selective etching, and the process feasibility is synchronous with the maturity of the GaN device process.
Drawings
FIG. 1 is a schematic illustration of the formation of an AlN nucleation layer and a GaN buffer layer on a substrate;
FIG. 2 is a schematic diagram of fabricating a selective back barrier buried layer;
FIG. 3 is a view showing the epitaxial growth of a non-doped GaN channel layer, AlxGa1-xSchematic diagrams of N barrier layer, p-type GaN and Mg layer;
FIG. 4 is a schematic diagram of forming a gate region;
FIG. 5 is a schematic illustration of deposition of a SiN surface passivation layer;
FIG. 6 is a schematic diagram of forming source/drain metal;
fig. 7 is a schematic diagram of the completed metal interconnect layer.
Detailed Description
The method for manufacturing the single event failure resistant high-voltage enhancement type GaN power HEMT device provided by the invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a manufacturing method of a high-voltage enhanced GaN power HEMT device capable of resisting single event failure, which comprises the following steps:
providing an epitaxial substrate as a substrate 01, wherein the epitaxial substrate can be Si or SiC; forming an AlN nucleation layer 02 and a GaN buffer layer 03 on the epitaxial substrate, as shown in fig. 1; the AlN nucleating layer 02 is 50-200 nm thick, and the GaN buffer layer 03 is 1-3 mu m thick;
there are two methods for manufacturing the selective back barrier buried layer shown in fig. 2: (1) forming a back barrier layer 04 on the GaN buffer layer 03; removing part of the back barrier layer to form a gate lower region 14; the area without the back barrier layer covers the grid electrode area which is manufactured in the later period and is deviated to the source electrode; (2) epitaxially growing an undoped GaN buffer layer 03, gluing and exposing a graphic window, and forming a back barrier layer of a region 14 below the gate by ion implantation doping of acceptor type impurities; completing the activation and lattice repair of the injected impurities through annealing;
continuing to epitaxially grow 1-2 mu m non-doped GaN channel layer 05 and 15-25 nm AlxGa1-xAn N barrier layer 06, a 100-200 nm p-type GaN Mg layer 15, as shown in FIG. 3; wherein Al isxGa1-xThe value of x in N is 15-25%; mg doping concentration of the p-type GaN Mg layer is 1019cm-3About 10 holes are formed in the concentration17cm-3Left and right;
coating glue and exposing the pattern window, and etching the p-type GaN-Mg layer outside the gate region by a dry method to form a gate region 09 as shown in FIG. 4; then SiN is deposited on the surface to be used as a SiN surface passivation layer 07 for passivating Al by etchingxGa1-xDamage caused by the surface of the N-barrier layer 06, as shown in fig. 5;
as shown in fig. 6, source metal 10 and drain metal 11 are deposited on the epitaxial substrate and source/drain electrodes are defined by photolithography, and the source metal 10 and the drain metal 11 can form ohmic contacts by using a gold-free process such as Ti/TiN; then, depositing grid metal 12 and defining grid contact metal by photoetching, wherein the metal contact of the p-type GaN, Mg grid can form Schottky contact property or ohmic contact property;
and manufacturing SiO2 or SiN on the surface to serve as an intermetallic dielectric layer 08, and finishing the subsequent metal interconnection layer 13, as shown in FIG. 7.
The structure of the GaN HEMT device manufactured by the method of the invention is shown in FIG. 7, and comprises a substrate 01, an AlN nucleating layer 02, a GaN buffer layer 03, a back barrier layer 04, a GaN channel layer 05 and AlxGa1-xThe structure comprises an N barrier layer 06, a gate region 09 formed by a p-type GaN or p-type AlGaN gate layer, a dielectric passivation layer 07, a source metal 10, a drain metal 11, a gate metal 12, an intermetallic dielectric layer 08 and a metal interconnection layer 13. Wherein the back barrier layer 04 adopts AlxGa1-xN or acceptor doped GaN, such as C-doped or Fe-doped or Mg-doped GaN. The back barrier layer is defined in a graphical mode, the back barrier layer below the gate region 09 is removed, and the back barrier layer below the drift region is reserved. The back barrier layer below the drift region can improve the transverse (grid-drain) uniformity of a high-voltage electric field, avoid punch-through source-drain punch-through current in advance, ensure the voltage resistance of the high-voltage device, and meanwhile, the removal of the back barrier layer below the grid region 09 can reduce the accumulation of holes below the grid when single particles are incident, so that the height of a peak electric field near the grid in the single particle effect is reduced, and the breakdown voltage of the GaN HEMT device in the single particle environment is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (6)
1. A manufacturing method of a high-voltage enhanced GaN power HEMT device resistant to single event failure is characterized by comprising the following steps:
providing an epitaxial substrate, and forming an AlN nucleating layer and a GaN buffer layer on the epitaxial substrate;
manufacturing a selective back barrier buried layer on the GaN buffer layer;
continuing epitaxial growth of non-doped GaN channel layer and AlxGa1-xN-barrier layer andp-type GaN is an Mg layer; wherein x is 15-25%;
etching the p-type GaN and Mg layers outside the grid region to form the grid region; SiN is deposited on the surface;
performing source/drain electrode metal deposition and defining a source/drain electrode by photoetching, and performing grid electrode metal deposition and defining a grid electrode by photoetching;
and finishing the metal interconnection process.
2. The method for fabricating the single event failure resistant high-voltage enhancement mode GaN power HEMT device as claimed in claim 1, wherein the method for fabricating the selected region back barrier layer on the GaN buffer layer comprises:
forming a back barrier layer on the GaN buffer layer;
removing part of the back barrier layer to form a region below the gate; the area without the back barrier layer covers the grid area and is biased to the source electrode;
and
epitaxially growing a non-doped GaN buffer layer, gluing and exposing a graphic window, and forming a back barrier layer in a region below the grid by ion implantation doping acceptor type impurities; activation of the implanted impurity and lattice repair are accomplished by annealing.
3. The method for fabricating the single event failure resistant high-voltage enhancement mode GaN power HEMT device as claimed in claim 2, wherein the forming a back barrier layer on the GaN buffer layer, removing part of the back barrier layer, and forming the region under the gate comprises:
synchronously doping acceptor type impurities during epitaxial growth to form a GaN: C or GaN: Fe or GaN: Mg back barrier layer with the impurity concentration of 1016～1017cm-3(ii) a Or epitaxially growing AlxGa1-xN is used as a back barrier layer, and x is 5 to 10 percent;
removing part of the back barrier layer by dry etching through gluing and exposing a pattern window; and then epitaxially and non-doping GaN fills the groove formed by etching below the grid.
4. The antithrombin of claim 1The manufacturing method of the particle-failure high-voltage enhanced GaN power HEMT device is characterized in that the thickness of the GaN channel layer is 1-2 mu m, and the Al isxGa1-xThe thickness of the N barrier layer is 15-25 nm, and the thickness of the p-type GaN-Mg layer is 100-200 nm.
5. The method for manufacturing the single event failure resistant high-voltage enhancement mode GaN power HEMT device as claimed in claim 1, wherein the epitaxial substrate is Si or SiC.
6. The method for manufacturing the single event failure resistant high-voltage enhancement mode GaN power HEMT device as claimed in claim 1, wherein the AlN nucleation layer has a thickness of 50-200 nm, and the GaN buffer layer has a thickness of 1-3 μm.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113594236A (en) * | 2021-07-28 | 2021-11-02 | 西安电子科技大学 | Enhanced gallium nitride high electron mobility transistor capable of improving single-particle burnout resistance |
| TWI797814B (en) * | 2020-11-06 | 2023-04-01 | 大陸商蘇州晶湛半導體有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783960A (en) * | 2017-01-11 | 2017-05-31 | 西安电子科技大学 | A kind of ladder p GaN enhanced AlGaNs/GaN HFETs |
| CN106981513A (en) * | 2017-04-24 | 2017-07-25 | 苏州能屋电子科技有限公司 | III group-III nitride polarization superjunction HEMT device and its preparation method based on high resistant cap |
| CN107170821A (en) * | 2017-03-29 | 2017-09-15 | 西安电子科技大学 | Floating type leakage field plate current apertures device and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783960A (en) * | 2017-01-11 | 2017-05-31 | 西安电子科技大学 | A kind of ladder p GaN enhanced AlGaNs/GaN HFETs |
| CN107170821A (en) * | 2017-03-29 | 2017-09-15 | 西安电子科技大学 | Floating type leakage field plate current apertures device and preparation method thereof |
| CN106981513A (en) * | 2017-04-24 | 2017-07-25 | 苏州能屋电子科技有限公司 | III group-III nitride polarization superjunction HEMT device and its preparation method based on high resistant cap |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI797814B (en) * | 2020-11-06 | 2023-04-01 | 大陸商蘇州晶湛半導體有限公司 | Semiconductor structure and manufacturing method thereof |
| CN113594236A (en) * | 2021-07-28 | 2021-11-02 | 西安电子科技大学 | Enhanced gallium nitride high electron mobility transistor capable of improving single-particle burnout resistance |
| CN113594236B (en) * | 2021-07-28 | 2024-04-26 | 西安电子科技大学 | Enhancement type gallium nitride high electron mobility transistor capable of improving single particle burnout resistance |
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